interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

aarch64: fix error recovery in aarch64_dpm_prepare 

Flush DTRRX with a dummy read if it's full, clear sticky errors
by writing CSE bit to EDRCR register.

Change-Id: Ia42ae9d3859ba6cbe892d48584e21acdd4e25c84
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky 2016-09-16 11:06:42 +02:00
parent 21a5c40430
commit f28d5ee71f
1 changed files with 8 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/target/aarch64.c
View File

@ -360,10 +360,14 @@ static int aarch64_dpm_prepare(struct arm_dpm *dpm)
if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
0xd5130400,
&dscr);
retval = mem_ap_read_u32(a8->armv8_common.debug_ap,
a8->armv8_common.debug_base + CPUV8_DBG_DTRRX, &dscr);
if (retval != ERROR_OK)
return retval;
/* Clear sticky error */
retval = mem_ap_write_u32(a8->armv8_common.debug_ap,
a8->armv8_common.debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
if (retval != ERROR_OK)
return retval;
}