From f1e20767bc9c78b994ecc18f1124e721b169013f Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Thu, 17 Nov 2022 11:27:18 -0800 Subject: [PATCH] target/riscv: 0.11, call handle_halt() after step This ensures that we populate the register cache and set target->state. Some RISC-V changes had upset the balance. Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5 Signed-off-by: Tim Newsome --- src/target/riscv/riscv-011.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 2c4a46e46..e38d85410 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -67,6 +67,8 @@ * to the target. Afterwards use cache_get... to read results. */ +static int handle_halt(struct target *target, bool announce); + #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) @@ -1192,7 +1194,7 @@ static int full_step(struct target *target, bool announce) return ERROR_FAIL; } } - return ERROR_OK; + return handle_halt(target, announce); } static uint64_t reg_cache_get(struct target *target, unsigned int number)