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mips32: fix typos 

Change-Id: Ibb98fe3da68bf670a5bb83600bb49647db8a4163
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-on: http://openocd.zylin.com/2338
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Antony Pavlov 2014-10-07 12:36:55 +04:00 committed by Spencer Oliver
parent fd25b3bcd1
commit f16b7a6d7e
2 changed files with 2 additions and 2 deletions
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2
src/target/mips32.c
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@ -289,7 +289,7 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s
mips32->common_magic = MIPS32_COMMON_MAGIC; mips32->common_magic = MIPS32_COMMON_MAGIC;
mips32->fast_data_area = NULL; mips32->fast_data_area = NULL;
/* has breakpoint/watchpint unit been scanned */ /* has breakpoint/watchpoint unit been scanned */
mips32->bp_scanned = 0; mips32->bp_scanned = 0;
mips32->data_break_list = NULL; mips32->data_break_list = NULL;

2
src/target/mips32.h
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@ -203,7 +203,7 @@ struct mips32_algorithm {
#define MIPS32_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */ #define MIPS32_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */
/** /**
* Cache operations definietions * Cache operations definitions
* Operation field is 5 bits long : * Operation field is 5 bits long :
* 1) bits 1..0 hold cache type * 1) bits 1..0 hold cache type
* 2) bits 4..2 hold operation code * 2) bits 4..2 hold operation code