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target/armv7m: change FPv4_SP and FPv5_SP/DP identifiers to uppercase 

Change-Id: Ia421a973e5fb4767715c9f95c91745f8ca1de1da
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/6177
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek 2021-04-22 08:40:02 +02:00
parent ab337d05f4
commit ef0aa38c10
4 changed files with 8 additions and 8 deletions
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2
src/rtos/FreeRTOS.c
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@ -438,7 +438,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
int cm4_fpu_enabled = 0; int cm4_fpu_enabled = 0;
struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
if (is_armv7m(armv7m_target)) { if (is_armv7m(armv7m_target)) {
if (armv7m_target->fp_feature == FPv4_SP) { if (armv7m_target->fp_feature == FPV4_SP) {
/* Found ARM v7m target which includes a FPU */ /* Found ARM v7m target which includes a FPU */
uint32_t cpacr; uint32_t cpacr;

2
src/rtos/nuttx.c
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@ -352,7 +352,7 @@ static int nuttx_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
bool cm4_fpu_enabled = false; bool cm4_fpu_enabled = false;
struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target); struct armv7m_common *armv7m_target = target_to_armv7m(rtos->target);
if (is_armv7m(armv7m_target)) { if (is_armv7m(armv7m_target)) {
if (armv7m_target->fp_feature == FPv4_SP) { if (armv7m_target->fp_feature == FPV4_SP) {
/* Found ARM v7m target which includes a FPU */ /* Found ARM v7m target which includes a FPU */
uint32_t cpacr; uint32_t cpacr;

6
src/target/armv7m.h
View File

@ -169,9 +169,9 @@ enum {
enum { enum {
FP_NONE = 0, FP_NONE = 0,
FPv4_SP, FPV4_SP,
FPv5_SP, FPV5_SP,
FPv5_DP, FPV5_DP,
}; };
#define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1) #define ARMV7M_NUM_CORE_REGS (ARMV7M_xPSR + 1)

6
src/target/cortex_m.c
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@ -2019,7 +2019,7 @@ int cortex_m_examine(struct target *target)
/* test for floating point feature on Cortex-M4 */ /* test for floating point feature on Cortex-M4 */
if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) { if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i); LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
armv7m->fp_feature = FPv4_SP; armv7m->fp_feature = FPV4_SP;
} }
} else if (i == 7 || i == 33 || i == 35 || i == 55) { } else if (i == 7 || i == 33 || i == 35 || i == 55) {
target_read_u32(target, MVFR0, &mvfr0); target_read_u32(target, MVFR0, &mvfr0);
@ -2028,10 +2028,10 @@ int cortex_m_examine(struct target *target)
/* test for floating point features on Cortex-M7 */ /* test for floating point features on Cortex-M7 */
if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) { if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i); LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i);
armv7m->fp_feature = FPv5_SP; armv7m->fp_feature = FPV5_SP;
} else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) { } else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i); LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i);
armv7m->fp_feature = FPv5_DP; armv7m->fp_feature = FPV5_DP;
} }
} else if (i == 0) { } else if (i == 0) {
/* Cortex-M0 does not support unaligned memory access */ /* Cortex-M0 does not support unaligned memory access */