David Brownell <david-b@pacbell.net>:
Minor updates to the Thumb2 disassembly: - Bugfixes: * Distinguish branch from misc via "!=" not "==" * MRS register shift is 8 bits (vs MSR being 16) - Format tweaks: * CPS needed tab (not space) * add commma before some shifts * add space after comma in LDM/STM * use ".W" width spec on various instructions git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@ -2080,7 +2080,7 @@ static int evaluate_cps_thumb(uint16_t opcode, uint32_t address,
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(opcode & 0x80) ? "BE" : "LE");
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(opcode & 0x80) ? "BE" : "LE");
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else /* ASSUME (opcode & 0x0fe0) == 0x0660 */
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else /* ASSUME (opcode & 0x0fe0) == 0x0660 */
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snprintf(instruction->text, 128,
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snprintf(instruction->text, 128,
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"0x%8.8" PRIx32 " 0x%4.4x \tCPSI%c %s%s%s",
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"0x%8.8" PRIx32 " 0x%4.4x \tCPSI%c\t%s%s%s",
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address, opcode,
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address, opcode,
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(opcode & 0x0010) ? 'D' : 'E',
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(opcode & 0x0010) ? 'D' : 'E',
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(opcode & 0x0004) ? "A" : "",
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(opcode & 0x0004) ? "A" : "",
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@ -2522,7 +2522,7 @@ static int t2ev_b_misc(uint32_t opcode, uint32_t address,
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case 0x4:
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case 0x4:
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goto undef;
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goto undef;
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case 0:
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case 0:
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if (((opcode >> 23) & 0x07) == 0x07)
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if (((opcode >> 23) & 0x07) != 0x07)
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return t2ev_cond_b(opcode, address, instruction, cp);
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return t2ev_cond_b(opcode, address, instruction, cp);
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if (opcode & (1 << 26))
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if (opcode & (1 << 26))
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goto undef;
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goto undef;
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@ -2541,7 +2541,7 @@ static int t2ev_b_misc(uint32_t opcode, uint32_t address,
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return t2ev_misc(opcode, address, instruction, cp);
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return t2ev_misc(opcode, address, instruction, cp);
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case 0x3e:
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case 0x3e:
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case 0x3f:
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case 0x3f:
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sprintf(cp, "MRS\tr%d, %s", (opcode >> 16) & 0x0f,
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sprintf(cp, "MRS\tr%d, %s", (opcode >> 8) & 0x0f,
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special_name(opcode & 0xff));
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special_name(opcode & 0xff));
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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@ -2560,6 +2560,7 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
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unsigned func;
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unsigned func;
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bool one = false;
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bool one = false;
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char *suffix = "";
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char *suffix = "";
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char *suffix2 = "";
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/* ARMv7-M: A5.3.2 Modified immediate constants */
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/* ARMv7-M: A5.3.2 Modified immediate constants */
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func = (opcode >> 11) & 0x0e;
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func = (opcode >> 11) & 0x0e;
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@ -2597,6 +2598,7 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
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mnemonic = "TST";
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mnemonic = "TST";
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one = true;
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one = true;
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suffix = "";
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suffix = "";
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suffix2 = ".W";
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rd = rn;
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rd = rn;
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} else {
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} else {
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instruction->type = ARM_AND;
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instruction->type = ARM_AND;
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@ -2612,6 +2614,7 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
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instruction->type = ARM_MOV;
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instruction->type = ARM_MOV;
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mnemonic = "MOV";
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mnemonic = "MOV";
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one = true;
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one = true;
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suffix2 = ".W";
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} else {
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} else {
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instruction->type = ARM_ORR;
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instruction->type = ARM_ORR;
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mnemonic = "ORR";
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mnemonic = "ORR";
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@ -2649,6 +2652,7 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
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} else {
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} else {
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instruction->type = ARM_ADD;
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instruction->type = ARM_ADD;
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mnemonic = "ADD";
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mnemonic = "ADD";
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suffix2 = ".W";
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}
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}
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break;
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break;
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case 10:
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case 10:
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@ -2670,21 +2674,24 @@ static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
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instruction->type = ARM_SUB;
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instruction->type = ARM_SUB;
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mnemonic = "SUB";
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mnemonic = "SUB";
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}
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}
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suffix2 = ".W";
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break;
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break;
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case 14:
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case 14:
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instruction->type = ARM_RSB;
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instruction->type = ARM_RSB;
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mnemonic = "RSB";
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mnemonic = "RSB";
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suffix2 = ".W";
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break;
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break;
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default:
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default:
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return ERROR_INVALID_ARGUMENTS;
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return ERROR_INVALID_ARGUMENTS;
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}
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}
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if (one)
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if (one)
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sprintf(cp, "%s\tr%d, #%d\t; %#8.8x",
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sprintf(cp, "%s%s\tr%d, #%d\t; %#8.8x",
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mnemonic, rd, immed, immed);
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mnemonic, suffix2 ,rd, immed, immed);
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else
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else
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sprintf(cp, "%s%s\tr%d, r%d, #%d\t; %#8.8x",
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sprintf(cp, "%s%s%s\tr%d, r%d, #%d\t; %#8.8x",
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mnemonic, suffix, rd, rn, immed, immed);
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mnemonic, suffix, suffix2,
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rd, rn, immed, immed);
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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@ -2959,13 +2966,13 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
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if (rn == 13 && t)
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if (rn == 13 && t)
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sprintf(cp, "POP\t");
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sprintf(cp, "POP\t");
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else
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else
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sprintf(cp, "LDM\tr%d%s, ", rn, t ? "!" : "");
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sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : "");
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break;
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break;
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case 4:
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case 4:
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if (rn == 13 && t)
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if (rn == 13 && t)
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sprintf(cp, "PUSH\t");
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sprintf(cp, "PUSH\t");
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else
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else
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sprintf(cp, "STM\tr%d%s, ", rn, t ? "!" : "");
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sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
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break;
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break;
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case 5:
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case 5:
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sprintf(cp, "LDMB\tr%d%s, ", rn, t ? "!" : "");
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sprintf(cp, "LDMB\tr%d%s, ", rn, t ? "!" : "");
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@ -2980,7 +2987,7 @@ static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
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if ((registers & 1) == 0)
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if ((registers & 1) == 0)
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continue;
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continue;
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registers &= ~1;
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registers &= ~1;
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sprintf(cp, "r%d%s", t, registers ? "," : "");
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sprintf(cp, "r%d%s", t, registers ? ", " : "");
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cp = strchr(cp, 0);
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cp = strchr(cp, 0);
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}
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}
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*cp++ = '}';
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*cp++ = '}';
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@ -3139,7 +3146,7 @@ shift:
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suffix = "ROR";
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suffix = "ROR";
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break;
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break;
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}
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}
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sprintf(cp, " %s #%d", suffix, immed ? immed : 32);
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sprintf(cp, ", %s #%d", suffix, immed ? immed : 32);
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return ERROR_OK;
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return ERROR_OK;
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two:
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two:
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