Cortex-M3: minor breakpoint cleanup
Shrink some lines, add some comments, simplify some tests. During debug startup, log the core revision level too. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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@ -42,6 +42,9 @@
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/* NOTE: most of this should work fine for the Cortex-M1 and
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/* NOTE: most of this should work fine for the Cortex-M1 and
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* Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
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* Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
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* Some differences: M0/M1 doesn't have FBP remapping or the
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* DWT tracing/profiling support. (So the cycle counter will
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* not be usable; the other stuff isn't currently used here.)
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*
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*
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* Although there are some workarounds for errata seen only in r0p0
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* Although there are some workarounds for errata seen only in r0p0
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* silicon, such old parts are hard to find and thus not much tested
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* silicon, such old parts are hard to find and thus not much tested
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@ -579,7 +582,7 @@ static void cortex_m3_enable_breakpoints(struct target *target)
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/* set any pending breakpoints */
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/* set any pending breakpoints */
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while (breakpoint)
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while (breakpoint)
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{
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{
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if (breakpoint->set == 0)
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if (!breakpoint->set)
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cortex_m3_set_breakpoint(target, breakpoint);
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cortex_m3_set_breakpoint(target, breakpoint);
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breakpoint = breakpoint->next;
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breakpoint = breakpoint->next;
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}
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}
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@ -936,16 +939,25 @@ cortex_m3_set_breakpoint(struct target *target, struct breakpoint *breakpoint)
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else if (breakpoint->type == BKPT_SOFT)
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else if (breakpoint->type == BKPT_SOFT)
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{
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{
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uint8_t code[4];
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uint8_t code[4];
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/* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
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* semihosting; don't use that. Otherwise the BKPT
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* parameter is arbitrary.
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*/
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buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
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buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
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if ((retval = target_read_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, breakpoint->orig_instr)) != ERROR_OK)
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retval = target_read_memory(target,
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{
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breakpoint->address & 0xFFFFFFFE,
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breakpoint->length, 1,
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breakpoint->orig_instr);
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if (retval != ERROR_OK)
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return retval;
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return retval;
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}
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retval = target_write_memory(target,
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if ((retval = target_write_memory(target, breakpoint->address & 0xFFFFFFFE, breakpoint->length, 1, code)) != ERROR_OK)
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breakpoint->address & 0xFFFFFFFE,
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{
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breakpoint->length, 1,
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code);
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if (retval != ERROR_OK)
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return retval;
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return retval;
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}
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breakpoint->set = true;
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breakpoint->set = 0x11; /* Any nice value but 0 */
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}
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}
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LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
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LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
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@ -1008,7 +1020,7 @@ cortex_m3_unset_breakpoint(struct target *target, struct breakpoint *breakpoint)
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}
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}
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}
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}
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}
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}
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breakpoint->set = 0;
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breakpoint->set = false;
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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@ -1187,7 +1199,7 @@ cortex_m3_unset_watchpoint(struct target *target, struct watchpoint *watchpoint)
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target_write_u32(target, comparator->dwt_comparator_address + 8,
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target_write_u32(target, comparator->dwt_comparator_address + 8,
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comparator->function);
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comparator->function);
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watchpoint->set = 0;
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watchpoint->set = false;
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return ERROR_OK;
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return ERROR_OK;
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}
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}
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@ -1273,7 +1285,7 @@ static void cortex_m3_enable_watchpoints(struct target *target)
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/* set any pending watchpoints */
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/* set any pending watchpoints */
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while (watchpoint)
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while (watchpoint)
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{
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{
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if (watchpoint->set == 0)
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if (!watchpoint->set)
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cortex_m3_set_watchpoint(target, watchpoint);
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cortex_m3_set_watchpoint(target, watchpoint);
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watchpoint = watchpoint->next;
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watchpoint = watchpoint->next;
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}
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}
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@ -1647,7 +1659,8 @@ static int cortex_m3_examine(struct target *target)
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return retval;
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return retval;
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if (((cpuid >> 4) & 0xc3f) == 0xc23)
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if (((cpuid >> 4) & 0xc3f) == 0xc23)
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LOG_DEBUG("CORTEX-M3 processor detected");
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LOG_DEBUG("Cortex-M3 r%dp%d processor detected",
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(cpuid >> 20) & 0xf, (cpuid >> 0) & 0xf);
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LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
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LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
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/* NOTE: FPB and DWT are both optional. */
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/* NOTE: FPB and DWT are both optional. */
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