- fixed endianness handling in arm7_9_read_core_reg (thanks to Magnus Lundin for reporting this)
- correctly handle ft2232_device_desc and ft2232_serial when both are given at the same time git-svn-id: svn://svn.berlios.de/openocd/trunk@104 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@ -994,7 +994,8 @@ int ft2232_init(void)
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WARNING("can't open by device description and serial number, giving precedence to serial");
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ft2232_device_desc = NULL;
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}
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else if (ft2232_device_desc)
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if (ft2232_device_desc)
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{
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openex_string = ft2232_device_desc;
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openex_flags = FT_OPEN_BY_DESCRIPTION;
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@ -1509,6 +1509,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
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int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
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{
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u32* reg_p[16];
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u32 value;
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int retval;
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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@ -1533,7 +1534,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
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if ((num >= 0) && (num <= 15))
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{
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/* read a normal core register */
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reg_p[num] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value;
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reg_p[num] = &value;
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arm7_9->read_core_regs(target, 1 << num, reg_p);
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}
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@ -1545,17 +1546,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
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armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
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int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
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arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, spsr);
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}
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
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if ((mode != ARMV4_5_MODE_ANY)
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&& (mode != armv4_5->core_mode)
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&& (reg_mode != ARMV4_5_MODE_ANY)) {
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/* restore processor mode (mask T bit) */
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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arm7_9->read_xpsr(target, &value, spsr);
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}
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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@ -1563,6 +1554,17 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
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ERROR("JTAG failure");
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exit(-1);
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}
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
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buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
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if ((mode != ARMV4_5_MODE_ANY)
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&& (mode != armv4_5->core_mode)
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&& (reg_mode != ARMV4_5_MODE_ANY)) {
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/* restore processor mode (mask T bit) */
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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}
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return ERROR_OK;
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@ -1768,7 +1770,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
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if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
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{
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ERROR("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
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WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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@ -1933,7 +1935,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
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if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
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{
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ERROR("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
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WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
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arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
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