target/armv4_5: use c99 array designator to init arm_core_regs[]
During code analysis and development, counting again and again the lines to find the index of the register is a boring error-prone brain-damaging activity. Use the c99 syntax and add once forever the array designators to specify the index values. The code behavior is not changed. Change-Id: I2c70f70794475679efb91a8dfadc00f50715bd3f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/5256 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
Tomas Vanek
parent
49d71d06d1
commit
e8d4074cf8
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@ -274,24 +274,24 @@ static const struct {
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* correspond to r0..r7, and the fifteenth to PC, so that callers
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* don't need to map them.
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*/
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{ .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
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{ .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
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{ .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
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{ .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
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{ .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
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{ .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
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{ .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
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{ .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
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[0] = { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
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[1] = { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
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[2] = { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
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[3] = { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
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[4] = { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
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[5] = { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
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[6] = { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
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[7] = { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
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/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
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* them as MODE_ANY creates special cases. (ANY means
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* "not mapped" elsewhere; here it's "everything but FIQ".)
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*/
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{ .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
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{ .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
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{ .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
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{ .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
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{ .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
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[8] = { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
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[9] = { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
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[10] = { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
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[11] = { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
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[12] = { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
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/* Historical GDB mapping of indices:
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* - 13-14 are sp and lr, but banked counterparts are used
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@ -300,47 +300,47 @@ static const struct {
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*/
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/* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
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{ .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
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{ .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
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[13] = { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
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[14] = { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
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/* guaranteed to be at index 15 */
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{ .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
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{ .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
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{ .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
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{ .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
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{ .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
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{ .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
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[15] = { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
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[16] = { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
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[17] = { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
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[18] = { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
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[19] = { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
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[20] = { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
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{ .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
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{ .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
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[21] = { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
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[22] = { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
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{ .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
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{ .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
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[23] = { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
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[24] = { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
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{ .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
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{ .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
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[25] = { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
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[26] = { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
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{ .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
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{ .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
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[27] = { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
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[28] = { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
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{ .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
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{ .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
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[29] = { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
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[30] = { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
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{ .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
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{ .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
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{ .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
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{ .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
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{ .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
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{ .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
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[31] = { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
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[32] = { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
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[33] = { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
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[34] = { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
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[35] = { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
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[36] = { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
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/* These are only used for GDB target description, banked registers are accessed instead */
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{ .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
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{ .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
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[37] = { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
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[38] = { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
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/* These exist only when the Security Extension (TrustZone) is present */
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{ .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
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{ .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
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{ .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
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[39] = { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
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[40] = { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
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[41] = { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
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};
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