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ARM semihosting: work with both low and high vectors 

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
Nicolas Pitre 2009-12-05 01:01:54 -05:00 committed by David Brownell
parent 899c9975e7
commit e8599cc3d8
1 changed files with 4 additions and 6 deletions
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10
src/target/arm_semihosting.c
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@ -414,18 +414,16 @@ static int do_semihosting(struct target *target)
int arm_semihosting(struct target *target, int *retval) int arm_semihosting(struct target *target, int *retval)
{ {
struct arm *arm = target_to_arm(target); struct arm *arm = target_to_arm(target);
uint32_t lr, spsr; uint32_t pc, lr, spsr;
struct reg *r; struct reg *r;
if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC) if (!arm->is_semihosting || arm->core_mode != ARM_MODE_SVC)
return 0; return 0;
/* Check for PC == 8: Supervisor Call vector /* Check for PC == 0x00000008 or 0xffff0008: Supervisor Call vector. */
* REVISIT: assumes low exception vectors, not hivecs...
* safer to test "was this entry from a vector catch".
*/
r = arm->core_cache->reg_list + 15; r = arm->core_cache->reg_list + 15;
if (buf_get_u32(r->value, 0, 32) != 0x08) pc = buf_get_u32(r->value, 0, 32);
if (pc != 0x00000008 && pc != 0xffff0008)
return 0; return 0;
r = arm_reg_current(arm, 14); r = arm_reg_current(arm, 14);