diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 8d54a50fb..fee1a2485 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -736,7 +736,7 @@ static int jtag_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
 	return retval;
 }
 
-static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
+static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned int reg,
 		uint32_t *data)
 {
 	int retval = jtag_limit_queue_size(dap);
@@ -749,7 +749,7 @@ static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
 	return retval;
 }
 
-static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
+static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned int reg,
 		uint32_t data)
 {
 	int retval = jtag_limit_queue_size(dap);
@@ -763,7 +763,7 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
 }
 
 /** Select the AP register bank */
-static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
+static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned int reg)
 {
 	int retval;
 	struct adiv5_dap *dap = ap->dap;
@@ -818,7 +818,7 @@ static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
 	return ERROR_OK;
 }
 
-static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
+static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned int reg,
 		uint32_t *data)
 {
 	int retval = jtag_limit_queue_size(ap->dap);
@@ -840,7 +840,7 @@ static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
 	return retval;
 }
 
-static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg,
+static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned int reg,
 		uint32_t data)
 {
 	int retval = jtag_limit_queue_size(ap->dap);
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 123100588..dda1b0674 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -485,7 +485,7 @@ static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
 	return check_sync(dap);
 }
 
-static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
+static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned int reg,
 		uint32_t *data)
 {
 	int retval = swd_check_reconnect(dap);
@@ -499,7 +499,7 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
 	return swd_queue_dp_read_inner(dap, reg, data);
 }
 
-static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
+static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned int reg,
 		uint32_t data)
 {
 	const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
@@ -517,7 +517,7 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 }
 
 /** Select the AP register bank */
-static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
+static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned int reg)
 {
 	int retval;
 	struct adiv5_dap *dap = ap->dap;
@@ -567,7 +567,7 @@ static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 	return ERROR_OK;
 }
 
-static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
+static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned int reg,
 		uint32_t *data)
 {
 	struct adiv5_dap *dap = ap->dap;
@@ -592,7 +592,7 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
 	return check_sync(dap);
 }
 
-static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
+static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned int reg,
 		uint32_t data)
 {
 	struct adiv5_dap *dap = ap->dap;
diff --git a/src/target/arc.c b/src/target/arc.c
index 72e4d918d..28ce93947 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -516,7 +516,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 		unsigned long i = 0;
 		struct reg_cache *reg_cache = target->reg_cache;
 		while (reg_cache) {
-			for (unsigned j = 0; j < reg_cache->num_regs; j++, i++)
+			for (unsigned int j = 0; j < reg_cache->num_regs; j++, i++)
 				(*reg_list)[i] =  &reg_cache->reg_list[j];
 			reg_cache = reg_cache->next;
 		}
@@ -527,7 +527,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
 		unsigned long gdb_reg_number = 0;
 		struct reg_cache *reg_cache = target->reg_cache;
 		while (reg_cache) {
-			for (unsigned j = 0;
+			for (unsigned int j = 0;
 				 j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg;
 				 j++) {
 				if (reg_cache->reg_list[j].exist) {
diff --git a/src/target/arm.h b/src/target/arm.h
index 0de322a5a..79ec99d11 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -143,8 +143,8 @@ enum {
 	ARM_VFP_V3_FPSCR,
 };
 
-const char *arm_mode_name(unsigned psr_mode);
-bool is_arm_mode(unsigned psr_mode);
+const char *arm_mode_name(unsigned int psr_mode);
+bool is_arm_mode(unsigned int psr_mode);
 
 /** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
 enum arm_state {
@@ -325,7 +325,7 @@ int arm_blank_check_memory(struct target *target,
 		struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
 
 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
-struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
-struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
+struct reg *arm_reg_current(struct arm *arm, unsigned int regnum);
+struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum);
 
 #endif /* OPENOCD_TARGET_ARM_H */
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 43790c737..c583a2ebd 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -478,7 +478,7 @@ static int arm11_resume(struct target *target, int current,
 	/* activate all breakpoints */
 	if (true) {
 		struct breakpoint *bp;
-		unsigned brp_num = 0;
+		unsigned int brp_num = 0;
 
 		for (bp = target->breakpoints; bp; bp = bp->next) {
 			struct arm11_sc7_action brp[2];
diff --git a/src/target/arm11.h b/src/target/arm11.h
index 1f56f7bba..40a3f9024 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -39,7 +39,7 @@ struct arm11_common {
 	/** Debug module state. */
 	struct arm_dpm dpm;
 	struct arm11_sc7_action *bpwp_actions;
-	unsigned bpwp_n;
+	unsigned int bpwp_n;
 
 	size_t brp;			/**< Number of Breakpoint Register Pairs from DIDR	*/
 	size_t free_brps;		/**< Number of breakpoints allocated */
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index b66f88618..36325911a 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -567,8 +567,8 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
 	chain5_fields[2].in_value               = NULL;
 
 	uint8_t *readies;
-	unsigned readies_num = count;
-	unsigned bytes = sizeof(*readies)*readies_num;
+	unsigned int readies_num = count;
+	unsigned int bytes = sizeof(*readies) * readies_num;
 
 	readies = malloc(bytes);
 	if (!readies) {
@@ -592,7 +592,7 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
 
 	int retval = jtag_execute_queue();
 	if (retval == ERROR_OK) {
-		unsigned error_count = 0;
+		unsigned int error_count = 0;
 
 		for (size_t i = 0; i < readies_num; i++) {
 			if (readies[i] != 1)
@@ -1042,7 +1042,7 @@ static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
  * and watchpoint operations instead of running them right away.  Since we
  * pre-allocated our vector, we don't need to worry about space.
  */
-static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
+static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
 	uint32_t addr, uint32_t control)
 {
 	struct arm11_common *arm11 = dpm_to_arm11(dpm);
@@ -1079,7 +1079,7 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 	return ERROR_OK;
 }
 
-static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
+static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
 {
 	struct arm11_common *arm11 = dpm_to_arm11(dpm);
 	struct arm11_sc7_action *action;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 3bacfaefd..7e31306b6 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -821,9 +821,9 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
 		else if (strcmp(CMD_ARGV[0], "none") == 0) {
 			/* do nothing */
 		} else {
-			for (unsigned i = 0; i < CMD_ARGC; i++) {
+			for (unsigned int i = 0; i < CMD_ARGC; i++) {
 				/* go through list of vectors */
-				unsigned j;
+				unsigned int j;
 				for (j = 0; arm9tdmi_vectors[j].name; j++) {
 					if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0) {
 						vector_catch_value |= arm9tdmi_vectors[j].value;
@@ -850,7 +850,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
 	}
 
 	/* output current settings */
-	for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) {
+	for (unsigned int i = 0; arm9tdmi_vectors[i].name; i++) {
 		command_print(CMD, "%s: %s", arm9tdmi_vectors[i].name,
 			(vector_catch_value & arm9tdmi_vectors[i].value)
 				? "catch" : "don't catch");
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 92c3dbc3a..ebd2752bd 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -454,17 +454,17 @@ struct dap_ops {
 	int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
 
 	/** DP register read. */
-	int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
+	int (*queue_dp_read)(struct adiv5_dap *dap, unsigned int reg,
 			uint32_t *data);
 	/** DP register write. */
-	int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
+	int (*queue_dp_write)(struct adiv5_dap *dap, unsigned int reg,
 			uint32_t data);
 
 	/** AP register read. */
-	int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
+	int (*queue_ap_read)(struct adiv5_ap *ap, unsigned int reg,
 			uint32_t *data);
 	/** AP register write. */
-	int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
+	int (*queue_ap_write)(struct adiv5_ap *ap, unsigned int reg,
 			uint32_t data);
 
 	/** AP operation abort. */
@@ -553,7 +553,7 @@ static inline int dap_send_sequence(struct adiv5_dap *dap,
  * @return ERROR_OK for success, else a fault code.
  */
 static inline int dap_queue_dp_read(struct adiv5_dap *dap,
-		unsigned reg, uint32_t *data)
+		unsigned int reg, uint32_t *data)
 {
 	assert(dap->ops);
 	return dap->ops->queue_dp_read(dap, reg, data);
@@ -571,7 +571,7 @@ static inline int dap_queue_dp_read(struct adiv5_dap *dap,
  * @return ERROR_OK for success, else a fault code.
  */
 static inline int dap_queue_dp_write(struct adiv5_dap *dap,
-		unsigned reg, uint32_t data)
+		unsigned int reg, uint32_t data)
 {
 	assert(dap->ops);
 	return dap->ops->queue_dp_write(dap, reg, data);
@@ -588,7 +588,7 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap,
  * @return ERROR_OK for success, else a fault code.
  */
 static inline int dap_queue_ap_read(struct adiv5_ap *ap,
-		unsigned reg, uint32_t *data)
+		unsigned int reg, uint32_t *data)
 {
 	assert(ap->dap->ops);
 	if (ap->refcount == 0) {
@@ -608,7 +608,7 @@ static inline int dap_queue_ap_read(struct adiv5_ap *ap,
  * @return ERROR_OK for success, else a fault code.
  */
 static inline int dap_queue_ap_write(struct adiv5_ap *ap,
-		unsigned reg, uint32_t data)
+		unsigned int reg, uint32_t data)
 {
 	assert(ap->dap->ops);
 	if (ap->refcount == 0) {
@@ -659,7 +659,7 @@ static inline int dap_sync(struct adiv5_dap *dap)
 	return ERROR_OK;
 }
 
-static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
+static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned int reg,
 				     uint32_t *value)
 {
 	int retval;
@@ -671,7 +671,7 @@ static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
 	return dap_run(dap);
 }
 
-static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
+static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned int reg,
 				       uint32_t mask, uint32_t value, int timeout)
 {
 	assert(timeout > 0);
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 5c52ad899..8619f8f82 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -114,7 +114,7 @@ static int evaluate_pld(uint32_t opcode,
 	if ((opcode & 0x0d30f000) == 0x0510f000) {
 		uint8_t rn;
 		uint8_t u;
-		unsigned offset;
+		unsigned int offset;
 
 		instruction->type = ARM_PLD;
 		rn = (opcode & 0xf0000) >> 16;
@@ -701,9 +701,9 @@ static int evaluate_load_store(uint32_t opcode,
 
 static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
 {
-	unsigned rm = (opcode >> 0) & 0xf;
-	unsigned rd = (opcode >> 12) & 0xf;
-	unsigned rn = (opcode >> 16) & 0xf;
+	unsigned int rm = (opcode >> 0) & 0xf;
+	unsigned int rd = (opcode >> 12) & 0xf;
+	unsigned int rn = (opcode >> 16) & 0xf;
 	char *type, *rot;
 
 	switch ((opcode >> 24) & 0x3) {
@@ -892,7 +892,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
 
 	/* multiplies */
 	if ((opcode & 0x01f00080) == 0x01000000) {
-		unsigned rn = (opcode >> 12) & 0xf;
+		unsigned int rn = (opcode >> 12) & 0xf;
 
 		if (rn != 0xf)
 			sprintf(cp, "SML%cD%s%s\tr%d, r%d, r%d, r%d",
@@ -925,7 +925,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
 		return ERROR_OK;
 	}
 	if ((opcode & 0x01f00000) == 0x01500000) {
-		unsigned rn = (opcode >> 12) & 0xf;
+		unsigned int rn = (opcode >> 12) & 0xf;
 
 		switch (opcode & 0xc0) {
 			case 3:
@@ -1001,8 +1001,8 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
 			return ERROR_OK;
 	}
 	if (mnemonic) {
-		unsigned rm = (opcode >> 0) & 0xf;
-		unsigned rd = (opcode >> 12) & 0xf;
+		unsigned int rm = (opcode >> 0) & 0xf;
+		unsigned int rd = (opcode >> 12) & 0xf;
 
 		sprintf(cp, "%s%s\tr%d, r%d", mnemonic, COND(opcode), rm, rd);
 		return ERROR_OK;
@@ -2747,7 +2747,7 @@ static int evaluate_cond_branch_thumb(uint16_t opcode,
 static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
 			     struct arm_instruction *instruction)
 {
-	unsigned offset;
+	unsigned int offset;
 
 	/* added in Thumb2 */
 	offset = (opcode >> 3) & 0x1f;
@@ -2858,7 +2858,7 @@ static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
 static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
 				 struct arm_instruction *instruction)
 {
-	unsigned cond = (opcode >> 4) & 0x0f;
+	unsigned int cond = (opcode >> 4) & 0x0f;
 	char *x = "", *y = "", *z = "";
 
 	if (opcode & 0x01)
diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index 1be567475..8317da997 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -171,7 +171,7 @@ struct arm_instruction {
 	uint32_t opcode;
 
 	/* return value ... Thumb-2 sizes vary */
-	unsigned instruction_size;
+	unsigned int instruction_size;
 
 	union {
 		struct arm_b_bl_bx_blx_instr b_bl_bx_blx;
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 94e91ad6c..318d5afec 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -167,7 +167,7 @@ int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 }
 
 /* Read 64bit VFP registers */
-static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
+static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 {
 	int retval = ERROR_FAIL;
 	uint32_t value_r0, value_r1;
@@ -205,7 +205,7 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 }
 
 /* just read the register -- rely on the core mode being right */
-int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
+int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 {
 	uint32_t value;
 	int retval;
@@ -272,7 +272,7 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 }
 
 /* Write 64bit VFP registers */
-static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
+static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 {
 	int retval = ERROR_FAIL;
 	uint32_t value_r0 = buf_get_u32(r->value, 0, 32);
@@ -308,7 +308,7 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum
 }
 
 /* just write the register -- rely on the core mode being right */
-static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
+static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 {
 	int retval;
 	uint32_t value = buf_get_u32(r->value, 0, 32);
@@ -386,7 +386,7 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm)
 		return retval;
 
 	/* read R0 and R1 first (it's used for scratch), then CPSR */
-	for (unsigned i = 0; i < 2; i++) {
+	for (unsigned int i = 0; i < 2; i++) {
 		r = arm->core_cache->reg_list + i;
 		if (!r->valid) {
 			retval = arm_dpm_read_reg(dpm, r, i);
@@ -404,7 +404,7 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm)
 	arm_set_cpsr(arm, cpsr);
 
 	/* REVISIT we can probably avoid reading R1..R14, saving time... */
-	for (unsigned i = 2; i < 16; i++) {
+	for (unsigned int i = 2; i < 16; i++) {
 		r = arm_reg_current(arm, i);
 		if (r->valid)
 			continue;
@@ -501,7 +501,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 	 * cope with the hand-crafted breakpoint code.
 	 */
 	if (arm->target->type->add_breakpoint == dpm_add_breakpoint) {
-		for (unsigned i = 0; i < dpm->nbp; i++) {
+		for (unsigned int i = 0; i < dpm->nbp; i++) {
 			struct dpm_bp *dbp = dpm->dbp + i;
 			struct breakpoint *bp = dbp->bp;
 
@@ -513,7 +513,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 	}
 
 	/* enable/disable watchpoints */
-	for (unsigned i = 0; i < dpm->nwp; i++) {
+	for (unsigned int i = 0; i < dpm->nwp; i++) {
 		struct dpm_wp *dwp = dpm->dwp + i;
 		struct watchpoint *wp = dwp->wp;
 
@@ -538,9 +538,9 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 		did_write = false;
 
 		/* check everything except our scratch registers R0 and R1 */
-		for (unsigned i = 2; i < cache->num_regs; i++) {
+		for (unsigned int i = 2; i < cache->num_regs; i++) {
 			struct arm_reg *r;
-			unsigned regnum;
+			unsigned int regnum;
 
 			/* also skip PC, CPSR, and non-dirty */
 			if (i == 15)
@@ -625,7 +625,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 	arm->pc->dirty = false;
 
 	/* flush R0 and R1 (our scratch registers) */
-	for (unsigned i = 0; i < 2; i++) {
+	for (unsigned int i = 0; i < 2; i++) {
 		retval = dpm_write_reg(dpm, &cache->reg_list[i], i);
 		if (retval != ERROR_OK)
 			goto done;
@@ -643,7 +643,7 @@ done:
  * or MODE_ANY.
  */
 static enum arm_mode dpm_mapmode(struct arm *arm,
-	unsigned num, enum arm_mode mode)
+	unsigned int num, enum arm_mode mode)
 {
 	enum arm_mode amode = arm->core_mode;
 
@@ -793,7 +793,7 @@ static int arm_dpm_full_context(struct target *target)
 		 * Pick some mode with unread registers and read them all.
 		 * Repeat until done.
 		 */
-		for (unsigned i = 0; i < cache->num_regs; i++) {
+		for (unsigned int i = 0; i < cache->num_regs; i++) {
 			struct arm_reg *r;
 
 			if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
@@ -921,7 +921,7 @@ static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
 	if (bp->type == BKPT_SOFT)
 		LOG_DEBUG("using HW bkpt, not SW...");
 
-	for (unsigned i = 0; i < dpm->nbp; i++) {
+	for (unsigned int i = 0; i < dpm->nbp; i++) {
 		if (!dpm->dbp[i].bp) {
 			retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
 					bp->address, bp->length);
@@ -940,7 +940,7 @@ static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
 	struct arm_dpm *dpm = arm->dpm;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
-	for (unsigned i = 0; i < dpm->nbp; i++) {
+	for (unsigned int i = 0; i < dpm->nbp; i++) {
 		if (dpm->dbp[i].bp == bp) {
 			dpm->dbp[i].bp = NULL;
 			dpm->dbp[i].bpwp.dirty = true;
@@ -954,7 +954,7 @@ static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
 	return retval;
 }
 
-static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
+static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
 	struct watchpoint *wp)
 {
 	int retval;
@@ -997,7 +997,7 @@ static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
 	int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 
 	if (dpm->bpwp_enable) {
-		for (unsigned i = 0; i < dpm->nwp; i++) {
+		for (unsigned int i = 0; i < dpm->nwp; i++) {
 			if (!dpm->dwp[i].wp) {
 				retval = dpm_watchpoint_setup(dpm, i, wp);
 				break;
@@ -1014,7 +1014,7 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
 	struct arm_dpm *dpm = arm->dpm;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
-	for (unsigned i = 0; i < dpm->nwp; i++) {
+	for (unsigned int i = 0; i < dpm->nwp; i++) {
 		if (dpm->dwp[i].wp == wp) {
 			dpm->dwp[i].wp = NULL;
 			dpm->dwp[i].bpwp.dirty = true;
@@ -1161,7 +1161,7 @@ int arm_dpm_initialize(struct arm_dpm *dpm)
 {
 	/* Disable all breakpoints and watchpoints at startup. */
 	if (dpm->bpwp_disable) {
-		unsigned i;
+		unsigned int i;
 
 		for (i = 0; i < dpm->nbp; i++) {
 			dpm->dbp[i].bpwp.number = i;
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index 2da463111..16c801ea5 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -19,7 +19,7 @@
  */
 
 struct dpm_bpwp {
-	unsigned number;
+	unsigned int number;
 	uint32_t address;
 	uint32_t control;
 	/* true if hardware state needs flushing */
@@ -109,7 +109,7 @@ struct arm_dpm {
 			uint32_t opcode, uint64_t *data);
 
 	struct reg *(*arm_reg_current)(struct arm *arm,
-			unsigned regnum);
+			unsigned int regnum);
 
 	/* BREAKPOINT/WATCHPOINT SUPPORT */
 
@@ -119,7 +119,7 @@ struct arm_dpm {
 	 * must currently be disabled.  Indices 0..15 are used for
 	 * breakpoints; indices 16..31 are for watchpoints.
 	 */
-	int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
+	int (*bpwp_enable)(struct arm_dpm *dpm, unsigned int index_value,
 			uint32_t addr, uint32_t control);
 
 	/**
@@ -127,15 +127,15 @@ struct arm_dpm {
 	 * hardware control registers.  Indices are the same ones
 	 * accepted by bpwp_enable().
 	 */
-	int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
+	int (*bpwp_disable)(struct arm_dpm *dpm, unsigned int index_value);
 
 	/* The breakpoint and watchpoint arrays are private to the
 	 * DPM infrastructure.  There are nbp indices in the dbp
 	 * array.  There are nwp indices in the dwp array.
 	 */
 
-	unsigned nbp;
-	unsigned nwp;
+	unsigned int nbp;
+	unsigned int nwp;
 	struct dpm_bp *dbp;
 	struct dpm_wp *dwp;
 
@@ -158,7 +158,7 @@ struct arm_dpm {
 int arm_dpm_setup(struct arm_dpm *dpm);
 int arm_dpm_initialize(struct arm_dpm *dpm);
 
-int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
+int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum);
 int arm_dpm_read_current_registers(struct arm_dpm *dpm);
 int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
 
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index ae89762e1..c1836bc7a 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -168,9 +168,9 @@ static const struct {
 };
 
 /** Map PSR mode bits to the name of an ARM processor operating mode. */
-const char *arm_mode_name(unsigned psr_mode)
+const char *arm_mode_name(unsigned int psr_mode)
 {
-	for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
 		if (arm_mode_data[i].psr == psr_mode)
 			return arm_mode_data[i].name;
 	}
@@ -179,9 +179,9 @@ const char *arm_mode_name(unsigned psr_mode)
 }
 
 /** Return true iff the parameter denotes a valid ARM processor mode. */
-bool is_arm_mode(unsigned psr_mode)
+bool is_arm_mode(unsigned int psr_mode)
 {
-	for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
 		if (arm_mode_data[i].psr == psr_mode)
 			return true;
 	}
@@ -272,8 +272,8 @@ static const struct {
 	 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
 	 * (Exception modes have both CPSR and SPSR registers ...)
 	 */
-	unsigned cookie;
-	unsigned gdb_index;
+	unsigned int cookie;
+	unsigned int gdb_index;
 	enum arm_mode mode;
 } arm_core_regs[] = {
 	/* IMPORTANT:  we guarantee that the first eight cached registers
@@ -499,7 +499,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
  *	However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
  *	CPSR (arm->cpsr) is also not mapped.
  */
-struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
+struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
 {
 	struct reg *r;
 
@@ -840,7 +840,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 
 	regs = arm->core_cache->reg_list;
 
-	for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
+	for (unsigned int mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
 		const char *name;
 		char *sep = "\n";
 		char *shadow = "";
@@ -875,11 +875,11 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 			sep, name, shadow);
 
 		/* display N rows of up to 4 registers each */
-		for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
+		for (unsigned int i = 0; i < arm_mode_data[mode].n_indices; ) {
 			char output[80];
 			int output_len = 0;
 
-			for (unsigned j = 0; j < 4; j++, i++) {
+			for (unsigned int j = 0; j < 4; j++, i++) {
 				uint32_t value;
 				struct reg *reg = regs;
 
@@ -1750,7 +1750,7 @@ cleanup:
 static int arm_full_context(struct target *target)
 {
 	struct arm *arm = target_to_arm(target);
-	unsigned num_regs = arm->core_cache->num_regs;
+	unsigned int num_regs = arm->core_cache->num_regs;
 	struct reg *reg = arm->core_cache->reg_list;
 	int retval = ERROR_OK;
 
diff --git a/src/target/armv7a_cache_l2x.h b/src/target/armv7a_cache_l2x.h
index d5f1a6f0e..ea726ec58 100644
--- a/src/target/armv7a_cache_l2x.h
+++ b/src/target/armv7a_cache_l2x.h
@@ -122,16 +122,16 @@ struct outer_cache_fns {
 	void (*resume)(void);
 
 	/* This is an ARM L2C thing */
-	void (*write_sec)(unsigned long, unsigned);
+	void (*write_sec)(unsigned long, unsigned int);
 	void (*configure)(const struct l2x0_regs *);
 };
 
 struct l2c_init_data {
 	const char *type;
-	unsigned way_size_0;
-	unsigned num_lock;
+	unsigned int way_size_0;
+	unsigned int num_lock;
 
-	void (*enable)(uint32_t, uint32_t, unsigned);
+	void (*enable)(uint32_t, uint32_t, unsigned int);
 	void (*fixup)(uint32_t, uint32_t, struct outer_cache_fns *);
 	void (*save)(uint32_t);
 	void (*configure)(uint32_t);
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index d508af7bf..a403b25a9 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -74,9 +74,9 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
  * doesn't include basepri or faultmask registers.
  */
 static const struct {
-	unsigned id;
+	unsigned int id;
 	const char *name;
-	unsigned bits;
+	unsigned int bits;
 	enum reg_type type;
 	const char *group;
 	const char *feature;
@@ -530,7 +530,7 @@ int armv7m_start_algorithm(struct target *target,
 	}
 
 	/* Store all non-debug execution registers to armv7m_algorithm_info context */
-	for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
+	for (unsigned int i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
 		struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
 		if (!reg->exist)
 			continue;
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 3e0ea0b75..3bf094275 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -36,7 +36,7 @@ static const char * const armv8_state_strings[] = {
 
 static const struct {
 	const char *name;
-	unsigned psr;
+	unsigned int psr;
 } armv8_mode_data[] = {
 	{
 		.name = "USR",
@@ -105,9 +105,9 @@ static const struct {
 };
 
 /** Map PSR mode bits to the name of an ARM processor operating mode. */
-const char *armv8_mode_name(unsigned psr_mode)
+const char *armv8_mode_name(unsigned int psr_mode)
 {
-	for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
 		if (armv8_mode_data[i].psr == psr_mode)
 			return armv8_mode_data[i].name;
 	}
@@ -683,7 +683,7 @@ static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum,
 	struct arm_dpm *dpm = &armv8->dpm;
 	struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
 	uint32_t value_r0 = 0, value_r1 = 0;
-	unsigned num = (regnum - ARMV8_V0) << 1;
+	unsigned int num = (regnum - ARMV8_V0) << 1;
 
 	switch (regnum) {
 	case ARMV8_V0 ... ARMV8_V15:
@@ -817,7 +817,7 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
 	struct arm_dpm *dpm = &armv8->dpm;
 	struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
 	uint32_t value_r0 = 0, value_r1 = 0;
-	unsigned num = (regnum - ARMV8_V0) << 1;
+	unsigned int num = (regnum - ARMV8_V0) << 1;
 
 	switch (regnum) {
 	case ARMV8_V0 ... ARMV8_V15:
@@ -1506,9 +1506,9 @@ static struct reg_data_type aarch64_flags_cpsr[] = {
 };
 
 static const struct {
-	unsigned id;
+	unsigned int id;
 	const char *name;
-	unsigned bits;
+	unsigned int bits;
 	enum arm_mode mode;
 	enum reg_type type;
 	const char *group;
@@ -1611,10 +1611,10 @@ static const struct {
 };
 
 static const struct {
-	unsigned id;
-	unsigned mapping;
+	unsigned int id;
+	unsigned int mapping;
 	const char *name;
-	unsigned bits;
+	unsigned int bits;
 	enum arm_mode mode;
 	enum reg_type type;
 	const char *group;
@@ -1881,7 +1881,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
 	return cache;
 }
 
-struct reg *armv8_reg_current(struct arm *arm, unsigned regnum)
+struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum)
 {
 	struct reg *r;
 
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 156b5f8bb..349c8f002 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -329,7 +329,7 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
 	}
 }
 
-const char *armv8_mode_name(unsigned psr_mode);
+const char *armv8_mode_name(unsigned int psr_mode);
 void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
 int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
 
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index bcecedc9d..22617fd0e 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -417,7 +417,7 @@ static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm,
 }
 
 #if 0
-static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
+static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
 	target_addr_t addr, uint32_t control)
 {
 	struct armv8_common *armv8 = dpm->arm->arch_info;
@@ -450,7 +450,7 @@ static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 }
 #endif
 
-static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
+static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
 {
 	struct armv8_common *armv8 = dpm->arm->arch_info;
 	uint32_t cr;
@@ -641,7 +641,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 /*
  * Common register read, relies on armv8_select_reg_access() having been called.
  */
-static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
+static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 {
 	struct armv8_common *armv8 = dpm->arm->arch_info;
 	int retval = ERROR_FAIL;
@@ -684,7 +684,7 @@ static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 /*
  * Common register write, relies on armv8_select_reg_access() having been called.
  */
-static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
+static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 {
 	struct armv8_common *armv8 = dpm->arm->arch_info;
 	int retval = ERROR_FAIL;
@@ -887,7 +887,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 	 * cope with the hand-crafted breakpoint code.
 	 */
 	if (arm->target->type->add_breakpoint == dpmv8_add_breakpoint) {
-		for (unsigned i = 0; i < dpm->nbp; i++) {
+		for (unsigned int i = 0; i < dpm->nbp; i++) {
 			struct dpm_bp *dbp = dpm->dbp + i;
 			struct breakpoint *bp = dbp->bp;
 
@@ -899,7 +899,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 	}
 
 	/* enable/disable watchpoints */
-	for (unsigned i = 0; i < dpm->nwp; i++) {
+	for (unsigned int i = 0; i < dpm->nwp; i++) {
 		struct dpm_wp *dwp = dpm->dwp + i;
 		struct watchpoint *wp = dwp->wp;
 
@@ -919,7 +919,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 		goto done;
 
 	/* check everything except our scratch register R0 */
-	for (unsigned i = 1; i < cache->num_regs; i++) {
+	for (unsigned int i = 1; i < cache->num_regs; i++) {
 		struct arm_reg *r;
 
 		/* skip non-existent */
@@ -1047,7 +1047,7 @@ static int armv8_dpm_full_context(struct target *target)
 		 * Pick some mode with unread registers and read them all.
 		 * Repeat until done.
 		 */
-		for (unsigned i = 0; i < cache->num_regs; i++) {
+		for (unsigned int i = 0; i < cache->num_regs; i++) {
 			struct arm_reg *r;
 
 			if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
@@ -1175,7 +1175,7 @@ static int dpmv8_add_breakpoint(struct target *target, struct breakpoint *bp)
 	if (bp->type == BKPT_SOFT)
 		LOG_DEBUG("using HW bkpt, not SW...");
 
-	for (unsigned i = 0; i < dpm->nbp; i++) {
+	for (unsigned int i = 0; i < dpm->nbp; i++) {
 		if (!dpm->dbp[i].bp) {
 			retval = dpmv8_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
 					bp->address, bp->length);
@@ -1194,7 +1194,7 @@ static int dpmv8_remove_breakpoint(struct target *target, struct breakpoint *bp)
 	struct arm_dpm *dpm = arm->dpm;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
-	for (unsigned i = 0; i < dpm->nbp; i++) {
+	for (unsigned int i = 0; i < dpm->nbp; i++) {
 		if (dpm->dbp[i].bp == bp) {
 			dpm->dbp[i].bp = NULL;
 			dpm->dbp[i].bpwp.dirty = true;
@@ -1208,7 +1208,7 @@ static int dpmv8_remove_breakpoint(struct target *target, struct breakpoint *bp)
 	return retval;
 }
 
-static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
+static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
 	struct watchpoint *wp)
 {
 	int retval;
@@ -1251,7 +1251,7 @@ static int dpmv8_add_watchpoint(struct target *target, struct watchpoint *wp)
 	int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 
 	if (dpm->bpwp_enable) {
-		for (unsigned i = 0; i < dpm->nwp; i++) {
+		for (unsigned int i = 0; i < dpm->nwp; i++) {
 			if (!dpm->dwp[i].wp) {
 				retval = dpmv8_watchpoint_setup(dpm, i, wp);
 				break;
@@ -1268,7 +1268,7 @@ static int dpmv8_remove_watchpoint(struct target *target, struct watchpoint *wp)
 	struct arm_dpm *dpm = arm->dpm;
 	int retval = ERROR_COMMAND_SYNTAX_ERROR;
 
-	for (unsigned i = 0; i < dpm->nwp; i++) {
+	for (unsigned int i = 0; i < dpm->nwp; i++) {
 		if (dpm->dwp[i].wp == wp) {
 			dpm->dwp[i].wp = NULL;
 			dpm->dwp[i].bpwp.dirty = true;
@@ -1484,7 +1484,7 @@ int armv8_dpm_initialize(struct arm_dpm *dpm)
 {
 	/* Disable all breakpoints and watchpoints at startup. */
 	if (dpm->bpwp_disable) {
-		unsigned i;
+		unsigned int i;
 
 		for (i = 0; i < dpm->nbp; i++) {
 			dpm->dbp[i].bpwp.number = i;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 498a9cd16..086aafe19 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -571,7 +571,7 @@ static int cortex_a_instr_read_data_r0_r1(struct arm_dpm *dpm,
 	return retval;
 }
 
-static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
+static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
 	uint32_t addr, uint32_t control)
 {
 	struct cortex_a_common *a = dpm_to_a(dpm);
@@ -606,7 +606,7 @@ static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 	return retval;
 }
 
-static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
+static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
 {
 	struct cortex_a_common *a = dpm_to_a(dpm);
 	uint32_t cr;
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 698a6868c..880a83a18 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -898,7 +898,7 @@ static int cortex_m_debug_entry(struct target *target)
 		arm->core_mode = ARM_MODE_HANDLER;
 		arm->map = armv7m_msp_reg_map;
 	} else {
-		unsigned control = buf_get_u32(arm->core_cache
+		unsigned int control = buf_get_u32(arm->core_cache
 				->reg_list[ARMV7M_CONTROL].value, 0, 3);
 
 		/* is this thread privileged? */
@@ -2142,7 +2142,7 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint
 	}
 
 	/* hardware allows address masks of up to 32K */
-	unsigned mask;
+	unsigned int mask;
 
 	for (mask = 0; mask < 16; mask++) {
 		if ((1u << mask) == watchpoint->length)
@@ -2378,7 +2378,7 @@ static int cortex_m_dwt_set_reg(struct reg *reg, uint8_t *buf)
 struct dwt_reg {
 	uint32_t addr;
 	const char *name;
-	unsigned size;
+	unsigned int size;
 };
 
 static const struct dwt_reg dwt_base_regs[] = {
@@ -2946,7 +2946,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
 
 	static const struct {
 		char name[10];
-		unsigned mask;
+		unsigned int mask;
 	} vec_ids[] = {
 		{ "hard_err",   VC_HARDERR, },
 		{ "int_err",    VC_INTERR, },
@@ -2972,7 +2972,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
 		return retval;
 
 	if (CMD_ARGC > 0) {
-		unsigned catch = 0;
+		unsigned int catch = 0;
 
 		if (CMD_ARGC == 1) {
 			if (strcmp(CMD_ARGV[0], "all") == 0) {
@@ -2984,7 +2984,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
 				goto write;
 		}
 		while (CMD_ARGC-- > 0) {
-			unsigned i;
+			unsigned int i;
 			for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
 				if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name) != 0)
 					continue;
@@ -3017,7 +3017,7 @@ write:
 		 */
 	}
 
-	for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(vec_ids); i++) {
 		command_print(CMD, "%9s: %s", vec_ids[i].name,
 			(demcr & vec_ids[i].mask) ? "catch" : "ignore");
 	}
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 687821c5d..953888de3 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -220,9 +220,9 @@ enum dsp563xx_reg_idx {
 };
 
 static const struct {
-	unsigned id;
+	unsigned int id;
 	const char *name;
-	unsigned bits;
+	unsigned int bits;
 	/* effective addressing mode encoding */
 	uint8_t eame;
 	uint32_t instr_mask;
diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c
index c90bca3c1..8b3b1c49b 100644
--- a/src/target/dsp5680xx.c
+++ b/src/target/dsp5680xx.c
@@ -1172,7 +1172,7 @@ static int dsp5680xx_read(struct target *t, target_addr_t a, uint32_t size,
 	dsp5680xx_context.flush = 0;
 	int counter = FLUSH_COUNT_READ_WRITE;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		if (--counter == 0) {
 			dsp5680xx_context.flush = 1;
 			counter = FLUSH_COUNT_READ_WRITE;
diff --git a/src/target/esirisc.c b/src/target/esirisc.c
index 14d34ff04..611141439 100644
--- a/src/target/esirisc.c
+++ b/src/target/esirisc.c
@@ -283,7 +283,7 @@ static int esirisc_save_context(struct target *target)
 
 	LOG_DEBUG("-");
 
-	for (unsigned i = 0; i < esirisc->reg_cache->num_regs; ++i) {
+	for (unsigned int i = 0; i < esirisc->reg_cache->num_regs; ++i) {
 		struct reg *reg = esirisc->reg_cache->reg_list + i;
 		struct esirisc_reg *reg_info = reg->arch_info;
 
@@ -300,7 +300,7 @@ static int esirisc_restore_context(struct target *target)
 
 	LOG_DEBUG("-");
 
-	for (unsigned i = 0; i < esirisc->reg_cache->num_regs; ++i) {
+	for (unsigned int i = 0; i < esirisc->reg_cache->num_regs; ++i) {
 		struct reg *reg = esirisc->reg_cache->reg_list + i;
 		struct esirisc_reg *reg_info = reg->arch_info;
 
diff --git a/src/target/esirisc_trace.c b/src/target/esirisc_trace.c
index 376ea1db7..a70d9d74b 100644
--- a/src/target/esirisc_trace.c
+++ b/src/target/esirisc_trace.c
@@ -287,9 +287,9 @@ static int esirisc_trace_init(struct target *target)
 }
 
 static int esirisc_trace_buf_get_u32(uint8_t *buffer, uint32_t size,
-		unsigned *pos, unsigned count, uint32_t *value)
+		unsigned int *pos, unsigned int count, uint32_t *value)
 {
-	const unsigned num_bits = size * 8;
+	const unsigned int num_bits = size * 8;
 
 	if (*pos+count > num_bits)
 		return ERROR_FAIL;
@@ -301,7 +301,7 @@ static int esirisc_trace_buf_get_u32(uint8_t *buffer, uint32_t size,
 }
 
 static int esirisc_trace_buf_get_pc(struct target *target, uint8_t *buffer, uint32_t size,
-		unsigned *pos, uint32_t *value)
+		unsigned int *pos, uint32_t *value)
 {
 	struct esirisc_common *esirisc = target_to_esirisc(target);
 	struct esirisc_trace *trace_info = &esirisc->trace_info;
@@ -380,7 +380,7 @@ static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *b
 	const uint32_t num_bits = size * 8;
 	int retval;
 
-	unsigned pos = 0;
+	unsigned int pos = 0;
 	while (pos < num_bits) {
 		uint32_t id;
 
@@ -484,7 +484,7 @@ static int esirisc_trace_analyze_simple(struct command_invocation *cmd, uint8_t
 	const uint32_t num_bits = size * 8;
 	int retval;
 
-	unsigned pos = 0;
+	unsigned int pos = 0;
 	while (pos < num_bits) {
 		uint32_t pc;
 
diff --git a/src/target/etb.h b/src/target/etb.h
index fa75600ad..1d0c08b2c 100644
--- a/src/target/etb.h
+++ b/src/target/etb.h
@@ -32,7 +32,7 @@ struct etb {
 	uint32_t ram_width;
 
 	/** how much trace buffer to fill after trigger */
-	unsigned trigger_percent;
+	unsigned int trigger_percent;
 };
 
 struct etb_reg {
diff --git a/src/target/etm.c b/src/target/etm.c
index d8f2a2faa..53d5cb68c 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -220,10 +220,10 @@ static const struct reg_arch_type etm_scan6_type = {
 /* Look up register by ID ... most ETM instances only
  * support a subset of the possible registers.
  */
-static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
+static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned int id)
 {
 	struct reg_cache *cache = etm_ctx->reg_cache;
-	unsigned i;
+	unsigned int i;
 
 	for (i = 0; i < cache->num_regs; i++) {
 		struct etm_reg *reg = cache->reg_list[i].arch_info;
@@ -238,9 +238,9 @@ static struct reg *etm_reg_lookup(struct etm_context *etm_ctx, unsigned id)
 	return NULL;
 }
 
-static void etm_reg_add(unsigned bcd_vers, struct arm_jtag *jtag_info,
+static void etm_reg_add(unsigned int bcd_vers, struct arm_jtag *jtag_info,
 	struct reg_cache *cache, struct etm_reg *ereg,
-	const struct etm_reg_info *r, unsigned nreg)
+	const struct etm_reg_info *r, unsigned int nreg)
 {
 	struct reg *reg = cache->reg_list;
 
@@ -281,7 +281,7 @@ struct reg_cache *etm_build_reg_cache(struct target *target,
 	struct reg_cache *reg_cache = malloc(sizeof(struct reg_cache));
 	struct reg *reg_list = NULL;
 	struct etm_reg *arch_info = NULL;
-	unsigned bcd_vers, config;
+	unsigned int bcd_vers, config;
 
 	/* the actual registers are kept in two arrays */
 	reg_list = calloc(128, sizeof(struct reg));
@@ -1590,7 +1590,7 @@ COMMAND_HANDLER(handle_etm_status_command)
 		if (!reg)
 			return ERROR_FAIL;
 		if (etm_get_reg(reg) == ERROR_OK) {
-			unsigned s = buf_get_u32(reg->value, 0, reg->size);
+			unsigned int s = buf_get_u32(reg->value, 0, reg->size);
 
 			command_print(CMD, "etm: %s%s%s%s",
 				/* bit(1) == progbit */
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index d6f2afb4e..6b0d2e95e 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -258,7 +258,7 @@ static int adapter_debug_entry(struct target *target)
 		arm->core_mode = ARM_MODE_HANDLER;
 		arm->map = armv7m_msp_reg_map;
 	} else {
-		unsigned control = buf_get_u32(arm->core_cache
+		unsigned int control = buf_get_u32(arm->core_cache
 				->reg_list[ARMV7M_CONTROL].value, 0, 3);
 
 		/* is this thread privileged? */
diff --git a/src/target/image.c b/src/target/image.c
index 440fe17d1..e8ac066fd 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -195,7 +195,7 @@ static int image_ihex_buffer_complete_inner(struct image *image,
 				}
 
 				while (count-- > 0) {
-					unsigned value;
+					unsigned int value;
 					sscanf(&lpsz_line[bytes_read], "%2x", &value);
 					ihex->buffer[cooked_bytes] = (uint8_t)value;
 					cal_checksum += (uint8_t)ihex->buffer[cooked_bytes];
@@ -864,7 +864,7 @@ static int image_mot_buffer_complete_inner(struct image *image,
 				}
 
 				while (count-- > 0) {
-					unsigned value;
+					unsigned int value;
 					sscanf(&lpsz_line[bytes_read], "%2x", &value);
 					mot->buffer[cooked_bytes] = (uint8_t)value;
 					cal_checksum += (uint8_t)mot->buffer[cooked_bytes];
diff --git a/src/target/lakemont.c b/src/target/lakemont.c
index 1fcd6426a..0340d0d0b 100644
--- a/src/target/lakemont.c
+++ b/src/target/lakemont.c
@@ -67,7 +67,7 @@ static const struct {
 	const char *name;
 	uint64_t op;
 	uint8_t pm_idx;
-	unsigned bits;
+	unsigned int bits;
 	enum reg_type type;
 	const char *group;
 	const char *feature;
@@ -597,7 +597,7 @@ static int read_all_core_hw_regs(struct target *t)
 {
 	int err;
 	uint32_t regval;
-	unsigned i;
+	unsigned int i;
 	struct x86_32_common *x86_32 = target_to_x86_32(t);
 	for (i = 0; i < (x86_32->cache->num_regs); i++) {
 		if (regs[i].pm_idx == NOT_AVAIL_REG)
@@ -616,7 +616,7 @@ static int read_all_core_hw_regs(struct target *t)
 static int write_all_core_hw_regs(struct target *t)
 {
 	int err;
-	unsigned i;
+	unsigned int i;
 	struct x86_32_common *x86_32 = target_to_x86_32(t);
 	for (i = 0; i < (x86_32->cache->num_regs); i++) {
 		if (regs[i].pm_idx == NOT_AVAIL_REG)
diff --git a/src/target/mips32.c b/src/target/mips32.c
index af52ffca0..dd40558a1 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -34,7 +34,7 @@ static const char *mips_isa_strings[] = {
  * based on gdb-7.6.2/gdb/features/mips-{fpu,cp0,cpu,dsp}.xml
  */
 static const struct {
-	unsigned id;
+	unsigned int id;
 	const char *name;
 	enum reg_type type;
 	const char *group;
@@ -1187,7 +1187,7 @@ int mips32_read_config_regs(struct target *target)
 		mips32->isa_imp = MIPS32_MIPS16;
 		LOG_USER("ISA implemented: %s%s", "MIPS32, MIPS16", buf);
 	} else if (ejtag_info->config_regs >= 4) {	/* config3 implemented */
-		unsigned isa_imp = (ejtag_info->config[3] & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT;
+		unsigned int isa_imp = (ejtag_info->config[3] & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT;
 		if (isa_imp == 1) {
 			mips32->isa_imp = MMIPS32_ONLY;
 			LOG_USER("ISA implemented: %s%s", "microMIPS32", buf);
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 018d8424e..2d0bd641b 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -370,7 +370,7 @@ int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_in
 		return ERROR_FAIL;
 	}
 
-	unsigned num_clocks =
+	unsigned int num_clocks =
 		((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000;
 
 	uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
@@ -1362,7 +1362,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
 	pracc_swap16_array(ejtag_info, jmp_code, ARRAY_SIZE(jmp_code));
 
 	/* execute jump code, with no address check */
-	for (unsigned i = 0; i < ARRAY_SIZE(jmp_code); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(jmp_code); i++) {
 		int retval = wait_for_pracc_rw(ejtag_info);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1397,7 +1397,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
 	mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
 
-	unsigned num_clocks = 0;	/* like in legacy code */
+	unsigned int num_clocks = 0;	/* like in legacy code */
 	if (ejtag_info->mode != 0)
 		num_clocks = ((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000;
 
diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h
index f78f89153..a0244a695 100644
--- a/src/target/mips32_pracc.h
+++ b/src/target/mips32_pracc.h
@@ -45,7 +45,7 @@ struct pa_list {
 
 struct pracc_queue_info {
 	struct mips_ejtag *ejtag_info;
-	unsigned isa;
+	unsigned int isa;
 	int retval;
 	int code_count;
 	int store_count;
diff --git a/src/target/mips64.c b/src/target/mips64.c
index 48f4563dc..3d193a300 100644
--- a/src/target/mips64.c
+++ b/src/target/mips64.c
@@ -21,7 +21,7 @@
 #include "mips64.h"
 
 static const struct {
-	unsigned id;
+	unsigned int id;
 	const char *name;
 	enum reg_type type;
 	const char *group;
@@ -332,8 +332,8 @@ int mips64_save_context(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	for (unsigned i = 0; i < MIPS64_NUM_REGS; i++)
-			retval = mips64->read_core_reg(target, i);
+	for (unsigned int i = 0; i < MIPS64_NUM_REGS; i++)
+		retval = mips64->read_core_reg(target, i);
 
 	return retval;
 }
@@ -343,7 +343,7 @@ int mips64_restore_context(struct target *target)
 	struct mips64_common *mips64 = target->arch_info;
 	struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
 
-	for (unsigned i = 0; i < MIPS64_NUM_REGS; i++) {
+	for (unsigned int i = 0; i < MIPS64_NUM_REGS; i++) {
 		if (mips64->core_cache->reg_list[i].dirty)
 			mips64->write_core_reg(target, i);
 	}
@@ -379,7 +379,7 @@ int mips64_build_reg_cache(struct target *target)
 	struct reg_cache **cache_p, *cache;
 	struct mips64_core_reg *arch_info = NULL;
 	struct reg *reg_list = NULL;
-	unsigned i;
+	unsigned int i;
 
 	cache = calloc(1, sizeof(*cache));
 	if (!cache) {
diff --git a/src/target/mips64_pracc.c b/src/target/mips64_pracc.c
index b083f5ce8..8cfce32e3 100644
--- a/src/target/mips64_pracc.c
+++ b/src/target/mips64_pracc.c
@@ -27,13 +27,13 @@
 
 struct mips64_pracc_context {
 	uint64_t *local_iparam;
-	unsigned num_iparam;
+	unsigned int num_iparam;
 	uint64_t *local_oparam;
-	unsigned num_oparam;
+	unsigned int num_oparam;
 	const uint32_t *code;
-	unsigned code_len;
+	unsigned int code_len;
 	uint64_t stack[STACK_DEPTH];
-	unsigned stack_offset;
+	unsigned int stack_offset;
 	struct mips_ejtag *ejtag_info;
 };
 
@@ -65,7 +65,7 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
 static int mips64_pracc_exec_read(struct mips64_pracc_context *ctx, uint64_t address)
 {
 	struct mips_ejtag *ejtag_info = ctx->ejtag_info;
-	unsigned offset;
+	unsigned int offset;
 	uint32_t ejtag_ctrl;
 	uint64_t data;
 	int rc;
@@ -154,7 +154,7 @@ static int mips64_pracc_exec_write(struct mips64_pracc_context *ctx, uint64_t ad
 {
 	uint32_t ejtag_ctrl;
 	uint64_t data;
-	unsigned offset;
+	unsigned int offset;
 	struct mips_ejtag *ejtag_info = ctx->ejtag_info;
 	int rc;
 
@@ -209,9 +209,9 @@ static int mips64_pracc_exec_write(struct mips64_pracc_context *ctx, uint64_t ad
 }
 
 int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
-		      unsigned code_len, const uint32_t *code,
-		      unsigned num_param_in, uint64_t *param_in,
-		      unsigned num_param_out, uint64_t *param_out)
+		      unsigned int code_len, const uint32_t *code,
+		      unsigned int num_param_in, uint64_t *param_in,
+		      unsigned int num_param_out, uint64_t *param_out)
 {
 	uint32_t ejtag_ctrl;
 	uint64_t address = 0, address_prev = 0;
@@ -219,7 +219,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
 	int retval;
 	int pass = 0;
 	bool first_time_call = true;
-	unsigned i;
+	unsigned int i;
 
 	for (i = 0; i < code_len; i++)
 		LOG_DEBUG("%08" PRIx32, code[i]);
@@ -354,11 +354,11 @@ static int mips64_pracc_read_u64(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 static int mips64_pracc_read_mem64(struct mips_ejtag *ejtag_info, uint64_t addr,
-			    unsigned count, uint64_t *buf)
+			    unsigned int count, uint64_t *buf)
 {
 	int retval = ERROR_OK;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		retval = mips64_pracc_read_u64(ejtag_info, addr + 8*i, &buf[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -414,11 +414,11 @@ static int mips64_pracc_read_u32(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 static int mips64_pracc_read_mem32(struct mips_ejtag *ejtag_info, uint64_t addr,
-				   unsigned count, uint32_t *buf)
+				   unsigned int count, uint32_t *buf)
 {
 	int retval = ERROR_OK;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		retval = mips64_pracc_read_u32(ejtag_info, addr + 4 * i, &buf[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -474,11 +474,11 @@ static int mips64_pracc_read_u16(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 static int mips64_pracc_read_mem16(struct mips_ejtag *ejtag_info, uint64_t addr,
-			    unsigned count, uint16_t *buf)
+			    unsigned int count, uint16_t *buf)
 {
 	int retval = ERROR_OK;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		retval = mips64_pracc_read_u16(ejtag_info, addr + 2*i, &buf[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -534,11 +534,11 @@ static int mips64_pracc_read_u8(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 static int mips64_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint64_t addr,
-			  unsigned count, uint8_t *buf)
+			  unsigned int count, uint8_t *buf)
 {
 	int retval = ERROR_OK;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		retval = mips64_pracc_read_u8(ejtag_info, addr + i, &buf[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -547,7 +547,7 @@ static int mips64_pracc_read_mem8(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 int mips64_pracc_read_mem(struct mips_ejtag *ejtag_info, uint64_t addr,
-			  unsigned size, unsigned count, void *buf)
+			  unsigned int size, unsigned int count, void *buf)
 {
 	switch (size) {
 	case 1:
@@ -612,11 +612,11 @@ static int mips64_pracc_write_u64(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 static int mips64_pracc_write_mem64(struct mips_ejtag *ejtag_info,
-			     uint64_t addr, unsigned count, uint64_t *buf)
+			     uint64_t addr, unsigned int count, uint64_t *buf)
 {
 	int retval = ERROR_OK;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		retval = mips64_pracc_write_u64(ejtag_info, addr + 8 * i, &buf[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -674,11 +674,11 @@ static int mips64_pracc_write_u32(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 static int mips64_pracc_write_mem32(struct mips_ejtag *ejtag_info, uint64_t addr,
-			     unsigned count, uint32_t *buf)
+			     unsigned int count, uint32_t *buf)
 {
 	int retval = ERROR_OK;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		retval = mips64_pracc_write_u32(ejtag_info, addr + 4 * i, &buf[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -734,11 +734,11 @@ static int mips64_pracc_write_u16(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 static int mips64_pracc_write_mem16(struct mips_ejtag *ejtag_info,
-			     uint64_t addr, unsigned count, uint16_t *buf)
+			     uint64_t addr, unsigned int count, uint16_t *buf)
 {
 	int retval = ERROR_OK;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		retval = mips64_pracc_write_u16(ejtag_info, addr + 2 * i, &buf[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -795,11 +795,11 @@ static int mips64_pracc_write_u8(struct mips_ejtag *ejtag_info, uint64_t addr,
 }
 
 static int mips64_pracc_write_mem8(struct mips_ejtag *ejtag_info,
-			    uint64_t addr, unsigned count, uint8_t *buf)
+			    uint64_t addr, unsigned int count, uint8_t *buf)
 {
 	int retval = ERROR_OK;
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		retval = mips64_pracc_write_u8(ejtag_info, addr + i, &buf[i]);
 		if (retval != ERROR_OK)
 			return retval;
@@ -808,8 +808,8 @@ static int mips64_pracc_write_mem8(struct mips_ejtag *ejtag_info,
 }
 
 int mips64_pracc_write_mem(struct mips_ejtag *ejtag_info,
-			   uint64_t addr, unsigned size,
-			   unsigned count, void *buf)
+			   uint64_t addr, unsigned int size,
+			   unsigned int count, void *buf)
 {
 	switch (size) {
 	case 1:
@@ -1270,7 +1270,7 @@ int mips64_pracc_read_regs(struct mips_ejtag *ejtag_info, uint64_t *regs)
 int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
 			       struct working_area *source,
 			       bool write_t, uint64_t addr,
-			       unsigned count, uint64_t *buf)
+			       unsigned int count, uint64_t *buf)
 {
 	uint32_t handler_code[] = {
 		/* caution when editing, table is modified below */
@@ -1321,7 +1321,7 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
 	};
 
 	int retval;
-	unsigned i;
+	unsigned int i;
 	uint32_t ejtag_ctrl, address32;
 	uint64_t address, val;
 
@@ -1385,7 +1385,7 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
 	mips64_ejtag_fastdata_scan(ejtag_info, 1, &val);
 
 	/* like in legacy code */
-	unsigned num_clocks = 0;
+	unsigned int num_clocks = 0;
 	if (ejtag_info->mode != 0)
 		num_clocks = ((uint64_t)(ejtag_info->scan_delay) * adapter_get_speed_khz() + 500000) / 1000000;
 	LOG_DEBUG("num_clocks=%d", num_clocks);
diff --git a/src/target/mips64_pracc.h b/src/target/mips64_pracc.h
index 19d151946..2bdc856b9 100644
--- a/src/target/mips64_pracc.h
+++ b/src/target/mips64_pracc.h
@@ -40,20 +40,22 @@
 #define MIPS64_PRACC_ADDR_STEP 4
 #define MIPS64_PRACC_DATA_STEP 8
 
-int mips64_pracc_read_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned size, unsigned count, void *buf);
-int mips64_pracc_write_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned size, unsigned count, void *buf);
+int mips64_pracc_read_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned int size,
+						  unsigned int count, void *buf);
+int mips64_pracc_write_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned int size,
+						   unsigned int count, void *buf);
 
 int mips64_pracc_read_regs(struct mips_ejtag *ejtag_info, uint64_t *regs);
 int mips64_pracc_write_regs(struct mips_ejtag *ejtag_info, uint64_t *regs);
 
 int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
-		      unsigned code_len, const uint32_t *code,
-		      unsigned num_param_in, uint64_t *param_in,
-		      unsigned num_param_out, uint64_t *param_out);
+		      unsigned int code_len, const uint32_t *code,
+		      unsigned int num_param_in, uint64_t *param_in,
+		      unsigned int num_param_out, uint64_t *param_out);
 
 int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
 			       struct working_area *source,
 			       bool write_t, uint64_t addr,
-			       unsigned count, uint64_t *buf);
+			       unsigned int count, uint64_t *buf);
 
 #endif /* OPENOCD_TARGET_MIPS64_PRACC_H */
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 389461cae..2ff4aa926 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -493,7 +493,7 @@ int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step)
 		MIPS64_NOP,
 	};
 	const uint32_t *code = enable_step ? code_enable : code_disable;
-	unsigned code_len = enable_step ? ARRAY_SIZE(code_enable) :
+	unsigned int code_len = enable_step ? ARRAY_SIZE(code_enable) :
 					  ARRAY_SIZE(code_disable);
 
 	return mips64_pracc_exec(ejtag_info,
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 7376e5141..30a46903f 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -214,7 +214,7 @@ struct mips_ejtag {
 
 	uint32_t reg8;
 	uint32_t reg9;
-	unsigned scan_delay;
+	unsigned int scan_delay;
 	int mode;
 	uint32_t pa_ctrl;
 	uint32_t pa_addr;
diff --git a/src/target/register.h b/src/target/register.h
index 1e4f2e088..b9af401b4 100644
--- a/src/target/register.h
+++ b/src/target/register.h
@@ -145,7 +145,7 @@ struct reg_cache {
 	const char *name;
 	struct reg_cache *next;
 	struct reg *reg_list;
-	unsigned num_regs;
+	unsigned int num_regs;
 };
 
 struct reg_arch_type {
diff --git a/src/target/stm8.c b/src/target/stm8.c
index 227101b6f..2b3466dac 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -38,7 +38,7 @@ static int (*adapter_speed)(int speed);
 extern struct adapter_driver *adapter_driver;
 
 static const struct {
-	unsigned id;
+	unsigned int id;
 	const char *name;
 	const uint8_t bits;
 	enum reg_type type;
diff --git a/src/target/target.c b/src/target/target.c
index 281bbbd40..56aa8b1e7 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1443,14 +1443,14 @@ int target_gdb_fileio_end(struct target *target, int retcode, int fileio_errno,
 
 target_addr_t target_address_max(struct target *target)
 {
-	unsigned bits = target_address_bits(target);
+	unsigned int bits = target_address_bits(target);
 	if (sizeof(target_addr_t) * 8 == bits)
 		return (target_addr_t) -1;
 	else
 		return (((target_addr_t) 1) << bits) - 1;
 }
 
-unsigned target_address_bits(struct target *target)
+unsigned int target_address_bits(struct target *target)
 {
 	if (target->type->address_bits)
 		return target->type->address_bits(target);
@@ -3035,7 +3035,7 @@ COMMAND_HANDLER(handle_reg_command)
 
 		unsigned int count = 0;
 		while (cache) {
-			unsigned i;
+			unsigned int i;
 
 			command_print(CMD, "===== %s", cache->name);
 
@@ -3070,13 +3070,13 @@ COMMAND_HANDLER(handle_reg_command)
 
 	/* access a single register by its ordinal number */
 	if ((CMD_ARGV[0][0] >= '0') && (CMD_ARGV[0][0] <= '9')) {
-		unsigned num;
+		unsigned int num;
 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
 
 		struct reg_cache *cache = target->reg_cache;
 		unsigned int count = 0;
 		while (cache) {
-			unsigned i;
+			unsigned int i;
 			for (i = 0; i < cache->num_regs; i++) {
 				if (count++ == num) {
 					reg = &cache->reg_list[i];
@@ -3194,7 +3194,7 @@ COMMAND_HANDLER(handle_wait_halt_command)
 	if (CMD_ARGC > 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	unsigned ms = DEFAULT_HALT_TIMEOUT;
+	unsigned int ms = DEFAULT_HALT_TIMEOUT;
 	if (1 == CMD_ARGC) {
 		int retval = parse_uint(CMD_ARGV[0], &ms);
 		if (retval != ERROR_OK)
@@ -3260,7 +3260,7 @@ COMMAND_HANDLER(handle_halt_command)
 		return retval;
 
 	if (CMD_ARGC == 1) {
-		unsigned wait_local;
+		unsigned int wait_local;
 		retval = parse_uint(CMD_ARGV[0], &wait_local);
 		if (retval != ERROR_OK)
 			return ERROR_COMMAND_SYNTAX_ERROR;
@@ -3344,14 +3344,14 @@ COMMAND_HANDLER(handle_step_command)
 }
 
 void target_handle_md_output(struct command_invocation *cmd,
-		struct target *target, target_addr_t address, unsigned size,
-		unsigned count, const uint8_t *buffer)
+		struct target *target, target_addr_t address, unsigned int size,
+		unsigned int count, const uint8_t *buffer)
 {
-	const unsigned line_bytecnt = 32;
-	unsigned line_modulo = line_bytecnt / size;
+	const unsigned int line_bytecnt = 32;
+	unsigned int line_modulo = line_bytecnt / size;
 
 	char output[line_bytecnt * 4 + 1];
-	unsigned output_len = 0;
+	unsigned int output_len = 0;
 
 	const char *value_fmt;
 	switch (size) {
@@ -3373,7 +3373,7 @@ void target_handle_md_output(struct command_invocation *cmd,
 		return;
 	}
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		if (i % line_modulo == 0) {
 			output_len += snprintf(output + output_len,
 					sizeof(output) - output_len,
@@ -3412,7 +3412,7 @@ COMMAND_HANDLER(handle_md_command)
 	if (CMD_ARGC < 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	unsigned size = 0;
+	unsigned int size = 0;
 	switch (CMD_NAME[2]) {
 	case 'd':
 		size = 8;
@@ -3445,7 +3445,7 @@ COMMAND_HANDLER(handle_md_command)
 	target_addr_t address;
 	COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
 
-	unsigned count = 1;
+	unsigned int count = 1;
 	if (CMD_ARGC == 2)
 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count);
 
@@ -3471,22 +3471,22 @@ typedef int (*target_write_fn)(struct target *target,
 static int target_fill_mem(struct target *target,
 		target_addr_t address,
 		target_write_fn fn,
-		unsigned data_size,
+		unsigned int data_size,
 		/* value */
 		uint64_t b,
 		/* count */
-		unsigned c)
+		unsigned int c)
 {
 	/* We have to write in reasonably large chunks to be able
 	 * to fill large memory areas with any sane speed */
-	const unsigned chunk_size = 16384;
+	const unsigned int chunk_size = 16384;
 	uint8_t *target_buf = malloc(chunk_size * data_size);
 	if (!target_buf) {
 		LOG_ERROR("Out of memory");
 		return ERROR_FAIL;
 	}
 
-	for (unsigned i = 0; i < chunk_size; i++) {
+	for (unsigned int i = 0; i < chunk_size; i++) {
 		switch (data_size) {
 		case 8:
 			target_buffer_set_u64(target, target_buf + i * data_size, b);
@@ -3507,8 +3507,8 @@ static int target_fill_mem(struct target *target,
 
 	int retval = ERROR_OK;
 
-	for (unsigned x = 0; x < c; x += chunk_size) {
-		unsigned current;
+	for (unsigned int x = 0; x < c; x += chunk_size) {
+		unsigned int current;
 		current = c - x;
 		if (current > chunk_size)
 			current = chunk_size;
@@ -3550,12 +3550,12 @@ COMMAND_HANDLER(handle_mw_command)
 	uint64_t value;
 	COMMAND_PARSE_NUMBER(u64, CMD_ARGV[1], value);
 
-	unsigned count = 1;
+	unsigned int count = 1;
 	if (CMD_ARGC == 3)
 		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], count);
 
 	struct target *target = get_current_target(CMD_CTX);
-	unsigned wordsize;
+	unsigned int wordsize;
 	switch (CMD_NAME[2]) {
 		case 'd':
 			wordsize = 8;
diff --git a/src/target/target.h b/src/target/target.h
index ecc8a9032..abd0b5825 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -685,7 +685,7 @@ target_addr_t target_address_max(struct target *target);
  *
  * This routine is a wrapper for target->type->address_bits.
  */
-unsigned target_address_bits(struct target *target);
+unsigned int target_address_bits(struct target *target);
 
 /**
  * Return the number of data bits this target supports.
@@ -778,8 +778,8 @@ int target_arch_state(struct target *target);
 void target_handle_event(struct target *t, enum target_event e);
 
 void target_handle_md_output(struct command_invocation *cmd,
-	struct target *target, target_addr_t address, unsigned size,
-	unsigned count, const uint8_t *buffer);
+	struct target *target, target_addr_t address, unsigned int size,
+	unsigned int count, const uint8_t *buffer);
 
 int target_profiling_default(struct target *target, uint32_t *samples, uint32_t
 		max_num_samples, uint32_t *num_samples, uint32_t seconds);
diff --git a/src/target/target_type.h b/src/target/target_type.h
index bc42c2d16..f35a59c5f 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -303,7 +303,7 @@ struct target_type {
 	/* Return the number of address bits this target supports. This will
 	 * typically be 32 for 32-bit targets, and 64 for 64-bit targets. If not
 	 * implemented, it's assumed to be 32. */
-	unsigned (*address_bits)(struct target *target);
+	unsigned int (*address_bits)(struct target *target);
 
 	/* Return the number of system bus data bits this target supports. This
 	 * will typically be 32 for 32-bit targets, and 64 for 64-bit targets. If
diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c
index 666bb07bf..2c60b9f7e 100644
--- a/src/target/x86_32_common.c
+++ b/src/target/x86_32_common.c
@@ -1330,14 +1330,14 @@ static int write_hw_reg_from_cache(struct target *t, int num)
 
 /* x86 32 commands */
 static void handle_iod_output(struct command_invocation *cmd,
-		struct target *target, uint32_t address, unsigned size,
-		unsigned count, const uint8_t *buffer)
+		struct target *target, uint32_t address, unsigned int size,
+		unsigned int count, const uint8_t *buffer)
 {
-	const unsigned line_bytecnt = 32;
-	unsigned line_modulo = line_bytecnt / size;
+	const unsigned int line_bytecnt = 32;
+	unsigned int line_modulo = line_bytecnt / size;
 
 	char output[line_bytecnt * 4 + 1];
-	unsigned output_len = 0;
+	unsigned int output_len = 0;
 
 	const char *value_fmt;
 	switch (size) {
@@ -1356,7 +1356,7 @@ static void handle_iod_output(struct command_invocation *cmd,
 		return;
 	}
 
-	for (unsigned i = 0; i < count; i++) {
+	for (unsigned int i = 0; i < count; i++) {
 		if (i % line_modulo == 0) {
 			output_len += snprintf(output + output_len,
 					sizeof(output) - output_len,
@@ -1399,7 +1399,7 @@ COMMAND_HANDLER(handle_iod_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	unsigned size = 0;
+	unsigned int size = 0;
 	switch (CMD_NAME[2]) {
 	case 'w':
 		size = 4;
@@ -1413,7 +1413,7 @@ COMMAND_HANDLER(handle_iod_command)
 	default:
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
-	unsigned count = 1;
+	unsigned int count = 1;
 	uint8_t *buffer = calloc(count, size);
 	struct target *target = get_current_target(CMD_CTX);
 	int retval = x86_32_common_read_io(target, address, size, buffer);
@@ -1425,7 +1425,7 @@ COMMAND_HANDLER(handle_iod_command)
 
 static int target_fill_io(struct target *target,
 		uint32_t address,
-		unsigned data_size,
+		unsigned int data_size,
 		/* value */
 		uint32_t b)
 {
@@ -1458,7 +1458,7 @@ COMMAND_HANDLER(handle_iow_command)
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
 	struct target *target = get_current_target(CMD_CTX);
 
-	unsigned wordsize;
+	unsigned int wordsize;
 	switch (CMD_NAME[2]) {
 		case 'w':
 			wordsize = 4;
diff --git a/src/target/xscale.c b/src/target/xscale.c
index fbf43516d..155abaef1 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -840,7 +840,7 @@ static int xscale_debug_entry(struct target *target)
 	struct arm *arm = &xscale->arm;
 	uint32_t pc;
 	uint32_t buffer[10];
-	unsigned i;
+	unsigned int i;
 	int retval;
 	uint32_t moe;
 
@@ -1515,7 +1515,7 @@ static int xscale_deassert_reset(struct target *target)
 	 */
 	{
 		uint32_t address;
-		unsigned buf_cnt;
+		unsigned int buf_cnt;
 		const uint8_t *buffer = xscale_debug_handler;
 		int retval;
 
@@ -1539,11 +1539,11 @@ static int xscale_deassert_reset(struct target *target)
 		 * coprocessors, trace data, etc.
 		 */
 		address = xscale->handler_address;
-		for (unsigned binary_size = sizeof(xscale_debug_handler);
+		for (unsigned int binary_size = sizeof(xscale_debug_handler);
 			binary_size > 0;
 			binary_size -= buf_cnt, buffer += buf_cnt) {
 			uint32_t cache_line[8];
-			unsigned i;
+			unsigned int i;
 
 			buf_cnt = binary_size;
 			if (buf_cnt > 32)
@@ -3215,7 +3215,7 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
 
 static const struct {
 	char name[15];
-	unsigned mask;
+	unsigned int mask;
 } vec_ids[] = {
 	{ "fiq",		DCSR_TF, },
 	{ "irq",		DCSR_TI, },
@@ -3250,7 +3250,7 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command)
 			}
 		}
 		while (CMD_ARGC-- > 0) {
-			unsigned i;
+			unsigned int i;
 			for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
 				if (strcmp(CMD_ARGV[CMD_ARGC], vec_ids[i].name))
 					continue;
@@ -3268,7 +3268,7 @@ COMMAND_HANDLER(xscale_handle_vector_catch_command)
 	}
 
 	dcsr_value = buf_get_u32(dcsr_reg->value, 0, 32);
-	for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++) {
+	for (unsigned int i = 0; i < ARRAY_SIZE(vec_ids); i++) {
 		command_print(CMD, "%15s: %s", vec_ids[i].name,
 			(dcsr_value & vec_ids[i].mask) ? "catch" : "ignore");
 	}