ARM: ADIv5 symbol and comment cleanup
Instead of magic numbers, use their AP_REG_* constants. Rename the ROM address symbol as BASE to match ARM's documentation. Comment various other symbols in the header; add some missing ones. Remove an unused struct. Add some doxygen for stuff including the DAP structure and initialization. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
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David Brownell
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ec88ccc51c
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e60c164cdb
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@ -23,16 +23,34 @@
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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/***************************************************************************
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* *
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* This file implements support for the ARM Debug Interface v5 (ADI_V5) *
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* *
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* ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
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* *
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* CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D *
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* Cortex-M3(tm) TRM, ARM DDI 0337G *
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* *
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***************************************************************************/
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/**
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* @file
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* This file implements support for the ARM Debug Interface version 5 (ADIv5)
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* debugging architecture. Compared with previous versions, this includes
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* a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
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* transport, and focusses on memory mapped resources as defined by the
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* CoreSight architecture.
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*
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* A key concept in ADIv5 is the Debug Access Port, or DAP. A DAP has two
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* basic components: a Debug Port (DP) transporting messages to and from a
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* debugger, and an Access Port (AP) accessing resources. Three types of DP
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* are defined. One uses only JTAG for communication, and is called JTAG-DP.
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* One uses only SWD for communication, and is called SW-DP. The third can
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* use either SWD or JTAG, and is called SWJ-DP. The most common type of AP
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* is used to access memory mapped resources and is called a MEM-AP. Also a
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* JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
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*/
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/*
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* Relevant specifications from ARM include:
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*
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* ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A
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* CoreSight(tm) v1.0 Architecture Specification ARM IHI 0029B
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*
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* CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
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* Cortex-M3(tm) TRM, ARM DDI 0337G
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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@ -950,6 +968,13 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u
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return retval;
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}
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/**
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* Initialize a DAP.
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*
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* @todo Rename this. We also need an initialization scheme which account
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* for SWD transports not just JTAG; that will need to address differences
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* in layering. (JTAG is useful without any debug target; but not SWD.)
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*/
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int ahbap_debugport_init(struct swjdp_common *swjdp)
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{
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uint32_t idreg, romaddr, dummy;
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@ -959,9 +984,17 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
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LOG_DEBUG(" ");
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/* Default MEM-AP setup.
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*
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* REVISIT AP #0 may be an inappropriate default for this.
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* Should we probe, or receve a hint from the caller?
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* Presumably we can ignore the possibility of multiple APs.
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*/
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swjdp->apsel = 0;
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swjdp->ap_csw_value = -1;
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swjdp->ap_tar_value = -1;
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/* DP initialization */
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swjdp->trans_mode = TRANS_MODE_ATOMIC;
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dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
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dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
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@ -999,8 +1032,14 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
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dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
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dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
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dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
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dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
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/*
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* REVISIT this isn't actually *initializing* anything in an AP,
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* and doesn't care if it's a MEM-AP at all (much less AHB-AP).
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* Should it? If the ROM address is valid, is this the right
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* place to scan the table and do any topology detection?
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*/
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dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
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dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
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LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
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@ -1035,8 +1074,8 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp
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apselold = swjdp->apsel;
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dap_ap_select(swjdp, apsel);
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dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase);
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dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
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dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
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dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
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swjdp_transaction_endcheck(swjdp);
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/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
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mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
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@ -1387,7 +1426,7 @@ DAP_COMMAND_HANDLER(dap_baseaddr_command)
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if (apselsave != apsel)
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dap_ap_select(swjdp, apsel);
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dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
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dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
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retval = swjdp_transaction_endcheck(swjdp);
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command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
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@ -1436,7 +1475,7 @@ DAP_COMMAND_HANDLER(dap_apsel_command)
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}
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dap_ap_select(swjdp, apsel);
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dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
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dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
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retval = swjdp_transaction_endcheck(swjdp);
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command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
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apsel, apid);
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@ -1464,7 +1503,7 @@ DAP_COMMAND_HANDLER(dap_apid_command)
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if (apselsave != apsel)
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dap_ap_select(swjdp, apsel);
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dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
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dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
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retval = swjdp_transaction_endcheck(swjdp);
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command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
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if (apselsave != apsel)
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@ -23,6 +23,13 @@
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#ifndef ARM_ADI_V5_H
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#define ARM_ADI_V5_H
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/**
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* @file
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* This defines formats and data structures used to talk to ADIv5 entities.
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* Those include a DAP, different types of Debug Port (DP), and memory mapped
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* resources accessed through a MEM-AP.
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*/
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#include "arm_jtag.h"
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#define DAP_IR_DPACC 0xA
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@ -30,14 +37,22 @@
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#define DPAP_WRITE 0
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#define DPAP_READ 1
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/* A[3:0] for DP registers (for JTAG, stored in DPACC) */
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#define DP_ZERO 0
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#define DP_CTRL_STAT 0x4
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#define DP_SELECT 0x8
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#define DP_RDBUFF 0xC
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/* Fields of the DP's CTRL/STAT register */
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#define CORUNDETECT (1 << 0)
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#define SSTICKYORUN (1 << 1)
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/* 3:2 - transaction mode (e.g. pushed compare) */
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#define SSTICKYERR (1 << 5)
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#define READOK (1 << 6)
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#define WDATAERR (1 << 7)
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/* 11:8 - mask lanes for pushed compare or verify ops */
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/* 21:12 - transaction counter */
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#define CDBGRSTREQ (1 << 26)
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#define CDBGRSTACK (1 << 27)
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#define CDBGPWRUPREQ (1 << 28)
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@ -45,6 +60,8 @@
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#define CSYSPWRUPREQ (1 << 30)
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#define CSYSPWRUPACK (1 << 31)
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/* MEM-AP register addresses */
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/* TODO: rename as MEM_AP_REG_* */
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#define AP_REG_CSW 0x00
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#define AP_REG_TAR 0x04
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#define AP_REG_DRW 0x0C
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@ -52,19 +69,26 @@
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#define AP_REG_BD1 0x14
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#define AP_REG_BD2 0x18
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#define AP_REG_BD3 0x1C
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#define AP_REG_DBGROMA 0xF8
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#define AP_REG_CFG 0xF4 /* big endian? */
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#define AP_REG_BASE 0xF8
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/* Generic AP register address */
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#define AP_REG_IDR 0xFC
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/* Fields of the MEM-AP's CSW register */
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#define CSW_8BIT 0
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#define CSW_16BIT 1
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#define CSW_32BIT 2
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#define CSW_ADDRINC_MASK (3 << 4)
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#define CSW_ADDRINC_OFF 0
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#define CSW_ADDRINC_SINGLE (1 << 4)
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#define CSW_ADDRINC_PACKED (2 << 4)
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#define CSW_HPROT (1 << 25)
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#define CSW_MASTER_DEBUG (1 << 29)
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#define CSW_DEVICE_EN (1 << 6)
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#define CSW_TRIN_PROG (1 << 7)
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#define CSW_SPIDEN (1 << 23)
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/* 30:24 - implementation-defined! */
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#define CSW_HPROT (1 << 25) /* ? */
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#define CSW_MASTER_DEBUG (1 << 29) /* ? */
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#define CSW_DBGSWENABLE (1 << 31)
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/* transaction mode */
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@ -74,12 +98,14 @@
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/* Freerunning transactions with delays and overrun checking */
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#define TRANS_MODE_COMPOSITE 2
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struct swjdp_reg
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{
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int addr;
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struct arm_jtag *jtag_info;
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};
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/**
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* This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
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* A DAP has two types of component: one Debug Port (DP), which is a
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* transport agent; and at least one Access Port (AP), controlling
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* resource access. Most common is a MEM-AP, for memory access.
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*
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* @todo Rename "swjdp_common" as "dap". Use of SWJ-DP is optional!
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*/
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struct swjdp_common
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{
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struct arm_jtag *jtag_info;
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