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riscv-openocd
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target/riscv: Refactor riscv_openocd_poll() 

There used to be entirely separate code paths depending on whether we're
in SMP mode or not. Now they're both the same.

Change-Id: I8f46295e4bc005f441af0c03d4f608c53b8a6586
Signed-off-by: Tim Newsome <tim@sifive.com>
This commit is contained in:
Tim Newsome 2022-10-06 11:42:55 -07:00
parent 5a48975118
commit e5f9024bb0
1 changed files with 81 additions and 108 deletions
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63
src/target/riscv/riscv.c
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@ -2266,13 +2266,28 @@ exit:
int riscv_openocd_poll(struct target *target)
{
LOG_DEBUG("polling all harts");
enum target_state old_state = target->state;
struct list_head *targets;
LIST_HEAD(single_target_list);
struct target_list single_target_entry = {
.lh = {NULL, NULL},
.target = target
};
if (target->smp) {
targets = target->smp_targets;
} else {
/* Make a list that just contains a single target, so we can
* share code below. */
list_add(&single_target_entry.lh, &single_target_list);
targets = &single_target_list;
}
unsigned should_remain_halted = 0;
unsigned should_resume = 0;
struct target_list *list;
foreach_smp_target(list, target->smp_targets) {
foreach_smp_target(list, targets) {
struct target *t = list->target;
if (!target_was_examined(t))
continue;
@ -2332,7 +2347,7 @@ int riscv_openocd_poll(struct target *target)
}
/* Sample memory if any target is running. */
foreach_smp_target(list, target->smp_targets) {
foreach_smp_target(list, targets) {
struct target *t = list->target;
if (t->state == TARGET_RUNNING) {
sample_memory(target);
@ -2340,48 +2355,6 @@ int riscv_openocd_poll(struct target *target)
}
}
return ERROR_OK;
} else {
enum riscv_poll_hart out = riscv_poll_hart(target, target->coreid);
if (out == RPH_NO_CHANGE || out == RPH_DISCOVERED_RUNNING) {
if (target->state == TARGET_RUNNING)
sample_memory(target);
return ERROR_OK;
} else if (out == RPH_ERROR) {
return ERROR_FAIL;
}
LOG_TARGET_DEBUG(target, "hart halted");
target->state = TARGET_HALTED;
enum riscv_halt_reason halt_reason = riscv_halt_reason(target);
if (set_debug_reason(target, halt_reason) != ERROR_OK)
return ERROR_FAIL;
target->state = TARGET_HALTED;
}
if (target->debug_reason == DBG_REASON_BREAKPOINT) {
int retval;
switch (riscv_semihosting(target, &retval)) {
case SEMI_NONE:
case SEMI_WAITING:
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
break;
case SEMI_HANDLED:
if (riscv_resume(target, true, 0, 0, 0, false) != ERROR_OK)
return ERROR_FAIL;
break;
case SEMI_ERROR:
return retval;
}
} else {
if (old_state == TARGET_DEBUG_RUNNING)
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED);
else
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
return ERROR_OK;
}