aarch64: clean up struct aarch64_common
remove some rarely or completely unused components. Change-Id: Id285bb7075901016297fa173a874db7f11a840d7 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3992 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
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@ -331,7 +331,6 @@ static int aarch64_poll(struct target *target)
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armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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aarch64->cpudbg_dscr = dscr;
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if (DSCR_RUN_MODE(dscr) == 0x3) {
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if (prev_target_state != TARGET_HALTED) {
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@ -601,21 +600,27 @@ static int aarch64_resume(struct target *target, int current,
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static int aarch64_debug_entry(struct target *target)
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{
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int retval = ERROR_OK;
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struct aarch64_common *aarch64 = target_to_aarch64(target);
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = &armv8->dpm;
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enum arm_state core_state;
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LOG_DEBUG("%s dscr = 0x%08" PRIx32, target_name(target), aarch64->cpudbg_dscr);
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dpm->dscr = aarch64->cpudbg_dscr;
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core_state = armv8_dpm_get_core_state(dpm);
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armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
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armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
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uint32_t dscr;
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/* make sure to clear all sticky errors */
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retval = mem_ap_write_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
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if (retval == ERROR_OK)
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("%s dscr = 0x%08" PRIx32, target_name(target), dscr);
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dpm->dscr = dscr;
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core_state = armv8_dpm_get_core_state(dpm);
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armv8_select_opcodes(armv8, core_state == ARM_STATE_AARCH64);
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armv8_select_reg_access(armv8, core_state == ARM_STATE_AARCH64);
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/* discard async exceptions */
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if (retval == ERROR_OK)
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@ -625,7 +630,7 @@ static int aarch64_debug_entry(struct target *target)
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return retval;
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/* Examine debug reason */
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armv8_dpm_report_dscr(dpm, aarch64->cpudbg_dscr);
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armv8_dpm_report_dscr(dpm, dscr);
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/* save address of instruction that triggered the watchpoint? */
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if (target->debug_reason == DBG_REASON_WATCHPOINT) {
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@ -717,7 +722,6 @@ static int aarch64_post_debug_entry(struct target *target)
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(aarch64->system_control_reg & 0x4U) ? 1 : 0;
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armv8->armv8_mmu.armv8_cache.i_cache_enabled =
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(aarch64->system_control_reg & 0x1000U) ? 1 : 0;
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aarch64->curr_mode = armv8->arm.core_mode;
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return ERROR_OK;
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}
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@ -1893,8 +1897,6 @@ static int aarch64_init_arch_info(struct target *target,
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armv8->arm.dap = tap->dap;
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aarch64->fast_reg_read = 0;
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/* register arch-specific functions */
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armv8->examine_debug_reason = NULL;
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@ -48,25 +48,16 @@ struct aarch64_common {
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int common_magic;
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/* Context information */
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uint32_t cpudbg_dscr;
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uint32_t system_control_reg;
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uint32_t system_control_reg_curr;
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enum arm_mode curr_mode;
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/* Breakpoint register pairs */
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int brp_num_context;
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int brp_num;
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int brp_num_available;
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struct aarch64_brp *brp_list;
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/* Use aarch64_read_regs_through_mem for fast register reads */
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int fast_reg_read;
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struct armv8_common armv8_common;
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};
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static inline struct aarch64_common *
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