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David Brownell <david-b@pacbell.net> split EK board support out 

from the target CPU support .

git-svn-id: svn://svn.berlios.de/openocd/trunk@2504 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2009-07-10 07:21:12 +00:00
parent 3cf4717a2a
commit e4cff09137
2 changed files with 28 additions and 24 deletions
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17
tcl/board/ek-lm3s3748.cfg Normal file
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@ -0,0 +1,17 @@
# Stellaris lm3s3748 Evaluation Kit
# http://www.luminarymicro.com/products/lm3s3748_usb_h_d_evaluation_kits.html
# NOTE: to use the on-board FT2232 JTAG interface:
# source [find interface/luminary.cfg]
source [find target/lm3s3748.cfg]
# LM3S parts don't support RTCK
jtag_khz 500
jtag_nsrst_delay 100
jtag_ntrst_delay 100
# Board has only srst
reset_config srst_only

35
tcl/target/lm3s3748.cfg
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@ -1,7 +1,4 @@
# Script for luminary lm3s3748 # TI/Luminary Stellaris lm3s3748
#
# NB! work in progress! Duplicated from lm3s811.cfg, but does
# it need modification??
if { [info exists CHIPNAME] } { if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME set _CHIPNAME $CHIPNAME
@ -19,31 +16,21 @@ if { [info exists ENDIAN] } {
if { [info exists CPUTAPID ] } { if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID set _CPUTAPID $CPUTAPID
} else { } else {
# force an error till we get a good number
set _CPUTAPID 0x3ba00477 set _CPUTAPID 0x3ba00477
} }
# RCLK # JTAG scan chain
jtag_khz 500
jtag_nsrst_delay 100
jtag_ntrst_delay 100
#lm3s3748 Evaluation Board has only srst
reset_config srst_only
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
# The "lm3s" variant works around an erratum when using Rev A of "DustDevil"
# parts (third generation, includes LM3S3748). It keeps the debug registers
# from being cleared, by using software reset not SRST; NOP on newer revs.
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN \
-chain-position $_TARGETNAME -variant lm3s
# the luminary variant causes a software reset rather than asserting SRST # 8k working area at base of ram, not backed up
# this stops the debug registers from being cleared $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
# this will be fixed in later revisions of silicon
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
# 8k working area at base of ram # flash configuration -- one bank of 128K
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
#flash configuration
flash bank stellaris 0 0 0 0 0 flash bank stellaris 0 0 0 0 0