pld: add support for lattice certus devices
Change-Id: Ic50a724e5793000fca11f35ba848c2d317c3cbab Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7398 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Daniel Anselmi
Antonio Borneo
parent
cf596a61db
commit
e33eae340d
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@ -8497,10 +8497,10 @@ for FPGA @var{num}.
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@deffn {FPGA Driver} {lattice} [family]
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The FGPA families ECP2, ECP3 and ECP5 by Lattice are supported.
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The FGPA families ECP2, ECP3, ECP5, Certus and CertusPro by Lattice are supported.
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This driver can be used to load the bitstream into the FPGA or read the status register and read/write the usercode register.
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The option @option{family} is one of @var{ecp2 ecp3 ecp5}. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
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The option @option{family} is one of @var{ecp2 ecp3 ecp5 certus}. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
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@deffn {Command} {lattice read_status} num
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Reads and displays the status register
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@ -2,6 +2,7 @@
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noinst_LTLIBRARIES += %D%/libpld.la
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%C%_libpld_la_SOURCES = \
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%D%/certus.c \
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%D%/ecp2_3.c \
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%D%/ecp5.c \
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%D%/lattice.c \
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@ -10,6 +11,7 @@ noinst_LTLIBRARIES += %D%/libpld.la
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%D%/raw_bit.c \
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%D%/xilinx_bit.c \
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%D%/virtex2.c \
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%D%/certus.h \
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%D%/ecp2_3.h \
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%D%/ecp5.h \
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%D%/lattice.h \
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@ -0,0 +1,232 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/***************************************************************************
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* Copyright (C) 2022 by Daniel Anselmi *
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* danselmi@gmx.ch *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "lattice.h"
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#include "lattice_cmd.h"
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#define LSC_ENABLE_X 0x74
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#define LSC_REFRESH 0x79
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#define LSC_DEVICE_CTRL 0x7D
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int lattice_certus_read_status(struct jtag_tap *tap, uint64_t *status, uint64_t out)
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{
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return lattice_read_u64_register(tap, LSC_READ_STATUS, status, out);
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}
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int lattice_certus_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out)
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{
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return lattice_read_u32_register(tap, READ_USERCODE, usercode, out, false);
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}
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int lattice_certus_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode)
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{
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LOG_ERROR("Not supported to write usercode on certus devices");
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return ERROR_FAIL;
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}
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static int lattice_certus_enable_transparent_mode(struct jtag_tap *tap)
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{
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struct scan_field field;
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int retval = lattice_set_instr(tap, LSC_ENABLE_X, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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uint8_t buffer = 0x0;
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field.num_bits = 8;
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field.out_value = &buffer;
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field.in_value = NULL;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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jtag_add_runtest(2, TAP_IDLE);
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return jtag_execute_queue();
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}
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static int lattice_certus_erase_device(struct lattice_pld_device *lattice_device)
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{
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struct jtag_tap *tap = lattice_device->tap;
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if (!tap)
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return ERROR_FAIL;
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int retval = lattice_set_instr(tap, LSC_DEVICE_CTRL, TAP_IRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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struct scan_field field;
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uint8_t buffer = 8;
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field.num_bits = 8;
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field.out_value = &buffer;
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field.in_value = NULL;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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jtag_add_runtest(2, TAP_IDLE);
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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retval = lattice_set_instr(tap, LSC_DEVICE_CTRL, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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buffer = 0;
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field.num_bits = 8;
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field.out_value = &buffer;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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jtag_add_runtest(2, TAP_IDLE);
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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retval = lattice_set_instr(tap, ISC_ERASE, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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buffer = 0;
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field.num_bits = 8;
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field.out_value = &buffer;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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jtag_add_runtest(100, TAP_IDLE);
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jtag_add_sleep(5000);
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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/* check done is cleared and fail is cleared */
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const uint64_t status_done_flag = 0x100;
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const uint64_t status_fail_flag = 0x2000;
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return lattice_verify_status_register_u64(lattice_device, 0x0, 0x0, status_done_flag | status_fail_flag);
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}
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static int lattice_certus_enable_programming(struct jtag_tap *tap)
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{
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struct scan_field field;
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int retval = lattice_set_instr(tap, LSC_REFRESH, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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jtag_add_runtest(2, TAP_IDLE);
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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uint8_t buffer = 0;
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field.num_bits = 8;
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field.out_value = &buffer;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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jtag_add_runtest(2, TAP_IDLE);
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return jtag_execute_queue();
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}
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static int lattice_certus_init_address(struct jtag_tap *tap)
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{
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int retval = lattice_set_instr(tap, LSC_INIT_ADDRESS, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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jtag_add_runtest(2, TAP_IDLE);
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return jtag_execute_queue();
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}
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static int lattice_certus_exit_programming_mode(struct jtag_tap *tap)
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{
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int retval = lattice_set_instr(tap, ISC_DISABLE, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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jtag_add_runtest(2, TAP_IDLE);
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retval = lattice_set_instr(tap, BYPASS, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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jtag_add_runtest(100, TAP_IDLE);
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return jtag_execute_queue();
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}
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static int lattice_certus_program_config_map(struct jtag_tap *tap, struct lattice_bit_file *bit_file)
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{
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struct scan_field field;
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int retval = lattice_set_instr(tap, LSC_BITSTREAM_BURST, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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field.num_bits = (bit_file->raw_bit.length - bit_file->offset) * 8;
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field.out_value = bit_file->raw_bit.data + bit_file->offset;
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field.in_value = NULL;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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return jtag_execute_queue();
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}
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int lattice_certus_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file)
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{
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struct jtag_tap *tap = lattice_device->tap;
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if (!tap)
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return ERROR_FAIL;
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int retval = lattice_preload(lattice_device);
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if (retval != ERROR_OK)
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return retval;
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/* check password protection is disabled */
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const uint64_t status_pwd_protection = 0x20000;
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retval = lattice_verify_status_register_u64(lattice_device, 0x0, 0x0, status_pwd_protection);
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if (retval != ERROR_OK) {
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LOG_ERROR("Password protection is set");
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return retval;
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}
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retval = lattice_certus_enable_transparent_mode(tap);
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if (retval != ERROR_OK)
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return retval;
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/* Check the SRAM Erase Lock */
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const uint64_t status_otp = 0x40;
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retval = lattice_verify_status_register_u64(lattice_device, 0x0, status_otp, status_otp);
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if (retval != ERROR_OK) {
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LOG_ERROR("NV User Feature Sector OTP is Set");
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return retval;
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}
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/* Check the SRAM Lock */
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const uint64_t status_write_protected = 0x400;
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retval = lattice_verify_status_register_u64(lattice_device, 0x0, 0x0, status_write_protected);
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if (retval != ERROR_OK) {
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LOG_ERROR("NV User Feature Sector OTP is Set");
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return retval;
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}
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retval = lattice_certus_enable_programming(tap);
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if (retval != ERROR_OK) {
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LOG_ERROR("failed to enable programming mode");
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return retval;
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}
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retval = lattice_certus_erase_device(lattice_device);
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if (retval != ERROR_OK) {
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LOG_ERROR("erasing device failed");
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return retval;
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}
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retval = lattice_certus_init_address(tap);
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if (retval != ERROR_OK)
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return retval;
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retval = lattice_certus_program_config_map(tap, bit_file);
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if (retval != ERROR_OK)
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return retval;
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const uint32_t expected = 0x100; // done
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const uint32_t mask = expected |
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0x3000 | // Busy Flag and Fail Flag
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0xf000000; // BSE Error
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retval = lattice_verify_status_register_u64(lattice_device, 0x0, 0x100, mask);
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if (retval != ERROR_OK)
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return retval;
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return lattice_certus_exit_programming_mode(tap);
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}
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@ -0,0 +1,18 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/***************************************************************************
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* Copyright (C) 2022 by Daniel Anselmi *
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* danselmi@gmx.ch *
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***************************************************************************/
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#ifndef OPENOCD_PLD_CERTUS_H
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#define OPENOCD_PLD_CERTUS_H
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#include "lattice.h"
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int lattice_certus_read_status(struct jtag_tap *tap, uint64_t *status, uint64_t out);
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int lattice_certus_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out);
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int lattice_certus_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode);
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int lattice_certus_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file);
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#endif /* OPENOCD_PLD_CERTUS_H */
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@ -15,6 +15,7 @@
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#include "lattice_bit.h"
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#include "ecp2_3.h"
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#include "ecp5.h"
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#include "certus.h"
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#define PRELOAD 0x1C
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@ -50,6 +51,9 @@ static const struct lattice_devices_elem lattice_devices[] = {
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{0x01111043, 409, LATTICE_ECP5 /* "LAE5UM-25F" */},
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{0x01112043, 510, LATTICE_ECP5 /* "LAE5UM-45F" */},
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{0x01113043, 750, LATTICE_ECP5 /* "LAE5UM-85F" */},
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{0x310f0043, 362, LATTICE_CERTUS /* LFD2NX-17 */},
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{0x310f1043, 362, LATTICE_CERTUS /* LFD2NX-40 */},
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{0x010f4043, 362, LATTICE_CERTUS /* LFCPNX-100 */},
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};
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int lattice_set_instr(struct jtag_tap *tap, uint8_t new_instr, tap_state_t endstate)
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@ -116,6 +120,27 @@ int lattice_read_u32_register(struct jtag_tap *tap, uint8_t cmd, uint32_t *in_va
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return retval;
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}
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int lattice_read_u64_register(struct jtag_tap *tap, uint8_t cmd, uint64_t *in_val,
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uint64_t out_val)
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{
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struct scan_field field;
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uint8_t buffer[8];
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int retval = lattice_set_instr(tap, cmd, TAP_IDLE);
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if (retval != ERROR_OK)
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return retval;
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h_u64_to_le(buffer, out_val);
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field.num_bits = 64;
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field.out_value = buffer;
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field.in_value = buffer;
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jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
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retval = jtag_execute_queue();
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if (retval == ERROR_OK)
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*in_val = le_to_h_u64(buffer);
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return retval;
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}
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int lattice_preload(struct lattice_pld_device *lattice_device)
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{
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struct scan_field field;
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@ -150,6 +175,8 @@ static int lattice_read_usercode(struct lattice_pld_device *lattice_device, uint
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return lattice_ecp2_3_read_usercode(tap, usercode, out);
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else if (lattice_device->family == LATTICE_ECP5)
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return lattice_ecp5_read_usercode(tap, usercode, out);
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else if (lattice_device->family == LATTICE_CERTUS)
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return lattice_certus_read_usercode(tap, usercode, out);
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return ERROR_FAIL;
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}
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@ -177,6 +204,8 @@ static int lattice_write_usercode(struct lattice_pld_device *lattice_device, uin
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return lattice_ecp2_3_write_usercode(lattice_device, usercode);
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else if (lattice_device->family == LATTICE_ECP5)
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return lattice_ecp5_write_usercode(lattice_device, usercode);
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else if (lattice_device->family == LATTICE_CERTUS)
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return lattice_certus_write_usercode(lattice_device, usercode);
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return ERROR_FAIL;
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}
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@ -194,12 +223,22 @@ static int lattice_read_status_u32(struct lattice_pld_device *lattice_device, ui
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return ERROR_FAIL;
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}
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static int lattice_read_status_u64(struct lattice_pld_device *lattice_device, uint64_t *status,
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uint64_t out)
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{
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if (!lattice_device->tap)
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return ERROR_FAIL;
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if (lattice_device->family == LATTICE_CERTUS)
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return lattice_certus_read_status(lattice_device->tap, status, out);
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return ERROR_FAIL;
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}
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int lattice_verify_status_register_u32(struct lattice_pld_device *lattice_device, uint32_t out,
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uint32_t expected, uint32_t mask, bool do_idle)
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{
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uint32_t status;
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int retval = lattice_read_status_u32(lattice_device, &status, out, do_idle);
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if (retval != ERROR_OK)
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return retval;
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@ -212,13 +251,28 @@ int lattice_verify_status_register_u32(struct lattice_pld_device *lattice_device
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return ERROR_OK;
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}
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int lattice_verify_status_register_u64(struct lattice_pld_device *lattice_device, uint64_t out,
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uint64_t expected, uint64_t mask)
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{
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uint64_t status;
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int retval = lattice_read_status_u64(lattice_device, &status, out);
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if (retval != ERROR_OK)
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return retval;
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if ((status & mask) != expected) {
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LOG_ERROR("verifying status register failed got: 0x%08" PRIx64 " expected: 0x%08" PRIx64,
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status & mask, expected);
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return ERROR_FAIL;
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}
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return ERROR_OK;
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}
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static int lattice_load_command(struct pld_device *pld_device, const char *filename)
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{
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if (!pld_device)
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return ERROR_FAIL;
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struct lattice_pld_device *lattice_device = pld_device->driver_priv;
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if (!lattice_device || !lattice_device->tap)
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return ERROR_FAIL;
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struct jtag_tap *tap = lattice_device->tap;
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@ -245,10 +299,14 @@ static int lattice_load_command(struct pld_device *pld_device, const char *filen
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retval = lattice_ecp3_load(lattice_device, &bit_file);
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break;
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case LATTICE_ECP5:
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case LATTICE_CERTUS:
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if (bit_file.has_id && id != bit_file.idcode)
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LOG_WARNING("Id on device (0x%8.8" PRIx32 ") and id in bit-stream (0x%8.8" PRIx32 ") don't match.",
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id, bit_file.idcode);
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retval = lattice_ecp5_load(lattice_device, &bit_file);
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if (lattice_device->family == LATTICE_ECP5)
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retval = lattice_ecp5_load(lattice_device, &bit_file);
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else
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retval = lattice_certus_load(lattice_device, &bit_file);
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break;
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default:
|
||||
LOG_ERROR("loading unknown device family");
|
||||
|
|
@ -283,6 +341,8 @@ PLD_DEVICE_COMMAND_HANDLER(lattice_pld_device_command)
|
|||
family = LATTICE_ECP3;
|
||||
} else if (strcasecmp(CMD_ARGV[2], "ecp5") == 0) {
|
||||
family = LATTICE_ECP5;
|
||||
} else if (strcasecmp(CMD_ARGV[2], "certus") == 0) {
|
||||
family = LATTICE_CERTUS;
|
||||
} else {
|
||||
command_print(CMD, "unknown family");
|
||||
free(lattice_device);
|
||||
|
|
@ -405,11 +465,18 @@ COMMAND_HANDLER(lattice_read_status_command_handler)
|
|||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
uint32_t status;
|
||||
const bool do_idle = lattice_device->family == LATTICE_ECP5;
|
||||
retval = lattice_read_status_u32(lattice_device, &status, 0x0, do_idle);
|
||||
if (retval == ERROR_OK)
|
||||
command_print(CMD, "0x%8.8" PRIx32, status);
|
||||
if (lattice_device->family == LATTICE_CERTUS) {
|
||||
uint64_t status;
|
||||
retval = lattice_read_status_u64(lattice_device, &status, 0x0);
|
||||
if (retval == ERROR_OK)
|
||||
command_print(CMD, "0x%016" PRIx64, status);
|
||||
} else {
|
||||
uint32_t status;
|
||||
const bool do_idle = lattice_device->family == LATTICE_ECP5;
|
||||
retval = lattice_read_status_u32(lattice_device, &status, 0x0, do_idle);
|
||||
if (retval == ERROR_OK)
|
||||
command_print(CMD, "0x%8.8" PRIx32, status);
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,10 +23,14 @@ struct lattice_pld_device {
|
|||
int lattice_set_instr(struct jtag_tap *tap, uint8_t new_instr, tap_state_t endstate);
|
||||
int lattice_read_u32_register(struct jtag_tap *tap, uint8_t cmd, uint32_t *in_val,
|
||||
uint32_t out_val, bool do_idle);
|
||||
int lattice_read_u64_register(struct jtag_tap *tap, uint8_t cmd, uint64_t *in_val,
|
||||
uint64_t out_val);
|
||||
int lattice_verify_usercode(struct lattice_pld_device *lattice_device, uint32_t out,
|
||||
uint32_t expected, uint32_t mask);
|
||||
int lattice_verify_status_register_u32(struct lattice_pld_device *lattice_device, uint32_t out,
|
||||
uint32_t expected, uint32_t mask, bool do_idle);
|
||||
int lattice_verify_status_register_u64(struct lattice_pld_device *lattice_device, uint64_t out,
|
||||
uint64_t expected, uint64_t mask);
|
||||
int lattice_preload(struct lattice_pld_device *lattice_device);
|
||||
|
||||
#endif /* OPENOCD_PLD_LATTICE_H */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,14 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
# https://www.latticesemi.com/products/developmentboardsandkits/certuspro-nx-versa-board
|
||||
|
||||
adapter driver ftdi
|
||||
ftdi vid_pid 0x0403 0x6010
|
||||
|
||||
ftdi channel 0
|
||||
ftdi layout_init 0x0008 0x008b
|
||||
reset_config none
|
||||
transport select jtag
|
||||
adapter speed 10000
|
||||
|
||||
source [find fpga/lattice_certuspro.cfg]
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME certus
|
||||
}
|
||||
|
||||
# Lattice Certus
|
||||
#
|
||||
# Certus NX LFD2NX-17 0x310f0043
|
||||
# Certus NX LFD2NX-40 0x310f1043
|
||||
|
||||
|
||||
jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
|
||||
-expected-id 0x310F1043 -expected-id 0x310F0043
|
||||
|
||||
pld device lattice $_CHIPNAME.tap
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME certuspro
|
||||
}
|
||||
|
||||
# Lattice CertusPro
|
||||
#
|
||||
# 0x010f4043 - LFCPNX-100
|
||||
# 0x 043 - LFCPNX-50
|
||||
|
||||
jtag newtap $_CHIPNAME tap -irlen 8 -irmask 0x83 -ircapture 0x1 \
|
||||
-expected-id 0x010f4043
|
||||
# -expected-id 0x01112043
|
||||
|
||||
pld device lattice $_CHIPNAME.tap
|
||||
Loading…
Reference in New Issue