diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 45b7ca9d6..1f1575c13 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -283,7 +283,7 @@ static void decode_dmi(char *text, unsigned address, unsigned data) { DMI_DMCONTROL, DMI_DMCONTROL_RESUMEREQ, "resumereq" }, { DMI_DMCONTROL, DMI_DMCONTROL_HARTRESET, "hartreset" }, { DMI_DMCONTROL, DMI_DMCONTROL_HASEL, "hasel" }, - { DMI_DMCONTROL, DMI_DMCONTROL_HARTSELLO, "hartsel" }, + { DMI_DMCONTROL, DMI_DMCONTROL_HARTSELLO, "hartsello" }, { DMI_DMCONTROL, DMI_DMCONTROL_NDMRESET, "ndmreset" }, { DMI_DMCONTROL, DMI_DMCONTROL_DMACTIVE, "dmactive" }, @@ -2941,7 +2941,7 @@ static int riscv013_test_sba_config_reg(struct target *target, read_sbcs_nonbusy(target, &sbcs); curr_addr = sb_read_address(target); if ((curr_addr - prev_addr != (uint32_t)(1 << sbaccess)) && (i != 0)) { - LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x", sbaccess); + LOG_ERROR("System Bus Access Test 2: Error with address auto-increment, sbaccess = %x.", sbaccess); test_passed = false; } dmi_write(target, DMI_SBDATA0, i); @@ -2968,7 +2968,7 @@ static int riscv013_test_sba_config_reg(struct target *target, read_sbcs_nonbusy(target, &sbcs); if (i != val) { LOG_ERROR("System Bus Access Test 2: Error reading auto-incremented address," - "expected val = %x, read val = %x", i, val); + "expected val = %x, read val = %x.", i, val); test_passed = false; } } @@ -3000,7 +3000,7 @@ static int riscv013_test_sba_config_reg(struct target *target, sbcs = set_field(sbcs_orig, DMI_SBCS_SBERROR, 2); dmi_write(target, DMI_SBCS,sbcs); dmi_read(target, &rd_val, DMI_SBCS); - if(get_field(rd_val, DMI_SBCS_SBERROR) == 0) + if (get_field(rd_val, DMI_SBCS_SBERROR) == 0) LOG_INFO("System Bus Access Test 4: Illegal address write test PASSED."); else LOG_ERROR("System Bus Access Test 4: Illegal address write test FAILED, unable to clear to 0.");