flash/nor/eneispif: support ENE KB1200 ispi flash
Change-Id: I03bccceb1956ee121e6a3728b7d647ef1262fa23 Signed-off-by: Steven Chang <steven@ene.com.tw> Reviewed-on: https://review.openocd.org/c/openocd/+/8136 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Steven Chang
Tomas Vanek
parent
a35e254c53
commit
dd17582722
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@ -6776,6 +6776,24 @@ Note that in order for this command to take effect, the target needs to be reset
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supported.}
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@end deffn
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@deffn {Flash Driver} {eneispif}
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All versions of the KB1200 microcontrollers from ENE include internal
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flash. The eneispif flash driver supports the KB1200 family of devices. The driver
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automatically recognizes the specific version's flash parameters and
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autoconfigures itself. The flash bank starts at address 0x60000000. An optional additional
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parameter sets the address of eneispif controller, with the default address is 0x50101000.
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@example
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flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME \
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0x50101000
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# Address defaults to 0x50101000
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flash bank $_FLASHNAME eneispif 0x60000000 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} {esirisc}
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Members of the eSi-RISC family may optionally include internal flash programmed
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via the eSi-TSMC Flash interface. Additional parameters are required to
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@ -28,6 +28,7 @@ NOR_DRIVERS = \
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%D%/dsp5680xx_flash.c \
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%D%/efm32.c \
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%D%/em357.c \
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%D%/eneispif.c \
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%D%/esirisc_flash.c \
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%D%/faux.c \
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%D%/fespi.c \
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@ -256,6 +256,7 @@ extern const struct flash_driver cfi_flash;
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extern const struct flash_driver dsp5680xx_flash;
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extern const struct flash_driver efm32_flash;
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extern const struct flash_driver em357_flash;
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extern const struct flash_driver eneispif_flash;
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extern const struct flash_driver esirisc_flash;
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extern const struct flash_driver faux_flash;
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extern const struct flash_driver fespi_flash;
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@ -33,6 +33,7 @@ static const struct flash_driver * const flash_drivers[] = {
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&dsp5680xx_flash,
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&efm32_flash,
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&em357_flash,
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&eneispif_flash,
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&esirisc_flash,
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&faux_flash,
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&fm3_flash,
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@ -0,0 +1,433 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2024 ENE Technology Inc.
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* steven@ene.com.tw
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*/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include <helper/time_support.h>
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#include <helper/bits.h>
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#include <target/target.h>
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#include <flash/nor/core.h>
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#include <flash/nor/driver.h>
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#include <flash/nor/spi.h>
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#define ISPICFG 0x0000
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#define ISPISTS 0x0004
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#define ISPIADDR 0x0008
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#define ISPICMD 0x000C
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#define ISPIDAT 0x0100
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#define ISPISTS_BUSY BIT(0)
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#define STATUS1_QE BIT(1)
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#define CFG_READ 0x372
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#define CFG_WRITE 0x371
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#define ISPI_CTRL_BASE 0x50101000
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/* name read qread page erase chip device_id page erase flash
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* _cmd _cmd _prog _cmd* _erase size size* size
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* _cmd _cmd
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*/
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struct flash_device ene_flash_device =
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FLASH_ID("ISPI flash", 0x03, 0x00, 0x02, 0x20, 0x60, 0x00132085, 0x100, 0x1000, 0x80000);
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struct eneispif_flash_bank {
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bool probed;
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target_addr_t ctrl_base;
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uint32_t dev_id;
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const struct flash_device *dev;
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};
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FLASH_BANK_COMMAND_HANDLER(eneispif_flash_bank_command)
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{
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struct eneispif_flash_bank *eneispif_info;
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LOG_DEBUG("%s", __func__);
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if (CMD_ARGC < 6)
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return ERROR_COMMAND_SYNTAX_ERROR;
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eneispif_info = malloc(sizeof(struct eneispif_flash_bank));
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if (!eneispif_info) {
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LOG_ERROR("not enough memory");
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return ERROR_FAIL;
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}
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bank->driver_priv = eneispif_info;
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eneispif_info->probed = false;
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eneispif_info->ctrl_base = ISPI_CTRL_BASE;
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if (CMD_ARGC >= 7) {
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COMMAND_PARSE_ADDRESS(CMD_ARGV[6], eneispif_info->ctrl_base);
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LOG_INFO("ASSUMING ISPI device at ctrl_base = " TARGET_ADDR_FMT,
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eneispif_info->ctrl_base);
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}
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return ERROR_OK;
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}
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static int eneispif_read_reg(struct flash_bank *bank, uint32_t *value, target_addr_t address)
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{
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struct target *target = bank->target;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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int result = target_read_u32(target, eneispif_info->ctrl_base + address, value);
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if (result != ERROR_OK) {
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LOG_ERROR("%s error at " TARGET_ADDR_FMT, __func__,
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eneispif_info->ctrl_base + address);
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return result;
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}
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LOG_DEBUG("Read address " TARGET_ADDR_FMT " = 0x%" PRIx32,
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eneispif_info->ctrl_base + address, *value);
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return ERROR_OK;
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}
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static int eneispif_write_reg(struct flash_bank *bank, target_addr_t address, uint32_t value)
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{
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struct target *target = bank->target;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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LOG_DEBUG("Write address " TARGET_ADDR_FMT " = 0x%" PRIx32,
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eneispif_info->ctrl_base + address, value);
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int result = target_write_u32(target, eneispif_info->ctrl_base + address, value);
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if (result != ERROR_OK) {
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LOG_ERROR("%s error writing 0x%" PRIx32 " to " TARGET_ADDR_FMT, __func__,
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value, eneispif_info->ctrl_base + address);
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return result;
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}
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return ERROR_OK;
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}
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static int eneispif_wait(struct flash_bank *bank)
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{
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int64_t start = timeval_ms();
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while (1) {
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uint32_t status;
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if (eneispif_read_reg(bank, &status, ISPISTS) != ERROR_OK)
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return ERROR_FAIL;
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if (!(status & ISPISTS_BUSY))
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break;
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int64_t now = timeval_ms();
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if (now - start > 1000) {
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LOG_ERROR("Busy more than 1000ms.");
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return ERROR_TARGET_TIMEOUT;
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}
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}
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return ERROR_OK;
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}
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static int eneispi_erase_sector(struct flash_bank *bank, int sector)
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{
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int retval = ERROR_OK;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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uint32_t offset;
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uint32_t conf;
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retval = eneispif_read_reg(bank, &conf, ISPICFG);
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if (retval != ERROR_OK)
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return retval;
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offset = bank->sectors[sector].offset;
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retval = eneispif_write_reg(bank, ISPIADDR, offset); /* Address */
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if (retval != ERROR_OK)
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goto done;
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eneispif_write_reg(bank, ISPICFG, CFG_WRITE); /* Cmmmand enable */
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eneispif_write_reg(bank, ISPICMD, SPIFLASH_WRITE_ENABLE); /* Write enable */
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retval = eneispif_write_reg(bank, ISPICMD, eneispif_info->dev->erase_cmd); /* Erase page */
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if (retval != ERROR_OK)
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goto done;
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retval = eneispif_wait(bank);
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if (retval != ERROR_OK)
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goto done;
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done:
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eneispif_write_reg(bank, ISPICFG, conf); /* restore */
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return retval;
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}
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static int eneispif_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
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{
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struct target *target = bank->target;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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int retval = ERROR_OK;
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LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (last < first || last >= bank->num_sectors) {
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LOG_ERROR("Flash sector invalid");
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return ERROR_FLASH_SECTOR_INVALID;
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}
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if (!(eneispif_info->probed)) {
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LOG_ERROR("Flash bank not probed");
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return ERROR_FLASH_BANK_NOT_PROBED;
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}
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for (unsigned int sector = first; sector <= last; sector++) {
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if (bank->sectors[sector].is_protected) {
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LOG_ERROR("Flash sector %u protected", sector);
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return ERROR_FAIL;
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}
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}
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if (eneispif_info->dev->erase_cmd == 0x00)
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return ERROR_FLASH_OPER_UNSUPPORTED;
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for (unsigned int sector = first; sector <= last; sector++) {
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retval = eneispi_erase_sector(bank, sector);
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if (retval != ERROR_OK)
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break;
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}
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return retval;
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}
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static int eneispif_protect(struct flash_bank *bank, int set, unsigned int first, unsigned int last)
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{
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for (unsigned int sector = first; sector <= last; sector++)
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bank->sectors[sector].is_protected = set;
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return ERROR_OK;
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}
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static int eneispif_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset,
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uint32_t count)
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{
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struct target *target = bank->target;
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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uint32_t page_size;
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uint32_t conf;
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int retval = ERROR_OK;
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LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32, bank->size, offset,
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count);
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (offset + count > eneispif_info->dev->size_in_bytes) {
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LOG_WARNING("Write past end of flash. Extra data discarded.");
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count = eneispif_info->dev->size_in_bytes - offset;
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}
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/* Check sector protection */
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for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
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/* Start offset in or before this sector? */
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/* End offset in or behind this sector? */
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if ((offset < (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
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((offset + count - 1) >= bank->sectors[sector].offset) &&
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bank->sectors[sector].is_protected) {
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LOG_ERROR("Flash sector %u protected", sector);
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return ERROR_FAIL;
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}
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}
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retval = eneispif_read_reg(bank, &conf, ISPICFG);
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if (retval != ERROR_OK)
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return retval;
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eneispif_write_reg(bank, ISPICFG, CFG_WRITE); // Cmmmand enable
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/* If no valid page_size, use reasonable default. */
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page_size =
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eneispif_info->dev->pagesize ? eneispif_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
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uint32_t page_offset = offset % page_size;
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while (count > 0) {
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uint32_t cur_count;
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/* clip block at page boundary */
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if (page_offset + count > page_size)
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cur_count = page_size - page_offset;
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else
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cur_count = count;
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eneispif_write_reg(bank, ISPICMD, SPIFLASH_WRITE_ENABLE); /* Write enable */
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target_write_buffer(target, eneispif_info->ctrl_base + ISPIDAT, cur_count, buffer);
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eneispif_write_reg(bank, ISPIADDR, offset);
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retval = eneispif_write_reg(bank, ISPICMD,
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(cur_count << 16) | eneispif_info->dev->pprog_cmd);
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if (retval != ERROR_OK)
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goto err;
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page_offset = 0;
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buffer += cur_count;
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offset += cur_count;
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count -= cur_count;
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retval = eneispif_wait(bank);
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if (retval != ERROR_OK)
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goto err;
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}
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err:
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eneispif_write_reg(bank, ISPICFG, conf); /* restore */
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return retval;
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}
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/* Return ID of flash device */
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/* On exit, SW mode is kept */
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static int eneispif_read_flash_id(struct flash_bank *bank, uint32_t *id)
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{
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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struct target *target = bank->target;
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int retval;
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uint32_t conf, value;
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uint8_t buffer[4];
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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retval = eneispif_read_reg(bank, &conf, ISPICFG);
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if (retval != ERROR_OK)
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return retval;
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LOG_DEBUG("ISPCFG = (0x%08" PRIx32 ")", conf);
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/* read ID from Receive Register */
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eneispif_write_reg(bank, ISPICFG, CFG_WRITE); /* Cmmmand enable */
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retval = eneispif_write_reg(bank, ISPICMD, (3 << 16) | SPIFLASH_READ_ID);
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if (retval != ERROR_OK)
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goto done;
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retval = eneispif_wait(bank);
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if (retval != ERROR_OK)
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goto done;
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retval = target_read_buffer(target, eneispif_info->ctrl_base + ISPIDAT, 3, buffer);
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if (retval != ERROR_OK)
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goto done;
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value = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0];
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LOG_DEBUG("ISPDAT = (0x%08" PRIx32 ")", value);
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*id = value;
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done:
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eneispif_write_reg(bank, ISPICFG, conf); // restore
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return retval;
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}
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static int eneispif_probe(struct flash_bank *bank)
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{
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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struct flash_sector *sectors;
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uint32_t id;
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int retval;
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uint32_t sectorsize;
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if (eneispif_info->probed)
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free(bank->sectors);
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eneispif_info->probed = false;
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LOG_INFO("Assuming ISPI flash at address " TARGET_ADDR_FMT
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" with controller at " TARGET_ADDR_FMT,
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bank->base, eneispif_info->ctrl_base);
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eneispif_write_reg(bank, ISPICFG, CFG_READ); /* RAM map enable */
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retval = eneispif_read_flash_id(bank, &id);
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if (retval != ERROR_OK)
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return retval;
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eneispif_info->dev_id = id;
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eneispif_info->dev = &ene_flash_device;
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LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")", eneispif_info->dev->name,
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eneispif_info->dev_id);
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/* Set correct size value */
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bank->size = eneispif_info->dev->size_in_bytes;
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if (bank->size <= (1UL << 16))
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LOG_WARNING("device needs 2-byte addresses - not implemented");
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/* if no sectors, treat whole bank as single sector */
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sectorsize = eneispif_info->dev->sectorsize ? eneispif_info->dev->sectorsize
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: eneispif_info->dev->size_in_bytes;
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/* create and fill sectors array */
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bank->num_sectors = eneispif_info->dev->size_in_bytes / sectorsize;
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sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
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if (!sectors) {
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LOG_ERROR("not enough memory");
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return ERROR_FAIL;
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}
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for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
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sectors[sector].offset = sector * sectorsize;
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sectors[sector].size = sectorsize;
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sectors[sector].is_erased = -1;
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sectors[sector].is_protected = 0;
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}
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bank->sectors = sectors;
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eneispif_info->probed = true;
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return ERROR_OK;
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}
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static int eneispif_auto_probe(struct flash_bank *bank)
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{
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struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
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if (eneispif_info->probed)
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return ERROR_OK;
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return eneispif_probe(bank);
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}
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static int eneispif_protect_check(struct flash_bank *bank)
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{
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/* Nothing to do. Protection is only handled in SW. */
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return ERROR_OK;
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}
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static int get_eneispif_info(struct flash_bank *bank, struct command_invocation *cmd)
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{
|
||||
struct eneispif_flash_bank *eneispif_info = bank->driver_priv;
|
||||
|
||||
if (!(eneispif_info->probed)) {
|
||||
command_print(cmd, "ENE ISPI flash bank not probed yet.");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
command_print(cmd,
|
||||
"ENE ISPI flash information:\n"
|
||||
" Device \'%s\' (ID 0x%08" PRIx32 ")",
|
||||
eneispif_info->dev->name, eneispif_info->dev_id);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
const struct flash_driver eneispif_flash = {
|
||||
.name = "eneispif",
|
||||
.usage = "flash bank <name> 'eneispif' <base_address> <size> 0 0 <target> <ctrl_base>",
|
||||
.flash_bank_command = eneispif_flash_bank_command,
|
||||
.erase = eneispif_erase,
|
||||
.protect = eneispif_protect,
|
||||
.write = eneispif_write,
|
||||
.read = default_flash_read,
|
||||
.probe = eneispif_probe,
|
||||
.auto_probe = eneispif_auto_probe,
|
||||
.erase_check = default_flash_blank_check,
|
||||
.protect_check = eneispif_protect_check,
|
||||
.info = get_eneispif_info,
|
||||
.free_driver_priv = default_flash_free_driver_priv,
|
||||
};
|
||||
Loading…
Reference in New Issue