Single memory reads/writes work.
This commit is contained in:
Tim Newsome
parent
39788e5e6b
commit
dce4a992a3
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@ -119,6 +119,7 @@ static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
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MATCH_FLW;
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}
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/*
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static uint32_t li(unsigned int dest, uint16_t imm)
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{
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return addi(dest, 0, imm);
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@ -131,7 +132,6 @@ static uint32_t lui(unsigned int dest, uint32_t imm)
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MATCH_LUI;
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}
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/*
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static uint32_t fence_i(void)
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{
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return MATCH_FENCE_I;
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@ -179,6 +179,7 @@ static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
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(dest << 7) |
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MATCH_ORI;
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}
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*/
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static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
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{
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@ -187,7 +188,6 @@ static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
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(dest << 7) |
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MATCH_XORI;
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}
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*/
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static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
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{
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@ -1,4 +1,5 @@
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#include <assert.h>
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#include <stdlib.h>
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#include <time.h>
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#ifdef HAVE_CONFIG_H
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@ -146,6 +147,12 @@ static struct scan_field select_dbus = {
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.in_value = NULL,
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.out_value = ir_dbus
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};
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static uint8_t ir_debug[1] = {0x5};
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static struct scan_field select_debug = {
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.in_value = NULL,
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.out_value = ir_debug
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};
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#define DEBUG_LENGTH 264
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static uint16_t dram_address(unsigned int index)
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{
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@ -155,19 +162,52 @@ static uint16_t dram_address(unsigned int index)
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return 0x40 + index - 0x10;
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}
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#if 0
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static int debug_scan(struct target *target)
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{
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uint8_t in[DIV_ROUND_UP(DEBUG_LENGTH, 8)];
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jtag_add_ir_scan(target->tap, &select_debug, TAP_IDLE);
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struct scan_field field;
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field.num_bits = DEBUG_LENGTH;
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field.out_value = NULL;
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field.check_value = NULL;
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field.check_mask = NULL;
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field.in_value = in;
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jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
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/* Always return to dbus. */
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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jtag_execute_queue();
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LOG_DEBUG(" debug_pc=0x%x", buf_get_u32(in, 0, 32));
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LOG_DEBUG(" last_returned_data=0x%x", buf_get_u32(in, 32, 32));
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LOG_DEBUG(" last_returned_pc=0x%x", buf_get_u32(in, 64, 32));
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LOG_DEBUG(" last_requested_pc=0x%x", buf_get_u32(in, 96, 32));
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LOG_DEBUG(" last_committed_instruction=0x%x", buf_get_u32(in, 128, 32));
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LOG_DEBUG(" last_committed_pc=0x%x", buf_get_u32(in, 160, 32));
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LOG_DEBUG(" last_committed_time=0x%lx", buf_get_u64(in, 192, 64));
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LOG_DEBUG(" 3bits=0x%x", buf_get_u32(in, 256, 3));
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return 0;
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}
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#endif
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static dbus_status_t dbus_scan(struct target *target, uint64_t *data_in,
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dbus_op_t op, uint16_t address, uint64_t data_out)
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{
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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struct scan_field field;
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uint8_t in[8] = {0};
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uint8_t out[8];
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struct scan_field field = {
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.num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
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.out_value = out,
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.in_value = in
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};
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assert(info->addrbits != 0);
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field.num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
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field.out_value = out;
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field.in_value = in;
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buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
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buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
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buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address);
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@ -190,6 +230,15 @@ static dbus_status_t dbus_scan(struct target *target, uint64_t *data_in,
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static const char *op_string[] = {"nop", "r", "w", "cw"};
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static const char *status_string[] = {"+", "nw", "F", "b"};
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LOG_DEBUG("vvv $display(\"hardware: dbus scan %db %s %01x:%08x @%02x -> %s %01x:%08x @%02x\");",
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field.num_bits,
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op_string[buf_get_u32(out, 0, 2)],
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buf_get_u32(out, 34, 2), buf_get_u32(out, 2, 32),
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buf_get_u32(out, 36, info->addrbits),
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status_string[buf_get_u32(in, 0, 2)],
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buf_get_u32(in, 34, 2), buf_get_u32(in, 2, 32),
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buf_get_u32(in, 36, info->addrbits));
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/*
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LOG_DEBUG("dbus scan %db %s %01x:%08x @%02x -> %s %01x:%08x @%02x",
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field.num_bits,
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op_string[buf_get_u32(out, 0, 2)],
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@ -198,6 +247,10 @@ static dbus_status_t dbus_scan(struct target *target, uint64_t *data_in,
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status_string[buf_get_u32(in, 0, 2)],
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buf_get_u32(in, 34, 2), buf_get_u32(in, 2, 32),
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buf_get_u32(in, 36, info->addrbits));
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*/
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//debug_scan(target);
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return buf_get_u64(in, DBUS_OP_START, DBUS_OP_SIZE);
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}
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@ -277,7 +330,7 @@ static void dram_write32(struct target *target, unsigned int index, uint32_t val
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info->dram_valid |= (1<<index);
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}
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#if 0
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#if 1
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static int dram_check32(struct target *target, unsigned int index,
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uint32_t expected)
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{
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@ -515,11 +568,12 @@ static int riscv_init_target(struct command_context *cmd_ctx,
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select_dtminfo.num_bits = target->tap->ir_length;
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select_dbus.num_bits = target->tap->ir_length;
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select_debug.num_bits = target->tap->ir_length;
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const unsigned int max_reg_name_len = 12;
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info->reg_list = calloc(REG_COUNT, sizeof(struct reg));
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info->reg_names = malloc(REG_COUNT * max_reg_name_len);
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info->reg_names = calloc(1, REG_COUNT * max_reg_name_len);
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char *reg_name = info->reg_names;
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info->reg_values = NULL;
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@ -655,6 +709,26 @@ static void megan_sequence(struct target *target)
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}
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#endif
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#if 0
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static void dram_test(struct target *target)
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{
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uint32_t shadow[16];
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for (int j = 0; j < 100; j++) {
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LOG_DEBUG("Round %d", j);
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for (int i = 0; i < 16; i++) {
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shadow[i] = random();
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dram_write32(target, i, shadow[i], false);
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}
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for (int i = 0; i < 16; i++) {
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if (dram_check32(target, i, shadow[i]) != ERROR_OK) {
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LOG_ERROR("Mismatch! j=%d i=%d", j, i);
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}
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}
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}
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}
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#endif
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static int riscv_examine(struct target *target)
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{
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LOG_DEBUG("riscv_examine()");
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@ -703,7 +777,8 @@ static int riscv_examine(struct target *target)
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return ERROR_FAIL;
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}
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#if 0
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//dram_test(target);
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// Figure out XLEN.
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dram_write32(target, 0, xori(S1, ZERO, -1), false);
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// 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff
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@ -734,66 +809,13 @@ static int riscv_examine(struct target *target)
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dram_write_jump(target, 5, true);
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#endif
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dram_write32(target, info->dramsize - 1, 0xdeadbeef, false);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#else
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#if 1
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// Blue blue red
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dram_write32(target, 1, nop(), false);
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dram_write32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 0, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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#if 0
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// no effect
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dram_write32(target, 1, ~nop(), false);
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dram_write32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 0, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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srli(0,0,0);nop(); // TODO
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#if 0
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// Blue blue red red
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dram_write32(target, 0, nop(), false);
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dram_write32(target, 1, nop(), false);
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dram_write32(target, 2, sw(S1, ZERO, DEBUG_RAM_START), false);
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dram_write32(target, 3, srli(S1, S1, 31), false);
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dram_write32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 5, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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#if 0
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// Blue off red red
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dram_write32(target, 0, nop(), false);
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dram_write32(target, 1, sw(S1, ZERO, DEBUG_RAM_START), false);
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dram_write32(target, 2, srli(S1, S1, 31), false);
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dram_write32(target, 3, sw(S1, ZERO, DEBUG_RAM_START + 4), false);
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dram_write_jump(target, 4, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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#endif
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#endif
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#if 0
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uint32_t word0 = dram_read32(target, 0);
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uint32_t word1 = dram_read32(target, 1);
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if (word0 == 1 && word1 == 0) {
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@ -803,43 +825,16 @@ static int riscv_examine(struct target *target)
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} else if (word0 == 0xffffffff && word1 == 0xffffffff) {
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info->xlen = 128;
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} else {
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LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x",
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word0, word1);
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uint32_t exception = dram_read32(target, info->dramsize-1);
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LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
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word0, word1, exception);
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return ERROR_FAIL;
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}
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LOG_DEBUG("Discovered XLEN is %d", info->xlen);
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#else
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info->xlen = 32;
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#endif
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// Update register list to match discovered XLEN.
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update_reg_list(target);
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// TODO
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// smoke test
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//dram_write32(target, 4, 0x700020a0, false);
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//dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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//dram_write32(target, 1, sw(ZERO, S0, 0), false);
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//dram_write32(target, 2, jal(ZERO, 0), true);
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//dram_write_jump(target, 2, true);
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li(0,0); // TODO: remove
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dram_write32(target, 0, lui(S0, 0x70002), false);
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dram_write32(target, 1, lui(S1, 0xccccc), false);
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dram_write32(target, 2, sw(S1, S0, 0xa0), false);
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dram_write32(target, 3, jal(ZERO, 0), true);
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// 400: 70002437 lui s0,0x70002
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// 404: 0a000493 li s1,160
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// 408: 0a942023 sw s1,160(s0) # 700020a0 <debug_ram+0x70001ca0>
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// 40c: 0000006f j 40c <debug_ram+0xc>
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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dram_read32(target, 4);
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target_set_examined(target);
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return ERROR_OK;
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@ -938,6 +933,8 @@ static int riscv_read_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer)
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{
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jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
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#if 0
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// Plain implementation, where we write the address each time.
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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switch (size) {
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@ -996,6 +993,54 @@ static int riscv_read_memory(struct target *target, uint32_t address,
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return ERROR_FAIL;
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}
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}
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#else
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dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
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switch (size) {
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case 1:
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dram_write32(target, 1, lb(S1, S0, 0), false);
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dram_write32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16), false);
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break;
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case 2:
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dram_write32(target, 1, lh(S1, S0, 0), false);
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dram_write32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16), false);
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break;
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case 4:
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dram_write32(target, 1, lw(S1, S0, 0), false);
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dram_write32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16), false);
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break;
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default:
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LOG_ERROR("Unsupported size: %d", size);
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return ERROR_FAIL;
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}
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dram_write_jump(target, 3, false);
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for (unsigned int i = 0; i < count; i++) {
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dram_write32(target, 4, address + i * size, true);
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if (wait_for_debugint_clear(target) != ERROR_OK) {
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LOG_ERROR("Debug interrupt didn't clear.");
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return ERROR_FAIL;
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}
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uint32_t value = dram_read32(target, 4);
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unsigned int offset = i * size;
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switch (size) {
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case 1:
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buffer[offset] = value & 0xff;
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break;
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case 2:
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buffer[offset] = value & 0xff;
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buffer[offset + 1] = (value >> 8) & 0xff;
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break;
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case 4:
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buffer[offset] = value & 0xff;
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buffer[offset + 1] = (value >> 8) & 0xff;
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buffer[offset + 2] = (value >> 16) & 0xff;
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buffer[offset + 3] = (value >> 24) & 0xff;
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break;
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}
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}
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#endif
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return ERROR_OK;
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}
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