aarch64: make DCC read/write functions operate on struct armv8_common
Change the signature of aarch64_(read|write)_dcc[_64] to take a "struct armv8_common *" as the context to operate on. No functional change. Change-Id: Ie501113f65ea22aff2eee173ec717f6908a63494 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
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@ -234,26 +234,26 @@ static inline struct aarch64_common *dpm_to_a8(struct arm_dpm *dpm)
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return container_of(dpm, struct aarch64_common, armv8_common.dpm);
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return container_of(dpm, struct aarch64_common, armv8_common.dpm);
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}
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}
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static int aarch64_write_dcc(struct aarch64_common *a8, uint32_t data)
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static int aarch64_write_dcc(struct armv8_common *armv8, uint32_t data)
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{
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{
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LOG_DEBUG("write DCC 0x%08" PRIx32, data);
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LOG_DEBUG("write DCC 0x%08" PRIx32, data);
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return mem_ap_write_u32(a8->armv8_common.debug_ap,
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return mem_ap_write_u32(armv8->debug_ap,
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a8->armv8_common.debug_base + CPUDBG_DTRRX, data);
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armv8->debug_base + CPUDBG_DTRRX, data);
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}
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}
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static int aarch64_write_dcc_64(struct aarch64_common *a8, uint64_t data)
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static int aarch64_write_dcc_64(struct armv8_common *armv8, uint64_t data)
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{
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{
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int ret;
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int ret;
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LOG_DEBUG("write DCC 0x%08" PRIx32, (unsigned)data);
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LOG_DEBUG("write DCC Low word0x%08" PRIx32, (unsigned)data);
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LOG_DEBUG("write DCC 0x%08" PRIx32, (unsigned)(data >> 32));
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LOG_DEBUG("write DCC High word 0x%08" PRIx32, (unsigned)(data >> 32));
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ret = mem_ap_write_u32(a8->armv8_common.debug_ap,
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ret = mem_ap_write_u32(armv8->debug_ap,
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a8->armv8_common.debug_base + CPUDBG_DTRRX, data);
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armv8->debug_base + CPUDBG_DTRRX, data);
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ret += mem_ap_write_u32(a8->armv8_common.debug_ap,
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ret += mem_ap_write_u32(armv8->debug_ap,
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a8->armv8_common.debug_base + CPUDBG_DTRTX, data >> 32);
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armv8->debug_base + CPUDBG_DTRTX, data >> 32);
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return ret;
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return ret;
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}
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}
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static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
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static int aarch64_read_dcc(struct armv8_common *armv8, uint32_t *data,
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uint32_t *dscr_p)
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uint32_t *dscr_p)
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{
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{
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uint32_t dscr = DSCR_INSTR_COMP;
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uint32_t dscr = DSCR_INSTR_COMP;
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@ -265,8 +265,8 @@ static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
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/* Wait for DTRRXfull */
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/* Wait for DTRRXfull */
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long long then = timeval_ms();
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long long then = timeval_ms();
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while ((dscr & DSCR_DTR_TX_FULL) == 0) {
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while ((dscr & DSCR_DTR_TX_FULL) == 0) {
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retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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a8->armv8_common.debug_base + CPUDBG_DSCR,
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armv8->debug_base + CPUDBG_DSCR,
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&dscr);
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&dscr);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -276,8 +276,8 @@ static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
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}
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}
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}
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}
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retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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a8->armv8_common.debug_base + CPUDBG_DTRTX,
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armv8->debug_base + CPUDBG_DTRTX,
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data);
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data);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -288,7 +288,8 @@ static int aarch64_read_dcc(struct aarch64_common *a8, uint32_t *data,
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return retval;
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return retval;
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}
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}
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static int aarch64_read_dcc_64(struct aarch64_common *a8, uint64_t *data,
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static int aarch64_read_dcc_64(struct armv8_common *armv8, uint64_t *data,
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uint32_t *dscr_p)
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uint32_t *dscr_p)
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{
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{
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uint32_t dscr = DSCR_INSTR_COMP;
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uint32_t dscr = DSCR_INSTR_COMP;
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@ -301,8 +302,8 @@ static int aarch64_read_dcc_64(struct aarch64_common *a8, uint64_t *data,
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/* Wait for DTRRXfull */
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/* Wait for DTRRXfull */
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long long then = timeval_ms();
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long long then = timeval_ms();
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while ((dscr & DSCR_DTR_TX_FULL) == 0) {
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while ((dscr & DSCR_DTR_TX_FULL) == 0) {
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retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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a8->armv8_common.debug_base + CPUDBG_DSCR,
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armv8->debug_base + CPUDBG_DSCR,
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&dscr);
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&dscr);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -312,14 +313,14 @@ static int aarch64_read_dcc_64(struct aarch64_common *a8, uint64_t *data,
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}
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}
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}
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}
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retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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a8->armv8_common.debug_base + CPUDBG_DTRTX,
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armv8->debug_base + CPUDBG_DTRTX,
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(uint32_t *)data);
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(uint32_t *)data);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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retval = mem_ap_read_atomic_u32(a8->armv8_common.debug_ap,
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retval = mem_ap_read_atomic_u32(armv8->debug_ap,
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a8->armv8_common.debug_base + CPUDBG_DTRRX,
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armv8->debug_base + CPUDBG_DTRRX,
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&higher);
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&higher);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -395,7 +396,7 @@ static int aarch64_instr_write_data_dcc(struct arm_dpm *dpm,
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int retval;
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int retval;
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uint32_t dscr = DSCR_INSTR_COMP;
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uint32_t dscr = DSCR_INSTR_COMP;
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retval = aarch64_write_dcc(a8, data);
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retval = aarch64_write_dcc(&a8->armv8_common, data);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -412,7 +413,7 @@ static int aarch64_instr_write_data_dcc_64(struct arm_dpm *dpm,
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int retval;
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int retval;
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uint32_t dscr = DSCR_INSTR_COMP;
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uint32_t dscr = DSCR_INSTR_COMP;
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retval = aarch64_write_dcc_64(a8, data);
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retval = aarch64_write_dcc_64(&a8->armv8_common, data);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -429,7 +430,7 @@ static int aarch64_instr_write_data_r0(struct arm_dpm *dpm,
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uint32_t dscr = DSCR_INSTR_COMP;
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uint32_t dscr = DSCR_INSTR_COMP;
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int retval;
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int retval;
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retval = aarch64_write_dcc(a8, data);
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retval = aarch64_write_dcc(&a8->armv8_common, data);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -456,7 +457,7 @@ static int aarch64_instr_write_data_r0_64(struct arm_dpm *dpm,
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uint32_t dscr = DSCR_INSTR_COMP;
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uint32_t dscr = DSCR_INSTR_COMP;
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int retval;
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int retval;
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retval = aarch64_write_dcc_64(a8, data);
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retval = aarch64_write_dcc_64(&a8->armv8_common, data);
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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@ -502,7 +503,7 @@ static int aarch64_instr_read_data_dcc(struct arm_dpm *dpm,
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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return aarch64_read_dcc(a8, data, &dscr);
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return aarch64_read_dcc(&a8->armv8_common, data, &dscr);
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}
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}
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static int aarch64_instr_read_data_dcc_64(struct arm_dpm *dpm,
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static int aarch64_instr_read_data_dcc_64(struct arm_dpm *dpm,
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@ -520,7 +521,7 @@ static int aarch64_instr_read_data_dcc_64(struct arm_dpm *dpm,
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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return aarch64_read_dcc_64(a8, data, &dscr);
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return aarch64_read_dcc_64(&a8->armv8_common, data, &dscr);
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}
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}
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static int aarch64_instr_read_data_r0(struct arm_dpm *dpm,
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static int aarch64_instr_read_data_r0(struct arm_dpm *dpm,
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@ -546,7 +547,7 @@ static int aarch64_instr_read_data_r0(struct arm_dpm *dpm,
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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return aarch64_read_dcc(a8, data, &dscr);
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return aarch64_read_dcc(&a8->armv8_common, data, &dscr);
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}
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}
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static int aarch64_instr_read_data_r0_64(struct arm_dpm *dpm,
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static int aarch64_instr_read_data_r0_64(struct arm_dpm *dpm,
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@ -572,7 +573,7 @@ static int aarch64_instr_read_data_r0_64(struct arm_dpm *dpm,
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if (retval != ERROR_OK)
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if (retval != ERROR_OK)
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return retval;
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return retval;
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return aarch64_read_dcc_64(a8, data, &dscr);
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return aarch64_read_dcc_64(&a8->armv8_common, data, &dscr);
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}
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}
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static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
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static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
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