diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c
index f41f7b51e..7fd7f3894 100644
--- a/src/jtag/drivers/bcm2835gpio.c
+++ b/src/jtag/drivers/bcm2835gpio.c
@@ -331,7 +331,7 @@ COMMAND_HANDLER(bcm2835gpio_handle_peripheral_base)
 	}
 
 	tmp_base = bcm2835_peri_base;
-	command_print(CMD, "BCM2835 GPIO: peripheral_base = 0x%08" PRIu64,
+	command_print(CMD, "BCM2835 GPIO: peripheral_base = 0x%08" PRIx64,
 				  tmp_base);
 	return ERROR_OK;
 }
diff --git a/src/target/arc.c b/src/target/arc.c
index 2ca6be16d..45005b29b 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -1573,9 +1573,6 @@ static int arc_set_breakpoint(struct target *target,
 		return ERROR_FAIL;
 	}
 
-	/* core instruction cache is now invalid. */
-	CHECK_RETVAL(arc_cache_invalidate(target));
-
 	return ERROR_OK;
 }
 
@@ -1658,9 +1655,6 @@ static int arc_unset_breakpoint(struct target *target,
 			return ERROR_FAIL;
 	}
 
-	/* core instruction cache is now invalid. */
-	CHECK_RETVAL(arc_cache_invalidate(target));
-
 	return retval;
 }
 
diff --git a/src/target/arm.h b/src/target/arm.h
index 28e533019..d5053afb8 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -61,6 +61,7 @@ enum arm_arch {
 /** Known ARM implementor IDs */
 enum arm_implementor {
 	ARM_IMPLEMENTOR_ARM = 0x41,
+	ARM_IMPLEMENTOR_INFINEON = 0x49,
 	ARM_IMPLEMENTOR_REALTEK = 0x72,
 };
 
@@ -230,12 +231,22 @@ struct arm {
 			uint32_t crn, uint32_t crm,
 			uint32_t *value);
 
+	/** Read coprocessor to two registers. */
+	int (*mrrc)(struct target *target, int cpnum,
+			uint32_t op, uint32_t crm,
+			uint64_t *value);
+
 	/** Write coprocessor register.  */
 	int (*mcr)(struct target *target, int cpnum,
 			uint32_t op1, uint32_t op2,
 			uint32_t crn, uint32_t crm,
 			uint32_t value);
 
+	/** Write coprocessor from two registers. */
+	int (*mcrr)(struct target *target, int cpnum,
+			uint32_t op, uint32_t crm,
+			uint64_t value);
+
 	void *arch_info;
 
 	/** For targets conforming to ARM Debug Interface v5,
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index ab9b50e23..9f3a444af 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -63,6 +63,29 @@ static int dpm_mrc(struct target *target, int cpnum,
 	return retval;
 }
 
+static int dpm_mrrc(struct target *target, int cpnum,
+	uint32_t op, uint32_t crm, uint64_t *value)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm_dpm *dpm = arm->dpm;
+	int retval;
+
+	retval = dpm->prepare(dpm);
+	if (retval != ERROR_OK)
+		return retval;
+
+	LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
+		 (int)op, (int)crm);
+
+	/* read coprocessor register into R0, R1; return via DCC */
+	retval = dpm->instr_read_data_r0_r1(dpm,
+			ARMV5_T_MRRC(cpnum, op, 0, 1, crm),
+			value);
+
+	/* (void) */ dpm->finish(dpm);
+	return retval;
+}
+
 static int dpm_mcr(struct target *target, int cpnum,
 	uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
 	uint32_t value)
@@ -88,6 +111,29 @@ static int dpm_mcr(struct target *target, int cpnum,
 	return retval;
 }
 
+static int dpm_mcrr(struct target *target, int cpnum,
+	uint32_t op, uint32_t crm, uint64_t value)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm_dpm *dpm = arm->dpm;
+	int retval;
+
+	retval = dpm->prepare(dpm);
+	if (retval != ERROR_OK)
+		return retval;
+
+	LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
+		(int)op, (int)crm);
+
+	/* read DCC into r0, r1; then write coprocessor register from R0, R1 */
+	retval = dpm->instr_write_data_r0_r1(dpm,
+			ARMV5_T_MCRR(cpnum, op, 0, 1, crm), value);
+
+	/* (void) */ dpm->finish(dpm);
+
+	return retval;
+}
+
 /*----------------------------------------------------------------------*/
 
 /*
@@ -1070,6 +1116,8 @@ int arm_dpm_setup(struct arm_dpm *dpm)
 	/* coprocessor access setup */
 	arm->mrc = dpm_mrc;
 	arm->mcr = dpm_mcr;
+	arm->mrrc = dpm_mrrc;
+	arm->mcrr = dpm_mcrr;
 
 	/* breakpoint setup -- optional until it works everywhere */
 	if (!target->type->add_breakpoint) {
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index d35e9f68d..2da463111 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -72,6 +72,12 @@ struct arm_dpm {
 	int (*instr_write_data_r0)(struct arm_dpm *dpm,
 			uint32_t opcode, uint32_t data);
 
+	/**
+	 * Runs two instructions, writing data to R0 and R1 before execution.
+	 */
+	int (*instr_write_data_r0_r1)(struct arm_dpm *dpm,
+			uint32_t opcode, uint64_t data);
+
 	/** Runs one instruction, writing data to R0 before execution. */
 	int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
 			uint32_t opcode, uint64_t data);
@@ -92,6 +98,13 @@ struct arm_dpm {
 	int (*instr_read_data_r0)(struct arm_dpm *dpm,
 			uint32_t opcode, uint32_t *data);
 
+	/**
+	 * Runs two instructions, reading data from r0 and r1 after
+	 * execution.
+	 */
+	int (*instr_read_data_r0_r1)(struct arm_dpm *dpm,
+			uint32_t opcode, uint64_t *data);
+
 	int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
 			uint32_t opcode, uint64_t *data);
 
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index c182f41c4..c8ce51f29 100644
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -187,6 +187,17 @@
 	(0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
 	| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
 
+/* Move to two ARM registers from coprocessor
+ * cp: Coprocessor number
+ * op: Coprocessor opcode
+ * rt: destination register 1
+ * rt2: destination register 2
+ * crm: coprocessor source register
+ */
+#define ARMV5_T_MRRC(cp, op, rt, rt2, crm) \
+	(0xec500000 | (crm) | ((op) << 4) | ((cp) << 8) \
+	| ((rt) << 12) | ((rt2) << 16))
+
 /* Move to coprocessor from ARM register
  * cp: Coprocessor number
  * op1: Coprocessor opcode
@@ -199,6 +210,17 @@
 	(0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
 	| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
 
+/* Move to coprocessor from two ARM registers
+ * cp: Coprocessor number
+ * op: Coprocessor opcode
+ * rt: destination register 1
+ * rt2: destination register 2
+ * crm: coprocessor source register
+ */
+#define ARMV5_T_MCRR(cp, op, rt, rt2, crm) \
+	(0xec400000 | (crm) | ((op) << 4) | ((cp) << 8) \
+	 | ((rt) << 12) | ((rt2) << 16))
+
 /* Breakpoint instruction (ARMv5)
  * im: 16-bit immediate
  */
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 8e3f22417..7debb9498 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1093,6 +1093,94 @@ COMMAND_HANDLER(handle_armv4_5_mcrmrc)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(handle_armv4_5_mcrrmrrc)
+{
+	bool is_mcrr = false;
+	unsigned int arg_cnt = 3;
+
+	if (!strcmp(CMD_NAME, "mcrr")) {
+		is_mcrr = true;
+		arg_cnt = 4;
+	}
+
+	if (arg_cnt != CMD_ARGC)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct target *target = get_current_target(CMD_CTX);
+	if (!target) {
+		command_print(CMD, "no current target");
+		return ERROR_FAIL;
+	}
+	if (!target_was_examined(target)) {
+		command_print(CMD, "%s: not yet examined", target_name(target));
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
+	struct arm *arm = target_to_arm(target);
+	if (!is_arm(arm)) {
+		command_print(CMD, "%s: not an ARM", target_name(target));
+		return ERROR_FAIL;
+	}
+
+	if (target->state != TARGET_HALTED)
+		return ERROR_TARGET_NOT_HALTED;
+
+	int cpnum;
+	uint32_t op1;
+	uint32_t crm;
+	uint64_t value;
+
+	/* NOTE:  parameter sequence matches ARM instruction set usage:
+	 *	MCRR	pNUM, op1, rX1, rX2, CRm	; write CP from rX1 and rX2
+	 *	MREC	pNUM, op1, rX1, rX2, CRm	; read CP into rX1 and rX2
+	 * The "rXn" are necessarily omitted; they use Tcl mechanisms.
+	 */
+	COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
+	if (cpnum & ~0xf) {
+		command_print(CMD, "coprocessor %d out of range", cpnum);
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
+	if (op1 & ~0xf) {
+		command_print(CMD, "op1 %d out of range", op1);
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crm);
+	if (crm & ~0xf) {
+		command_print(CMD, "CRm %d out of range", crm);
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	/*
+	 * FIXME change the call syntax here ... simplest to just pass
+	 * the MRC() or MCR() instruction to be executed.  That will also
+	 * let us support the "mrrc2" and "mcrr2" opcodes (toggling one bit)
+	 * if that's ever needed.
+	 */
+	if (is_mcrr) {
+		COMMAND_PARSE_NUMBER(u64, CMD_ARGV[3], value);
+
+		/* NOTE: parameters reordered! */
+		/* ARMV5_T_MCRR(cpnum, op1, crm) */
+		int retval = arm->mcrr(target, cpnum, op1, crm, value);
+		if (retval != ERROR_OK)
+			return retval;
+	} else {
+		value = 0;
+		/* NOTE: parameters reordered! */
+		/* ARMV5_T_MRRC(cpnum, op1, crm) */
+		int retval = arm->mrrc(target, cpnum, op1, crm, &value);
+		if (retval != ERROR_OK)
+			return retval;
+
+		command_print(CMD, "0x%" PRIx64, value);
+	}
+
+	return ERROR_OK;
+}
+
 static const struct command_registration arm_exec_command_handlers[] = {
 	{
 		.name = "reg",
@@ -1115,6 +1203,20 @@ static const struct command_registration arm_exec_command_handlers[] = {
 		.help = "read coprocessor register",
 		.usage = "cpnum op1 CRn CRm op2",
 	},
+	{
+		.name = "mcrr",
+		.mode = COMMAND_EXEC,
+		.handler = handle_armv4_5_mcrrmrrc,
+		.help = "write coprocessor 64-bit register",
+		.usage = "cpnum op1 CRm value",
+	},
+	{
+		.name = "mrrc",
+		.mode = COMMAND_EXEC,
+		.handler = handle_armv4_5_mcrrmrrc,
+		.help = "read coprocessor 64-bit register",
+		.usage = "cpnum op1 CRm",
+	},
 	{
 		.chain = arm_all_profiles_command_handlers,
 	},
@@ -1669,6 +1771,14 @@ static int arm_default_mrc(struct target *target, int cpnum,
 	return ERROR_FAIL;
 }
 
+static int arm_default_mrrc(struct target *target, int cpnum,
+	uint32_t op, uint32_t crm,
+	uint64_t *value)
+{
+	LOG_ERROR("%s doesn't implement MRRC", target_type_name(target));
+	return ERROR_FAIL;
+}
+
 static int arm_default_mcr(struct target *target, int cpnum,
 	uint32_t op1, uint32_t op2,
 	uint32_t crn, uint32_t crm,
@@ -1678,6 +1788,14 @@ static int arm_default_mcr(struct target *target, int cpnum,
 	return ERROR_FAIL;
 }
 
+static int arm_default_mcrr(struct target *target, int cpnum,
+	uint32_t op, uint32_t crm,
+	uint64_t value)
+{
+	LOG_ERROR("%s doesn't implement MCRR", target_type_name(target));
+	return ERROR_FAIL;
+}
+
 int arm_init_arch_info(struct target *target, struct arm *arm)
 {
 	target->arch_info = arm;
@@ -1697,8 +1815,12 @@ int arm_init_arch_info(struct target *target, struct arm *arm)
 
 	if (!arm->mrc)
 		arm->mrc = arm_default_mrc;
+	if (!arm->mrrc)
+		arm->mrrc = arm_default_mrrc;
 	if (!arm->mcr)
 		arm->mcr = arm_default_mcr;
+	if (!arm->mcrr)
+		arm->mcrr = arm_default_mcrr;
 
 	return ERROR_OK;
 }
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 9ba6b5453..552bcfa02 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -725,7 +725,8 @@ static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 }
 
 /**
- * Read basic registers of the current context:  R0 to R15, and CPSR;
+ * Read basic registers of the current context:  R0 to R15, and CPSR in AArch32
+ * state or R0 to R31, PC and CPSR in AArch64 state;
  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
  * In normal operation this is called on entry to halting debug state,
  * possibly after some other operations supporting restore of debug state
@@ -772,9 +773,15 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
 	/* update core mode and state */
 	armv8_set_cpsr(arm, cpsr);
 
-	for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) {
+	/* read the remaining registers that would be required by GDB 'g' packet */
+	for (unsigned int i = ARMV8_R2; i <= ARMV8_PC ; i++) {
 		struct arm_reg *arm_reg;
 
+		/* in AArch32 skip AArch64 registers */
+		/* TODO: this should be detected below through arm_reg->mode */
+		if (arm->core_state != ARM_STATE_AARCH64 && i > ARMV8_R14 && i < ARMV8_PC)
+			continue;
+
 		r = armv8_reg_current(arm, i);
 		if (!r->exist || r->valid)
 			continue;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index abfd6ac5f..ba3349d09 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -471,6 +471,28 @@ static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
 	return retval;
 }
 
+static int cortex_a_instr_write_data_r0_r1(struct arm_dpm *dpm,
+	uint32_t opcode, uint64_t data)
+{
+	struct cortex_a_common *a = dpm_to_a(dpm);
+	uint32_t dscr = DSCR_INSTR_COMP;
+	int retval;
+
+	retval = cortex_a_instr_write_data_rt_dcc(dpm, 0, data & 0xffffffffULL);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = cortex_a_instr_write_data_rt_dcc(dpm, 1, data >> 32);
+	if (retval != ERROR_OK)
+		return retval;
+
+	/* then the opcode, taking data from R0, R1 */
+	retval = cortex_a_exec_opcode(a->armv7a_common.arm.target,
+			opcode,
+			&dscr);
+	return retval;
+}
+
 static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
 {
 	struct target *target = dpm->arm->target;
@@ -539,6 +561,29 @@ static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
 	return cortex_a_instr_read_data_rt_dcc(dpm, 0, data);
 }
 
+static int cortex_a_instr_read_data_r0_r1(struct arm_dpm *dpm,
+	uint32_t opcode, uint64_t *data)
+{
+	uint32_t lo, hi;
+	int retval;
+
+	/* the opcode, writing data to RO, R1 */
+	retval = cortex_a_instr_read_data_r0(dpm, opcode, &lo);
+	if (retval != ERROR_OK)
+		return retval;
+
+	*data = lo;
+
+	/* write R1 to DCC */
+	retval = cortex_a_instr_read_data_rt_dcc(dpm, 1, &hi);
+	if (retval != ERROR_OK)
+		return retval;
+
+	*data |= (uint64_t)hi << 32;
+
+	return retval;
+}
+
 static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 	uint32_t addr, uint32_t control)
 {
@@ -612,10 +657,12 @@ static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
 
 	dpm->instr_write_data_dcc = cortex_a_instr_write_data_dcc;
 	dpm->instr_write_data_r0 = cortex_a_instr_write_data_r0;
+	dpm->instr_write_data_r0_r1 = cortex_a_instr_write_data_r0_r1;
 	dpm->instr_cpsr_sync = cortex_a_instr_cpsr_sync;
 
 	dpm->instr_read_data_dcc = cortex_a_instr_read_data_dcc;
 	dpm->instr_read_data_r0 = cortex_a_instr_read_data_r0;
+	dpm->instr_read_data_r0_r1 = cortex_a_instr_read_data_r0_r1;
 
 	dpm->bpwp_enable = cortex_a_bpwp_enable;
 	dpm->bpwp_disable = cortex_a_bpwp_disable;
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 854e8eb58..3eafee0a1 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -111,6 +111,11 @@ static const struct cortex_m_part_info cortex_m_parts[] = {
 		.arch = ARM_ARCH_V8M,
 		.flags = CORTEX_M_F_HAS_FPV5,
 	},
+	{
+		.impl_part = INFINEON_SLX2_PARTNO,
+		.name = "Infineon-SLx2",
+		.arch = ARM_ARCH_V8M,
+	},
 	{
 		.impl_part = REALTEK_M200_PARTNO,
 		.name = "Real-M200 (KM0)",
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 065e4d47b..0bc139911 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -45,19 +45,20 @@
  */
 enum cortex_m_impl_part {
 	CORTEX_M_PARTNO_INVALID,
-	STAR_MC1_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0x132), /* FIXME - confirm implementor! */
-	CORTEX_M0_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC20),
-	CORTEX_M1_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC21),
-	CORTEX_M3_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC23),
-	CORTEX_M4_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC24),
-	CORTEX_M7_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC27),
-	CORTEX_M0P_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC60),
-	CORTEX_M23_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD20),
-	CORTEX_M33_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD21),
-	CORTEX_M35P_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD31),
-	CORTEX_M55_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD22),
-	REALTEK_M200_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd20),
-	REALTEK_M300_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd22),
+	STAR_MC1_PARTNO      = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0x132), /* FIXME - confirm implementor! */
+	CORTEX_M0_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC20),
+	CORTEX_M1_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC21),
+	CORTEX_M3_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC23),
+	CORTEX_M4_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC24),
+	CORTEX_M7_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC27),
+	CORTEX_M0P_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC60),
+	CORTEX_M23_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD20),
+	CORTEX_M33_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD21),
+	CORTEX_M35P_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD31),
+	CORTEX_M55_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD22),
+	INFINEON_SLX2_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_INFINEON, 0xDB0),
+	REALTEK_M200_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd20),
+	REALTEK_M300_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd22),
 };
 
 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
diff --git a/src/target/image.c b/src/target/image.c
index ad2d856b5..e998a35f4 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -96,20 +96,22 @@ static int autodetect_image_type(struct image *image, const char *url)
 static int identify_image_type(struct image *image, const char *type_string, const char *url)
 {
 	if (type_string) {
-		if (!strcmp(type_string, "bin"))
+		if (!strcmp(type_string, "bin")) {
 			image->type = IMAGE_BINARY;
-		else if (!strcmp(type_string, "ihex"))
+		} else if (!strcmp(type_string, "ihex")) {
 			image->type = IMAGE_IHEX;
-		else if (!strcmp(type_string, "elf"))
+		} else if (!strcmp(type_string, "elf")) {
 			image->type = IMAGE_ELF;
-		else if (!strcmp(type_string, "mem"))
+		} else if (!strcmp(type_string, "mem")) {
 			image->type = IMAGE_MEMORY;
-		else if (!strcmp(type_string, "s19"))
+		} else if (!strcmp(type_string, "s19")) {
 			image->type = IMAGE_SRECORD;
-		else if (!strcmp(type_string, "build"))
+		} else if (!strcmp(type_string, "build")) {
 			image->type = IMAGE_BUILDER;
-		else
+		} else {
+			LOG_ERROR("Unknown image type: %s, use one of: bin, ihex, elf, mem, s19, build", type_string);
 			return ERROR_IMAGE_TYPE_UNKNOWN;
+		}
 	} else
 		return autodetect_image_type(image, url);
 
diff --git a/src/target/target.c b/src/target/target.c
index 167b1ea5d..84ad8ee3b 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3117,7 +3117,7 @@ COMMAND_HANDLER(handle_reg_command)
 		if (!reg) {
 			command_print(CMD, "%i is out of bounds, the current target "
 					"has only %i registers (0 - %i)", num, count, count - 1);
-			return ERROR_OK;
+			return ERROR_FAIL;
 		}
 	} else {
 		/* access a single register by its name */
@@ -3176,7 +3176,7 @@ COMMAND_HANDLER(handle_reg_command)
 
 not_found:
 	command_print(CMD, "register %s not found in current target", CMD_ARGV[0]);
-	return ERROR_OK;
+	return ERROR_FAIL;
 }
 
 COMMAND_HANDLER(handle_poll_command)
diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index 2539be049..0c82c5758 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -5,6 +5,7 @@
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
@@ -116,3 +117,51 @@ proc nrf52_recover {} {
 }
 
 add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
+	targets $_targetname
+
+	# Read FICR.INFO.PART
+	set PART [mrw 0x10000100]
+
+	switch $PART {
+		0x52840 -
+		0x52833 -
+		0x52832 {
+			if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+				if { [$_chipname.tpiu cget -port-width] != 4 } {
+					echo "Error. Device only supports 4-bit sync traces."
+					return
+				}
+
+				# Set TRACECONFIG.TRACEMUX to enable synchronous trace
+				mmw 0x4000055C 0x00020000 0x00010000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00020000 0x00010000
+				}
+			} else {
+				# Set TRACECONFIG.TRACEMUX to enable SWO
+				mmw 0x4000055C 0x00010000 0x00020000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00010000 0x00020000
+				}
+			}
+		}
+		0x52820 -
+		0x52811 -
+		0x52810 -
+		0x52805 {
+			echo "Error: Device does not support TPIU"
+			return
+		}
+		default {
+			echo "Error: Unknown device"
+			return
+		}
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME"
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 01e11c69f..1cd85eec3 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -248,6 +248,13 @@ switch $_soc {
 	}
 }
 
+proc _get_rtos_type_for_cpu { target_name } {
+	if { [info exists ::RTOS($target_name)] } {
+		return $::RTOS($target_name)
+	}
+	return none
+}
+
 set _CHIPNAME $_soc
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
@@ -260,7 +267,10 @@ set _CTINAME $_CHIPNAME.cti
 
 # sysctrl is always present
 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
+
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \
+	-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
+
 $_TARGETNAME.sysctrl configure -event reset-assert { }
 
 proc sysctrl_up {} {
@@ -303,8 +313,9 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
 	cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
 		-baseaddr [lindex $ARMV8_CTIBASE $_core]
 
-	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
-		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
+	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
+		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
 
 	set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
 
@@ -340,7 +351,7 @@ if { $_v8_smp_debug == 0 } {
 		_armv8_smp_up
 	}
 	# Declare SMP
-	target smp $:::_v8_smp_targets
+	target smp {*}$_v8_smp_targets
 }
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
@@ -350,7 +361,8 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
 
 	# inactive core examination will fail - wait till startup of additional core
 	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
+		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
 
 	$_TARGETNAME.$_r5_name configure -event gdb-attach {
 		_cpu_no_smp_up
@@ -368,7 +380,8 @@ proc r5_up { args } {
 
 if { $_gp_mcu_cores != 0 } {
 	cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
-	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
 	$_TARGETNAME.gp_mcu configure -event reset-assert { }
 
 	proc gp_mcu_up {} {
@@ -404,4 +417,7 @@ if { 0 == [string compare [adapter name] dmem ] } {
 	} else {
 		puts "ERROR: ${SOC} data is missing to support dmem access!"
 	}
+} else {
+	# AXI AP access port for SoC address map
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2
 }