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riscv-openocd
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whitespace fixes 

git-svn-id: svn://svn.berlios.de/openocd/trunk@1682 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2009-05-08 20:44:52 +00:00
parent de8430d3c3
commit d7f71e7fe9
2 changed files with 13 additions and 52 deletions
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51
src/target/etb.c
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@ -58,6 +58,7 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm
static int etb_set_instr(etb_t *etb, u32 new_instr)
{
jtag_tap_t *tap;
tap = etb->tap;
if (tap==NULL)
return ERROR_FAIL;
@ -73,10 +74,6 @@ static int etb_set_instr(etb_t *etb, u32 new_instr)
field.in_value = NULL;
jtag_add_ir_scan(1, &field, TAP_INVALID);
free(field.out_value);
@ -98,10 +95,6 @@ static int etb_scann(etb_t *etb, u32 new_scan_chain)
field.in_value = NULL;
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
jtag_add_dr_scan(1, &field, TAP_INVALID);
@ -159,6 +152,7 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
static int etb_get_reg(reg_t *reg)
{
int retval;
if ((retval = etb_read_reg(reg)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register read");
@ -189,24 +183,20 @@ static int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
u8 tmp[4];
fields[0].in_value = tmp;
fields[1].tap = etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, 4);
fields[1].in_value = NULL;
fields[2].tap = etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
for (i = 0; i < num_frames; i++)
{
/* ensure nR/W reamins set to read */
@ -246,35 +236,20 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].in_value = NULL;
fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
/* read the identification register in the second run, to make sure we
@ -301,6 +276,7 @@ int etb_read_reg(reg_t *reg)
int etb_set_reg(reg_t *reg, u32 value)
{
int retval;
if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
{
LOG_ERROR("BUG: error scheduling etm register write");
@ -317,6 +293,7 @@ int etb_set_reg(reg_t *reg, u32 value)
int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if ((retval = jtag_execute_queue()) != ERROR_OK)
@ -343,24 +320,14 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
buf_set_u32(fields[0].out_value, 0, 32, value);
fields[0].in_value = NULL;
fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
@ -368,12 +335,6 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, TAP_INVALID);
free(fields[0].out_value);
free(fields[1].out_value);
free(fields[2].out_value);
@ -424,12 +385,12 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm
}
tap = jtag_TapByString( args[1] );
if( tap == NULL ){
if (tap == NULL)
{
command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
return ERROR_FAIL;
}
if (arm7_9->etm_ctx)
{
etb_t *etb = malloc(sizeof(etb_t));