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doc: add missing target types 

missing target types are arm946e, avr32_ap7k, cortex_r4, dsp5680xx,
hla_target, mips_mips64, nds32_v2, nds32_v3, nds32_v3m, quark_d20xx,
quark_x10xx, riscv, stm8 and testee

Change-Id: I38f6ed78ee88c09add4b779cd409ebb1e219304f
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5487
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@casualhacker.net>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Tarek BOCHKATI 2020-03-02 15:28:04 +01:00 committed by Oleksij Rempel
parent 8f221f32bc
commit d6541a811d
1 changed files with 27 additions and 13 deletions
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doc/openocd.texi
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@ -4410,30 +4410,39 @@ Lists all supported target types.
At this writing, the supported CPU types are: At this writing, the supported CPU types are:
@itemize @bullet @itemize @bullet
@item @code{aarch64} -- this is an ARMv8-A core with an MMU @item @code{aarch64} -- this is an ARMv8-A core with an MMU.
@item @code{arm11} -- this is a generation of ARMv6 cores @item @code{arm11} -- this is a generation of ARMv6 cores.
@item @code{arm720t} -- this is an ARMv4 core with an MMU @item @code{arm720t} -- this is an ARMv4 core with an MMU.
@item @code{arm7tdmi} -- this is an ARMv4 core @item @code{arm7tdmi} -- this is an ARMv4 core.
@item @code{arm920t} -- this is an ARMv4 core with an MMU @item @code{arm920t} -- this is an ARMv4 core with an MMU.
@item @code{arm926ejs} -- this is an ARMv5 core with an MMU @item @code{arm926ejs} -- this is an ARMv5 core with an MMU.
@item @code{arm966e} -- this is an ARMv5 core @item @code{arm946e} -- this is an ARMv5 core with an MMU.
@item @code{arm9tdmi} -- this is an ARMv4 core @item @code{arm966e} -- this is an ARMv5 core.
@item @code{arm9tdmi} -- this is an ARMv4 core.
@item @code{avr} -- implements Atmel's 8-bit AVR instruction set. @item @code{avr} -- implements Atmel's 8-bit AVR instruction set.
(Support for this is preliminary and incomplete.) (Support for this is preliminary and incomplete.)
@item @code{cortex_a} -- this is an ARMv7-A core with an MMU @item @code{avr32_ap7k} -- this an AVR32 core.
@item @code{cortex_a} -- this is an ARMv7-A core with an MMU.
@item @code{cortex_m} -- this is an ARMv7-M core, supporting only the @item @code{cortex_m} -- this is an ARMv7-M core, supporting only the
compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
@item @code{dragonite} -- resembles arm966e @item @code{cortex_r4} -- this is an ARMv7-R core.
@item @code{dragonite} -- resembles arm966e.
@item @code{dsp563xx} -- implements Freescale's 24-bit DSP. @item @code{dsp563xx} -- implements Freescale's 24-bit DSP.
(Support for this is still incomplete.) (Support for this is still incomplete.)
@item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
@item @code{esirisc} -- this is an EnSilica eSi-RISC core. @item @code{esirisc} -- this is an EnSilica eSi-RISC core.
The current implementation supports eSi-32xx cores. The current implementation supports eSi-32xx cores.
@item @code{fa526} -- resembles arm920 (w/o Thumb) @item @code{fa526} -- resembles arm920 (w/o Thumb).
@item @code{feroceon} -- resembles arm926 @item @code{feroceon} -- resembles arm926.
@item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.
@item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs, @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs,
allowing access to physical memory addresses independently of CPU cores. allowing access to physical memory addresses independently of CPU cores.
@item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs. @item @code{mem_ap} -- this is an ARM debug infrastructure Access Port without a CPU, through which bus read and write cycles can be generated; it may be useful for working with non-CPU hardware behind an AP or during development of support for new CPUs.
@item @code{mips_m4k} -- a MIPS core @item @code{mips_m4k} -- a MIPS core.
@item @code{mips_mips64} -- a MIPS64 core.
@item @code{nds32_v2} -- this is an Andes NDS32 v2 core.
@item @code{nds32_v3} -- this is an Andes NDS32 v3 core.
@item @code{nds32_v3m} -- this is an Andes NDS32 v3m core.
@item @code{or1k} -- this is an OpenRISC 1000 core. @item @code{or1k} -- this is an OpenRISC 1000 core.
The current implementation supports three JTAG TAP cores: The current implementation supports three JTAG TAP cores:
@itemize @minus @itemize @minus
@ -4446,6 +4455,11 @@ And two debug interfaces cores:
@item @code{Advanced debug interface} (See: @url{http://opencores.org/project@comma{}adv_debug_sys}) @item @code{Advanced debug interface} (See: @url{http://opencores.org/project@comma{}adv_debug_sys})
@item @code{SoC Debug Interface} (See: @url{http://opencores.org/project@comma{}dbg_interface}) @item @code{SoC Debug Interface} (See: @url{http://opencores.org/project@comma{}dbg_interface})
@end itemize @end itemize
@item @code{quark_d20xx} -- an Intel Quark D20xx core.
@item @code{quark_x10xx} -- an Intel Quark X10xx core.
@item @code{riscv} -- a RISC-V core.
@item @code{stm8} -- implements an STM8 core.
@item @code{testee} -- a dummy target for cases without a real CPU, e.g. CPLD.
@item @code{xscale} -- this is actually an architecture, @item @code{xscale} -- this is actually an architecture,
not a CPU type. It is based on the ARMv5 architecture. not a CPU type. It is based on the ARMv5 architecture.
@end itemize @end itemize