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cortex_a8/a9: fix some comments 

Signed-off-by: Luca Ellero <lroluk@gmail.com>
This commit is contained in:
Luca Ellero 2011-02-08 05:16:54 +00:00 committed by Øyvind Harboe
parent 706284a8fd
commit d51b561b10
2 changed files with 8 additions and 8 deletions
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8
src/target/cortex_a8.c
View File

@ -299,7 +299,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
if (dscr & DSCR_DTR_RX_FULL) if (dscr & DSCR_DTR_RX_FULL)
{ {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr); &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
@ -318,7 +318,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
if (Rd < 15) if (Rd < 15)
{ {
/* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */ /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr); &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
@ -326,7 +326,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
} }
else if (Rd == 15) else if (Rd == 15)
{ {
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "mov r15, r0" * then "mov r15, r0"
*/ */
retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
@ -339,7 +339,7 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
} }
else else
{ {
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
*/ */
retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), retval = cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),

8
src/target/cortex_a9.c
View File

@ -299,7 +299,7 @@ static int cortex_a9_dap_write_coreregister_u32(struct target *target,
if (dscr & DSCR_DTR_RX_FULL) if (dscr & DSCR_DTR_RX_FULL)
{ {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ /* Clear DCCRX with MRC(p14, 0, Rd, c0, c5, 0), opcode 0xEE100E15 */
retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
&dscr); &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
@ -318,7 +318,7 @@ static int cortex_a9_dap_write_coreregister_u32(struct target *target,
if (Rd < 15) if (Rd < 15)
{ {
/* DCCRX to Rn, "MCR p14, 0, Rn, c0, c5, 0", 0xEE00nE15 */ /* DCCRX to Rn, "MRC p14, 0, Rn, c0, c5, 0", 0xEE10nE15 */
retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0), retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0),
&dscr); &dscr);
if (retval != ERROR_OK) if (retval != ERROR_OK)
@ -326,7 +326,7 @@ static int cortex_a9_dap_write_coreregister_u32(struct target *target,
} }
else if (Rd == 15) else if (Rd == 15)
{ {
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "mov r15, r0" * then "mov r15, r0"
*/ */
retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
@ -339,7 +339,7 @@ static int cortex_a9_dap_write_coreregister_u32(struct target *target,
} }
else else
{ {
/* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 /* DCCRX to R0, "MRC p14, 0, R0, c0, c5, 0", 0xEE100E15
* then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields) * then "MSR CPSR_cxsf, r0" or "MSR SPSR_cxsf, r0" (all fields)
*/ */
retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0), retval = cortex_a9_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0),