From d471fff3dbeeaf2db80d39fb754e6071b6b3e03e Mon Sep 17 00:00:00 2001 From: Ryan Macdonald Date: Thu, 5 Apr 2018 17:57:53 -0700 Subject: [PATCH] Fixed build issues --- src/target/riscv/riscv-013.c | 49 ++++++++++++++++++------------------ src/target/riscv/riscv.c | 12 ++++++--- src/target/riscv/riscv.h | 3 ++- 3 files changed, 35 insertions(+), 29 deletions(-) diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 389d2d711..988b69111 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -57,7 +57,8 @@ static void riscv013_fill_dmi_write_u64(struct target *target, char *buf, int a, static void riscv013_fill_dmi_read_u64(struct target *target, char *buf, int a); static int riscv013_dmi_write_u64_bits(struct target *target); static void riscv013_fill_dmi_nop_u64(struct target *target, char *buf); -static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address); +static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, + target_addr_t illegal_address); uint32_t read_memory_sba_simple(struct target *target, uint32_t addr, uint32_t sbcs); void write_memory_sba_simple(struct target *target, uint32_t addr, uint32_t data, uint32_t sbcs); static int register_read_direct(struct target *target, uint64_t *value, uint32_t number); @@ -2840,13 +2841,13 @@ static int get_max_sbaccess(struct target *target) return ERROR_FAIL; } -static int riscv013_test_sba_config_reg(struct target *target, target_addr_t illegal_address) +static int riscv013_test_sba_config_reg(struct target *target, target_addr_t legal_address, target_addr_t illegal_address) { LOG_INFO("Testing System Bus Access as defined by RISC-V Debug Spec v0.13"); uint32_t rd_val; uint32_t sbcs_orig; - dmi_read(target, &sbcs_orig, DMI_SBCS) + dmi_read(target, &sbcs_orig, DMI_SBCS); uint32_t sbcs = sbcs_orig; bool test_passed; @@ -2873,12 +2874,12 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill dmi_write(target, DMI_SBCS, sbcs); for (int i = 0; i < 100; i++) { - uint32_t addr = 0x80000000 + (i << sbaccess); + uint32_t addr = legal_address + (i << sbaccess); write_memory_sba_simple(target, addr, i, sbcs); } for (uint32_t i = 0; i < 100; i++) { - uint32_t addr = 0x80000000 + (i << sbaccess); + uint32_t addr = legal_address + (i << sbaccess); uint32_t val = read_memory_sba_simple(target, addr, sbcs); if (i != val) { LOG_ERROR("System Bus Access Test 1: Error reading non-autoincremented address %x, expected val = %d, read val = %d", addr, i, val); @@ -2898,7 +2899,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill sbcs = set_field(sbcs, DMI_SBCS_SBACCESS, sbaccess); dmi_write(target, DMI_SBCS, sbcs); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, legal_address); for (int i = 0; i < 100; i++) { read_sbcs_nonbusy(target, &sbcs); dmi_write(target, DMI_SBDATA0, i); @@ -2906,7 +2907,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill read_sbcs_nonbusy(target, &sbcs); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, legal_address); uint32_t val; sbcs = set_field(sbcs, DMI_SBCS_SBREADONDATA, 1); @@ -2958,7 +2959,7 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill sbcs = set_field(sbcs_orig, DMI_SBCS_SBACCESS, 4); dmi_write(target, DMI_SBCS, sbcs); - write_memory_sba_simple(target, 0x80000000, 0xdeadbeef, sbcs_orig); + write_memory_sba_simple(target, legal_address, 0xdeadbeef, sbcs_orig); dmi_read(target, &rd_val, DMI_SBCS); @@ -2992,22 +2993,22 @@ static int riscv013_test_sba_config_reg(struct target *target, target_addr_t ill dmi_write(target, DMI_SBDATA0, 0xdeadbeef); dmi_write(target, DMI_SBDATA0, 0xdeadbeef); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); - dmi_write(target, DMI_SBADDRESS0, 0x80000000); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); + dmi_write(target, DMI_SBADDRESS0, legal_address); dmi_read(target, &rd_val, DMI_SBCS); if (get_field(rd_val, DMI_SBCS_SBBUSYERROR)) { diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index a94640eee..9aed49cca 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1438,11 +1438,13 @@ COMMAND_HANDLER(riscv_test_sba_config_reg) struct target *target = get_current_target(CMD_CTX); RISCV_INFO(r); + uint32_t legal_address; uint32_t illegal_address; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], illegal_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], legal_address); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], illegal_address); if (r->test_sba_config_reg) { - return r->test_sba_config_reg(target, illegal_address); + return r->test_sba_config_reg(target, legal_address, illegal_address); } else { LOG_ERROR("test_sba_config_reg is not implemented for this target."); return ERROR_FAIL; @@ -1520,8 +1522,10 @@ static const struct command_registration riscv_exec_command_handlers[] = { .name = "test_sba_config_reg", .handler = riscv_test_sba_config_reg, .mode = COMMAND_ANY, - .usage = "riscv test_sba_config_reg illegal_address", - .help = "Perform a series of tests on the SBCS register. Input arg is a non-readable/writable address." + .usage = "riscv test_sba_config_reg legal_address illegal_address", + .help = "Perform a series of tests on the SBCS register." + "Inputs are a legal address for read/write tests," + "and an illegal address to for error flag/handling cases." }, COMMAND_REGISTRATION_DONE }; diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h index 18f47b7a8..ec0a21c38 100644 --- a/src/target/riscv/riscv.h +++ b/src/target/riscv/riscv.h @@ -117,7 +117,8 @@ typedef struct { int (*dmi_read)(struct target *target, uint32_t *value, uint32_t address); int (*dmi_write)(struct target *target, uint32_t address, uint32_t value); - int (*test_sba_config_reg)(struct target *target, target_addr_t illegal_address); + int (*test_sba_config_reg)(struct target *target, target_addr_t legal_address, + target_addr_t illegal_address); } riscv_info_t;