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pld/virtex2: small doc extension 

Change-Id: I174cd702388be04268b38178fbfacb90db452f72
Signed-off-by: Daniel Anselmi <danselmi@gmx.ch>
Reviewed-on: https://review.openocd.org/c/openocd/+/7303
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
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Daniel Anselmi 2022-11-02 17:21:18 +01:00 committed by Antonio Borneo
parent fb23c9c10b
commit d3e79c1eaf
1 changed files with 8 additions and 0 deletions
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doc/openocd.texi
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@ -8478,12 +8478,20 @@ that particular type of PLD.
@deffn {FPGA Driver} {virtex2} [no_jstart] @deffn {FPGA Driver} {virtex2} [no_jstart]
Virtex-II is a family of FPGAs sold by Xilinx. Virtex-II is a family of FPGAs sold by Xilinx.
This driver can also be used to load Series3, Series6, Series7 and Zynq 7000 devices.
It supports the IEEE 1532 standard for In-System Configuration (ISC). It supports the IEEE 1532 standard for In-System Configuration (ISC).
If @var{no_jstart} is non-zero, the JSTART instruction is not used after If @var{no_jstart} is non-zero, the JSTART instruction is not used after
loading the bitstream. While required for Series2, Series3, and Series6, it loading the bitstream. While required for Series2, Series3, and Series6, it
breaks bitstream loading on Series7. breaks bitstream loading on Series7.
@example
openocd -f board/digilent_zedboard.cfg -c "init" \
-c "pld load 0 zedboard_bitstream.bit"
@end example
@deffn {Command} {virtex2 read_stat} num @deffn {Command} {virtex2 read_stat} num
Reads and displays the Virtex-II status register (STAT) Reads and displays the Virtex-II status register (STAT)
for FPGA @var{num}. for FPGA @var{num}.