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Merge branch 'master' into update 

Change-Id: Icec244b174cc0c67ab58961649a369db7f344824
This commit is contained in:
Tim Newsome 2017-12-22 13:03:58 -08:00
parent 6c719f0ab8 1c2e3d41de
commit d2c92be73f
109 changed files with 5298 additions and 905 deletions
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6
configure.ac
View File

@ -571,7 +571,7 @@ AS_IF([test "x$build_buspirate" = "xyes"], [
AS_IF([test "x$use_internal_jimtcl" = "xyes"], [
AS_IF([test -f "$srcdir/jimtcl/configure.ac"], [
AX_CONFIG_SUBDIR_OPTION([jimtcl], [--disable-install-jim --with-ext="eventloop array clock regexp stdlib tclcompat" --without-ext="default"])
AX_CONFIG_SUBDIR_OPTION([jimtcl], [--disable-install-jim])
], [
AC_MSG_ERROR([jimtcl not found, run git submodule init and git submodule update.])
])
@ -628,7 +628,7 @@ PKG_CHECK_MODULES([LIBFTDI], [libftdi1], [use_libftdi=yes], [
PKG_CHECK_MODULES([LIBFTDI], [libftdi], [use_libftdi=yes], [use_libftdi=no])
])
PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.1],
PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.2],
[use_libjaylink=yes], [use_libjaylink=no])
m4_define([PROCESS_ADAPTERS], [
@ -655,7 +655,7 @@ PROCESS_ADAPTERS([USB0_ADAPTERS], ["x$use_libusb0" = "xyes"], [libusb-0.1])
PROCESS_ADAPTERS([HIDAPI_ADAPTERS], ["x$use_hidapi" = "xyes"], [hidapi])
PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libusb1" = "xyes"], [hidapi and libusb-1.x])
PROCESS_ADAPTERS([LIBFTDI_ADAPTERS], ["x$use_libftdi" = "xyes"], [libftdi])
PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_libusb1" = "xyes" -a "x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libusb-1.x or libjaylink-0.1])
PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.1])
AS_IF([test "x$build_openjtag" = "xyes"], [
AS_IF([test "x$use_libusb1" != "xyes" -a "x$use_libusb0" != "xyes"], [

5
contrib/loaders/Makefile
View File

@ -1,6 +1,6 @@
.PHONY: arm clean-arm
all: arm
all: arm stm8
common_dirs = \
checksum \
@ -32,3 +32,6 @@ clean: clean-arm
for d in $(common_dirs); do \
$(MAKE) -C $$d clean; \
done
stm8:
$(MAKE) -C erase_check stm8

17
contrib/loaders/erase_check/Makefile
View File

@ -6,6 +6,12 @@ ARM_OBJCOPY ?= $(ARM_CROSS_COMPILE)objcopy
ARM_AFLAGS = -EL
STM8_CROSS_COMPILE ?= stm8-
STM8_AS ?= $(STM8_CROSS_COMPILE)as
STM8_OBJCOPY ?= $(STM8_CROSS_COMPILE)objcopy
STM8_AFLAGS =
arm: armv4_5_erase_check.inc armv7m_erase_check.inc armv7m_0_erase_check.inc
armv4_5_%.elf: armv4_5_%.s
@ -26,5 +32,16 @@ armv7m_%.bin: armv7m_%.elf
armv7m_%.inc: armv7m_%.bin
$(BIN2C) < $< > $@
stm8: stm8_erase_check.inc
stm8_%.elf: stm8_%.s
$(STM8_AS) $(STM8_AFLAGS) $< -o $@
stm8_%.bin: stm8_%.elf
$(STM8_OBJCOPY) -Obinary $< $@
stm8_%.inc: stm8_%.bin
$(BIN2C) < $< > $@
clean:
-rm -f *.elf *.bin *.inc

5
contrib/loaders/erase_check/stm8_erase_check.inc Normal file
View File

@ -0,0 +1,5 @@
/* Autogenerated with ../../../src/helper/bin2char.sh */
0x00,0x80,0x00,0x00,0x80,0x00,0x96,0xcf,0x00,0x22,0x1e,0x01,0x16,0x04,0xa6,0xff,
0x90,0x5d,0x26,0x04,0x0d,0x03,0x27,0x17,0x90,0x5d,0x26,0x02,0x0a,0x03,0x90,0x5a,
0x92,0xbc,0x00,0x00,0xa1,0xff,0x26,0x07,0x5c,0x26,0xe5,0x0c,0x00,0x20,0xe1,0x1f,
0x01,0x17,0x04,0x8b,

69
contrib/loaders/erase_check/stm8_erase_check.s Normal file
View File

@ -0,0 +1,69 @@
/*
Copyright (C) 2017 Ake Rehnman
ake.rehnman(at)gmail.com
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
;;
;; erase check memory code
;;
.org 0x0
;; start address
start_addr: .byte 0x00
.word 0x8000
;; byte count
byte_cnt: .byte 0x00
.word 0x8000
;
; SP must point to start_addr on entry
; first relocate start_addr to the location
; we are running at
start:
ldw X,SP
ldw .cont+2,X
ldw X,(start_addr+1,SP) ;start addr
ldw Y,(byte_cnt+1,SP) ;count
ld A,#0xff
;
; if count == 0 return
.L1:
tnzw Y
jrne .decrcnt ;continue if low word != 0
tnz (byte_cnt,SP) ;high byte
jreq .exit ;goto exit
;
; decrement count (byte_cnt)
.decrcnt:
tnzw Y ;low word count
jrne .decr1
dec (byte_cnt,SP) ;high byte
.decr1:
decw Y; decr low word
;
; first check if [start_addr] is 0xff
.cont:
ldf A, [start_addr.e]
cp A,#0xff
jrne .exit ;exit if not 0xff
;
; increment start_addr (addr)
incw X
jrne .L1
inc (start_addr,SP) ;increment high byte
jra .L1
;
.exit:
ldw (start_addr+1,SP),X ;start addr
ldw (byte_cnt+1,SP),Y ;count
break

4
contrib/loaders/flash/efm32.S
View File

@ -44,11 +44,7 @@
#define EFM32_MSC_ADDRB_OFFSET 0x010
#define EFM32_MSC_WDATA_OFFSET 0x018
#define EFM32_MSC_STATUS_OFFSET 0x01c
#define EFM32_MSC_LOCK_OFFSET 0x03c
/* unlock MSC */
ldr r6, =#0x1b71
str r6, [r0, #EFM32_MSC_LOCK_OFFSET]
/* set WREN to 1 */
movs r6, #1
str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET]

121
contrib/loaders/flash/stm32h7x.S Normal file
View File

@ -0,0 +1,121 @@
/***************************************************************************
* Copyright (C) 2017 by STMicroelectronics *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc. *
***************************************************************************/
.text
.syntax unified
.cpu cortex-m7
.thumb
.thumb_func
/*
* To assemble:
* arm-none-eabi-gcc -c stm32h7x.S
*
* To disassemble:
* arm-none-eabi-objdump -d stm32h7x.o
*
* To generate binary file:
* arm-none-eabi-objcopy -O binary stm32h7x.o stm32h7_flash_write_code.bin
*
* To generate include file:
* xxd -i stm32h7_flash_write_code.bin
*/
/*
* Code limitations:
* The workarea must have size multiple of 4 bytes, since R/W
* operations are all at 32 bits.
* The workarea must be big enough to contain 32 bytes of data,
* thus the minimum size is (rp, wp, data) = 4 + 4 + 32 = 40 bytes.
* To benefit from concurrent host write-to-buffer and target
* write-to-flash, the workarea must be way bigger than the minimum.
*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
* r3 = count (256 bit words)
* r4 = flash reg base
*
* Clobbered:
* r5 - rp
* r6 - wp, status, tmp
* r7 - loop index, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x0C /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
#define STM32_CR_PROG 0x00000032 /* PSIZE64 | PG */
#define STM32_SR_BUSY_MASK 0x00000001 /* BSY */
#define STM32_SR_ERROR_MASK 0x03ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
| INCERR | STRBERR | PGSERR | WRPERR */
code:
ldr r5, [r0, #4] /* read rp */
wait_fifo:
ldr r6, [r0, #0] /* read wp */
cbz r6, exit /* abort if wp == 0, status = 0 */
subs r6, r6, r5 /* number of bytes available for read in r6 */
ittt mi /* if wrapped around */
addmi r6, r1 /* add size of buffer */
submi r6, r0
submi r6, #8
cmp r6, #32 /* wait until 32 bytes are available */
bcc wait_fifo
mov r6, #STM32_CR_PROG
str r6, [r4, #STM32_FLASH_CR_OFFSET]
mov r7, #8 /* program by 8 words = 32 bytes */
write_flash:
ldr r6, [r5], #0x04 /* read one word from src, increment ptr */
str r6, [r2], #0x04 /* write one word to dst, increment ptr */
dsb
cmp r5, r1 /* if rp >= end of buffer ... */
it cs
addcs r5, r0, #8 /* ... then wrap at buffer start */
subs r7, r7, #1 /* decrement loop index */
bne write_flash /* loop if not done */
busy:
ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
tst r6, #STM32_SR_BUSY_MASK
bne busy /* operation in progress, wait ... */
ldr r7, stm32_sr_error_mask
tst r6, r7
bne error /* fail... */
str r5, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement count */
bne wait_fifo /* loop if not done */
b exit
error:
movs r7, #0
str r7, [r0, #4] /* set rp = 0 on error */
exit:
mov r0, r6 /* return status in r0 */
bkpt #0x00
stm32_sr_error_mask:
.word STM32_SR_ERROR_MASK

149
doc/openocd.texi
View File

@ -2948,8 +2948,8 @@ Specifies the serial number of the adapter.
Specifies the adapter layout to use.
@end deffn
@deffn {Config Command} {hla_vid_pid} vid pid
The vendor ID and product ID of the device.
@deffn {Config Command} {hla_vid_pid} [vid pid]+
Pairs of vendor IDs and product IDs of the device.
@end deffn
@deffn {Command} {hla_command} command
@ -4503,12 +4503,6 @@ and (if the target is using it) after SRST has been
released on the scan chain.
@item @b{reset-end}
@* Issued as the final step in @command{reset} processing.
@ignore
@item @b{reset-halt-post}
@* Currently not used
@item @b{reset-halt-pre}
@* Currently not used
@end ignore
@item @b{reset-init}
@* Used by @b{reset init} command for board-specific initialization.
This event fires after @emph{reset-deassert-post}.
@ -4525,12 +4519,6 @@ before @command{reset_init} is called.
This is the most robust place to use @command{jtag_rclk}
or @command{adapter_khz} to switch to a low JTAG clock rate,
when reset disables PLLs needed to use a fast clock.
@ignore
@item @b{reset-wait-pos}
@* Currently not used
@item @b{reset-wait-pre}
@* Currently not used
@end ignore
@item @b{resume-start}
@* Before any target is resumed
@item @b{resume-end}
@ -5767,17 +5755,19 @@ Show information about flash driver.
@end deffn
@deffn {Flash Driver} nrf51
@deffn {Flash Driver} nrf5
All members of the nRF51 microcontroller families from Nordic Semiconductor
include internal flash and use ARM Cortex-M0 core.
Also, the nRF52832 microcontroller from Nordic Semiconductor, which include
internal flash and use an ARM Cortex-M4F core.
@example
flash bank $_FLASHNAME nrf51 0 0x00000000 0 0 $_TARGETNAME
flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
@end example
Some nrf51-specific commands are defined:
Some nrf5-specific commands are defined:
@deffn Command {nrf51 mass_erase}
@deffn Command {nrf5 mass_erase}
Erases the contents of the code memory and user information
configuration registers as well. It must be noted that this command
works only for chips that do not have factory pre-programmed region 0
@ -5886,9 +5876,6 @@ All members of the Stellaris LM3Sxxx, LM4x and Tiva C microcontroller
families from Texas Instruments include internal flash. The driver
automatically recognizes a number of these chips using the chip
identification register, and autoconfigures itself.
@footnote{Currently there is a @command{stellaris mass_erase} command.
That seems pointless since the same effect can be had using the
standard @command{flash erase_address} command.}
@example
flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
@ -5934,11 +5921,7 @@ as per the following example.
flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME
@end example
Some stm32f1x-specific commands
@footnote{Currently there is a @command{stm32f1x mass_erase} command.
That seems pointless since the same effect can be had using the
standard @command{flash erase_address} command.}
are defined:
Some stm32f1x-specific commands are defined:
@deffn Command {stm32f1x lock} num
Locks the entire stm32 device.
@ -5950,6 +5933,11 @@ Unlocks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32f1x mass_erase} num
Mass erases the entire stm32f1x device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32f1x options_read} num
Read and display the stm32 option bytes written by
the @command{stm32f1x options_write} command.
@ -5968,6 +5956,10 @@ include internal flash and use ARM Cortex-M3/M4/M7 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
@example
flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
@end example
Note that some devices have been found that have a flash size register that contains
an invalid value, to workaround this issue you can override the probed value used by
the flash driver.
@ -5988,6 +5980,11 @@ Unlocks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32f2x mass_erase} num
Mass erases the entire stm32f2x device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32f2x options_read} num
Reads and displays user options and (where implemented) boot_addr0, boot_addr1, optcr2.
The @var{num} parameter is a value shown by @command{flash banks}.
@ -6007,12 +6004,52 @@ The @var{num} parameter is a value shown by @command{flash banks}, @var{optcr2}
@end deffn
@end deffn
@deffn {Flash Driver} stm32h7x
All members of the STM32H7 microcontroller families from ST Microelectronics
include internal flash and use ARM Cortex-M7 core.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
@example
flash bank $_FLASHNAME stm32h7x 0 0 0 0 $_TARGETNAME
@end example
Note that some devices have been found that have a flash size register that contains
an invalid value, to workaround this issue you can override the probed value used by
the flash driver.
@example
flash bank $_FLASHNAME stm32h7x 0 0x20000 0 0 $_TARGETNAME
@end example
Some stm32h7x-specific commands are defined:
@deffn Command {stm32h7x lock} num
Locks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32h7x unlock} num
Unlocks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32h7x mass_erase} num
Mass erases the entire stm32h7x device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@end deffn
@deffn {Flash Driver} stm32lx
All members of the STM32L microcontroller families from ST Microelectronics
include internal flash and use ARM Cortex-M3 and Cortex-M0+ cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
@example
flash bank $_FLASHNAME stm32lx 0 0 0 0 $_TARGETNAME
@end example
Note that some devices have been found that have a flash size register that contains
an invalid value, to workaround this issue you can override the probed value used by
the flash driver. If you use 0 as the bank base address, it tells the
@ -6025,6 +6062,16 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0x20000 0 0 $_TARGETNAME
Some stm32lx-specific commands are defined:
@deffn Command {stm32lx lock} num
Locks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32lx unlock} num
Unlocks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32lx mass_erase} num
Mass erases the entire stm32lx device (all flash banks and EEPROM
data). This is the only way to unlock a protected flash (unless RDP
@ -6033,6 +6080,42 @@ The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@end deffn
@deffn {Flash Driver} stm32l4x
All members of the STM32L4 microcontroller families from ST Microelectronics
include internal flash and use ARM Cortex-M4 cores.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
@example
flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
@end example
Note that some devices have been found that have a flash size register that contains
an invalid value, to workaround this issue you can override the probed value used by
the flash driver.
@example
flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
@end example
Some stm32l4x-specific commands are defined:
@deffn Command {stm32l4x lock} num
Locks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32l4x unlock} num
Unlocks the entire stm32 device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn Command {stm32l4x mass_erase} num
Mass erases the entire stm32l4x device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@end deffn
@deffn {Flash Driver} str7x
All members of the STR7 microcontroller family from ST Microelectronics
include internal flash and use ARM7TDMI cores.
@ -7602,6 +7685,20 @@ requests by using a special SVC instruction that is trapped at the
Supervisor Call vector by OpenOCD.
@end deffn
@deffn Command {arm semihosting_cmdline} [@option{enable}|@option{disable}]
@cindex ARM semihosting
Set the command line to be passed to the debuggee.
@example
arm semihosting_cmdline argv0 argv1 argv2 ...
@end example
This option lets one set the command line arguments to be passed to
the program. The first argument (argv0) is the program name in a
standard C environment (argv[0]). Depending on the program (not much
programs look at argv[0]), argv0 is ignored and can be any string.
@end deffn
@deffn Command {arm semihosting_fileio} [@option{enable}|@option{disable}]
@cindex ARM semihosting
Display status of semihosting fileio, after optionally changing that

4
src/flash/mflash.c
View File

@ -259,11 +259,11 @@ static int mg_dsk_wait(mg_io_type_wait wait_local, uint32_t time_var)
case mg_io_wait_rdy:
if (status & mg_io_rbit_status_ready)
return ERROR_OK;
/* fallthrough */
case mg_io_wait_drq:
if (status & mg_io_rbit_status_data_req)
return ERROR_OK;
/* fallthrough */
default:
break;
}

1
src/flash/nand/mx3.c
View File

@ -281,6 +281,7 @@ static int imx31_command(struct nand_device *nand, uint8_t command)
* offset == one half of page size
*/
in_sram_address = MX3_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
break;
default:
in_sram_address = MX3_NF_MAIN_BUFFER0;
}

3
src/flash/nor/Makefile.am
View File

@ -37,7 +37,7 @@ NOR_DRIVERS = \
%D%/mrvlqspi.c \
%D%/niietcm4.c \
%D%/non_cfi.c \
%D%/nrf51.c \
%D%/nrf5.c \
%D%/numicro.c \
%D%/ocl.c \
%D%/pic32mx.c \
@ -50,6 +50,7 @@ NOR_DRIVERS = \
%D%/stm32f2x.c \
%D%/stm32lx.c \
%D%/stm32l4x.c \
%D%/stm32h7x.c \
%D%/str7x.c \
%D%/str9x.c \
%D%/str9xpec.c \

4
src/flash/nor/drivers.c
View File

@ -49,6 +49,7 @@ extern struct flash_driver lpcspifi_flash;
extern struct flash_driver mdr_flash;
extern struct flash_driver mrvlqspi_flash;
extern struct flash_driver niietcm4_flash;
extern struct flash_driver nrf5_flash;
extern struct flash_driver nrf51_flash;
extern struct flash_driver numicro_flash;
extern struct flash_driver ocl_flash;
@ -60,6 +61,7 @@ extern struct flash_driver stm32f1x_flash;
extern struct flash_driver stm32f2x_flash;
extern struct flash_driver stm32lx_flash;
extern struct flash_driver stm32l4x_flash;
extern struct flash_driver stm32h7x_flash;
extern struct flash_driver stmsmi_flash;
extern struct flash_driver str7x_flash;
extern struct flash_driver str9x_flash;
@ -103,6 +105,7 @@ static struct flash_driver *flash_drivers[] = {
&mdr_flash,
&mrvlqspi_flash,
&niietcm4_flash,
&nrf5_flash,
&nrf51_flash,
&numicro_flash,
&ocl_flash,
@ -114,6 +117,7 @@ static struct flash_driver *flash_drivers[] = {
&stm32f2x_flash,
&stm32lx_flash,
&stm32l4x_flash,
&stm32h7x_flash,
&stmsmi_flash,
&str7x_flash,
&str9x_flash,

99
src/flash/nor/efm32.c
View File

@ -49,6 +49,8 @@
#define EZR_FAMILY_ID_WONDER_GECKO 120
#define EZR_FAMILY_ID_LEOPARD_GECKO 121
#define EZR_FAMILY_ID_HAPPY_GECKO 122
#define EFR_FAMILY_ID_MIGHTY_GECKO 16
#define EFR_FAMILY_ID_BLUE_GECKO 20
#define EFM32_FLASH_ERASE_TMO 100
#define EFM32_FLASH_WDATAREADY_TMO 100
@ -72,27 +74,31 @@
#define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
#define EFM32_MSC_REGBASE 0x400c0000
#define EFM32_MSC_WRITECTRL (EFM32_MSC_REGBASE+0x008)
#define EFR32_MSC_REGBASE 0x400e0000
#define EFM32_MSC_REG_WRITECTRL 0x008
#define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
#define EFM32_MSC_WRITECMD (EFM32_MSC_REGBASE+0x00c)
#define EFM32_MSC_REG_WRITECMD 0x00c
#define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
#define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
#define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
#define EFM32_MSC_ADDRB (EFM32_MSC_REGBASE+0x010)
#define EFM32_MSC_WDATA (EFM32_MSC_REGBASE+0x018)
#define EFM32_MSC_STATUS (EFM32_MSC_REGBASE+0x01c)
#define EFM32_MSC_REG_ADDRB 0x010
#define EFM32_MSC_REG_WDATA 0x018
#define EFM32_MSC_REG_STATUS 0x01c
#define EFM32_MSC_STATUS_BUSY_MASK 0x1
#define EFM32_MSC_STATUS_LOCKED_MASK 0x2
#define EFM32_MSC_STATUS_INVADDR_MASK 0x4
#define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
#define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
#define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
#define EFM32_MSC_LOCK (EFM32_MSC_REGBASE+0x03c)
#define EFM32_MSC_REG_LOCK 0x03c
#define EFR32_MSC_REG_LOCK 0x040
#define EFM32_MSC_LOCK_LOCKKEY 0x1b71
struct efm32x_flash_bank {
int probed;
uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
uint32_t reg_base;
uint32_t reg_lock;
};
struct efm32_info {
@ -132,11 +138,30 @@ static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
}
static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
uint32_t *value)
{
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
uint32_t base = efm32x_info->reg_base;
return target_read_u32(bank->target, base + offset, value);
}
static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
uint32_t value)
{
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
uint32_t base = efm32x_info->reg_base;
return target_write_u32(bank->target, base + offset, value);
}
static int efm32x_read_info(struct flash_bank *bank,
struct efm32_info *efm32_info)
{
int ret;
uint32_t cpuid = 0;
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
memset(efm32_info, 0, sizeof(struct efm32_info));
@ -175,6 +200,15 @@ static int efm32x_read_info(struct flash_bank *bank,
if (ERROR_OK != ret)
return ret;
if (EFR_FAMILY_ID_BLUE_GECKO == efm32_info->part_family ||
EFR_FAMILY_ID_MIGHTY_GECKO == efm32_info->part_family) {
efm32x_info->reg_base = EFR32_MSC_REGBASE;
efm32x_info->reg_lock = EFR32_MSC_REG_LOCK;
} else {
efm32x_info->reg_base = EFM32_MSC_REGBASE;
efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
}
if (EFM_FAMILY_ID_GECKO == efm32_info->part_family ||
EFM_FAMILY_ID_TINY_GECKO == efm32_info->part_family)
efm32_info->page_size = 512;
@ -208,7 +242,9 @@ static int efm32x_read_info(struct flash_bank *bank,
}
} else if (EFM_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
EZR_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
EZR_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
EZR_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family ||
EFR_FAMILY_ID_BLUE_GECKO == efm32_info->part_family ||
EFR_FAMILY_ID_MIGHTY_GECKO == efm32_info->part_family) {
uint8_t pg_size = 0;
ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
&pg_size);
@ -241,6 +277,10 @@ static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
case EZR_FAMILY_ID_HAPPY_GECKO:
printed = snprintf(buf, buf_size, "EZR32 ");
break;
case EFR_FAMILY_ID_MIGHTY_GECKO:
case EFR_FAMILY_ID_BLUE_GECKO:
printed = snprintf(buf, buf_size, "EFR32 ");
break;
default:
printed = snprintf(buf, buf_size, "EFM32 ");
}
@ -276,6 +316,12 @@ static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
case EZR_FAMILY_ID_HAPPY_GECKO:
printed = snprintf(buf, buf_size, "Happy Gecko");
break;
case EFR_FAMILY_ID_BLUE_GECKO:
printed = snprintf(buf, buf_size, "Blue Gecko");
break;
case EFR_FAMILY_ID_MIGHTY_GECKO:
printed = snprintf(buf, buf_size, "Mighty Gecko");
break;
}
buf += printed;
@ -319,7 +365,7 @@ static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
int ret = 0;
uint32_t reg_val = 0;
ret = target_read_u32(bank->target, reg, &reg_val);
ret = efm32x_read_reg_u32(bank, reg, &reg_val);
if (ERROR_OK != ret)
return ret;
@ -328,18 +374,19 @@ static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
else
reg_val &= ~bitmask;
return target_write_u32(bank->target, reg, reg_val);
return efm32x_write_reg_u32(bank, reg, reg_val);
}
static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
{
return efm32x_set_reg_bits(bank, EFM32_MSC_WRITECTRL,
return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
}
static int efm32x_msc_lock(struct flash_bank *bank, int lock)
{
return target_write_u32(bank->target, EFM32_MSC_LOCK,
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
(lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
}
@ -350,7 +397,7 @@ static int efm32x_wait_status(struct flash_bank *bank, int timeout,
uint32_t status = 0;
while (1) {
ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
if (ERROR_OK != ret)
break;
@ -389,16 +436,16 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
if (ERROR_OK != ret)
return ret;
ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
if (ERROR_OK != ret)
return ret;
ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
if (ERROR_OK != ret)
return ret;
@ -412,7 +459,7 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
return ERROR_FAIL;
}
ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
if (ERROR_OK != ret)
return ret;
@ -589,6 +636,7 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
uint32_t address = bank->base + offset;
struct reg_param reg_params[5];
struct armv7m_algorithm armv7m_info;
struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
int ret = ERROR_OK;
/* see contrib/loaders/flash/efm32.S for src */
@ -598,10 +646,7 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
/* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
/* #define EFM32_MSC_WDATA_OFFSET 0x018 */
/* #define EFM32_MSC_STATUS_OFFSET 0x01c */
/* #define EFM32_MSC_LOCK_OFFSET 0x03c */
0x15, 0x4e, /* ldr r6, =#0x1b71 */
0xc6, 0x63, /* str r6, [r0, #EFM32_MSC_LOCK_OFFSET] */
0x01, 0x26, /* movs r6, #1 */
0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
@ -660,11 +705,9 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
/* exit: */
0x30, 0x46, /* mov r0, r6 */
0x00, 0xbe, /* bkpt #0 */
/* LOCKKEY */
0x71, 0x1b, 0x00, 0x00
};
/* flash write code */
if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
&write_algorithm) != ERROR_OK) {
@ -697,7 +740,7 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
buf_set_u32(reg_params[0].value, 0, 32, EFM32_MSC_REGBASE);
buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
buf_set_u32(reg_params[1].value, 0, 32, count);
buf_set_u32(reg_params[2].value, 0, 32, source->address);
buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
@ -762,16 +805,16 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
/* if not called, GDB errors will be reported during large writes */
keep_alive();
ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
if (ERROR_OK != ret)
return ret;
ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
if (ERROR_OK != ret)
return ret;
ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
if (ERROR_OK != ret)
return ret;
@ -792,13 +835,13 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
return ret;
}
ret = target_write_u32(bank->target, EFM32_MSC_WDATA, val);
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
if (ERROR_OK != ret) {
LOG_ERROR("WDATA write failed");
return ret;
}
ret = target_write_u32(bank->target, EFM32_MSC_WRITECMD,
ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
EFM32_MSC_WRITECMD_WRITEONCE_MASK);
if (ERROR_OK != ret) {
LOG_ERROR("WRITECMD write failed");

3
src/flash/nor/kinetis.c
View File

@ -1959,7 +1959,7 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
unsigned cpu_mhz = 120;
unsigned idx;
bool use_nvm_marking = false;
char flash_marking[8], nvm_marking[2];
char flash_marking[11], nvm_marking[2];
char name[40];
k_chip->probed = false;
@ -2126,6 +2126,7 @@ static int kinetis_probe_chip(struct kinetis_chip *k_chip)
case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1: /* errata 7534 - should be K63 */
case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2: /* errata 7534 - should be K64 */
subfamid += 2; /* errata 7534 fix */
/* fallthrough */
case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
/* K63FN1M0 */
case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:

811
src/flash/nor/nrf51.c → src/flash/nor/nrf5.c
View File

File diff suppressed because it is too large Load Diff

2
src/flash/nor/spi.c
View File

@ -69,6 +69,8 @@ const struct flash_device flash_devices[] = {
FLASH_ID("mac 25l6405", 0xd8, 0xc7, 0x001720c2, 0x100, 0x10000, 0x800000),
FLASH_ID("micron n25q064", 0xd8, 0xc7, 0x0017ba20, 0x100, 0x10000, 0x800000),
FLASH_ID("micron n25q128", 0xd8, 0xc7, 0x0018ba20, 0x100, 0x10000, 0x1000000),
FLASH_ID("micron n25q256 3v", 0xd8, 0xc7, 0x0019ba20, 0x100, 0x10000, 0x2000000),
FLASH_ID("micron n25q256 1.8v", 0xd8, 0xc7, 0x0019bb20, 0x100, 0x10000, 0x2000000),
FLASH_ID("issi is25lp128", 0xd8, 0xc7, 0x0018609d, 0x100, 0x10000, 0x1000000),
FLASH_ID("win w25q80bv", 0xd8, 0xc7, 0x001440ef, 0x100, 0x10000, 0x100000),
FLASH_ID("win w25q32fv", 0xd8, 0xc7, 0x001640ef, 0x100, 0x10000, 0x400000),

17
src/flash/nor/stm32f2x.c
View File

@ -143,9 +143,8 @@
#define FLASH_PSIZE_16 (1 << 8)
#define FLASH_PSIZE_32 (2 << 8)
#define FLASH_PSIZE_64 (3 << 8)
/* The sector number encoding is not straight binary for dual bank flash.
* Warning: evaluates the argument multiple times */
#define FLASH_SNB(a) ((((a) >= 12) ? 0x10 | ((a) - 12) : (a)) << 3)
/* The sector number encoding is not straight binary for dual bank flash. */
#define FLASH_SNB(a) ((a) << 3)
#define FLASH_LOCK (1 << 31)
/* FLASH_SR register bits */
@ -489,6 +488,7 @@ static int stm32x_protect_check(struct flash_bank *bank)
static int stm32x_erase(struct flash_bank *bank, int first, int last)
{
struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
struct target *target = bank->target;
int i;
@ -516,8 +516,14 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
*/
for (i = first; i <= last; i++) {
int snb;
if (stm32x_info->has_large_mem && i >= 12)
snb = (i - 12) | 0x10;
else
snb = i;
retval = target_write_u32(target,
stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(i) | FLASH_STRT);
stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(snb) | FLASH_STRT);
if (retval != ERROR_OK)
return retval;
@ -1047,7 +1053,8 @@ static int stm32x_probe(struct flash_bank *bank)
if (device_id == 0x451) {
for (i = 0; i < num_prot_blocks; i++) {
bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
bank->prot_blocks[i].size = bank->sectors[i << 1].size << 1;
bank->prot_blocks[i].size = bank->sectors[i << 1].size
+ bank->sectors[(i << 1) + 1].size;
}
}
} else {

1183
src/flash/nor/stm32h7x.c Normal file
View File

File diff suppressed because it is too large Load Diff

15
src/flash/nor/stm32lx.c
View File

@ -726,16 +726,13 @@ reset_pg_and_lock:
static int stm32lx_read_id_code(struct target *target, uint32_t *id)
{
/* read stm32 device id register */
int retval = target_read_u32(target, DBGMCU_IDCODE, id);
if (retval != ERROR_OK)
return retval;
/* STM32L0 parts will have 0 there, try reading the L0's location for
* DBG_IDCODE in case this is an L0 part. */
if (*id == 0)
struct armv7m_common *armv7m = target_to_armv7m(target);
int retval;
if (armv7m->arm.is_armv6m == true)
retval = target_read_u32(target, DBGMCU_IDCODE_L0, id);
else
/* read stm32 device id register */
retval = target_read_u32(target, DBGMCU_IDCODE, id);
return retval;
}

4
src/flash/nor/xmc4xxx.c
View File

@ -931,13 +931,13 @@ static int xmc4xxx_get_info_command(struct flash_bank *bank, char *buf, int buf_
/* If OTP Write protection is enabled (User 2), list each
* sector that has it enabled */
char otp_str[8];
char otp_str[14];
if (otp_enabled) {
strcat(prot_str, "\nOTP Protection is enabled for sectors:\n");
for (int i = 0; i < bank->num_sectors; i++) {
if (fb->write_prot_otp[i]) {
snprintf(otp_str, sizeof(otp_str), "- %d\n", i);
strncat(prot_str, otp_str, ARRAY_SIZE(otp_str));
strncat(prot_str, otp_str, sizeof(prot_str) - strlen(prot_str) - 1);
}
}
}

2
src/helper/command.c
View File

@ -1456,8 +1456,8 @@ COMMAND_HELPER(handle_command_parse_bool, bool *out, const char *label)
LOG_ERROR("%s: argument '%s' is not valid", CMD_NAME, in);
return ERROR_COMMAND_SYNTAX_ERROR;
}
/* fall through */
}
/* fallthrough */
case 0:
LOG_INFO("%s is %s", label, *out ? "enabled" : "disabled");
break;

3
src/helper/options.c
View File

@ -37,6 +37,9 @@
#ifdef HAVE_SYS_SYSCTL_H
#include <sys/sysctl.h>
#endif
#if IS_WIN32 && !IS_CYGWIN
#include <windows.h>
#endif
static int help_flag, version_flag;

3
src/jtag/drivers/cmsis_dap_usb.c
View File

@ -958,11 +958,14 @@ static int cmsis_dap_init(void)
retval = cmsis_dap_cmd_DAP_TFER_Configure(0, 64, 0);
if (retval != ERROR_OK)
return ERROR_FAIL;
if (swd_mode) {
/* Data Phase (bit 2) must be set to 1 if sticky overrun
* detection is enabled */
retval = cmsis_dap_cmd_DAP_SWD_Configure(0); /* 1 TRN, no Data Phase */
if (retval != ERROR_OK)
return ERROR_FAIL;
}
retval = cmsis_dap_cmd_DAP_LED(0x03); /* Both LEDs on */
if (retval != ERROR_OK)

4
src/jtag/drivers/ftdi.c
View File

@ -855,6 +855,7 @@ COMMAND_HANDLER(ftdi_handle_set_signal_command)
ftdi_set_signal(sig, *CMD_ARGV[1]);
break;
}
/* fallthrough */
default:
LOG_ERROR("unknown signal level '%s', use 0, 1 or z", CMD_ARGV[1]);
return ERROR_COMMAND_SYNTAX_ERROR;
@ -1217,14 +1218,17 @@ static int ftdi_swd_switch_seq(enum swd_special_seq seq)
switch (seq) {
case LINE_RESET:
LOG_DEBUG("SWD line reset");
ftdi_swd_swdio_en(true);
mpsse_clock_data_out(mpsse_ctx, swd_seq_line_reset, 0, swd_seq_line_reset_len, SWD_MODE);
break;
case JTAG_TO_SWD:
LOG_DEBUG("JTAG-to-SWD");
ftdi_swd_swdio_en(true);
mpsse_clock_data_out(mpsse_ctx, swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len, SWD_MODE);
break;
case SWD_TO_JTAG:
LOG_DEBUG("SWD-to-JTAG");
ftdi_swd_swdio_en(true);
mpsse_clock_data_out(mpsse_ctx, swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len, SWD_MODE);
break;
default:

110
src/jtag/drivers/jlink.c
View File

@ -322,7 +322,7 @@ static int jlink_speed(int speed)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_speeds() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_JTAG_DEVICE_ERROR;
}
@ -349,7 +349,7 @@ static int jlink_speed(int speed)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_set_speed() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_JTAG_DEVICE_ERROR;
}
@ -378,7 +378,7 @@ static bool read_device_config(struct device_config *cfg)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_read_raw_config() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return false;
}
@ -409,7 +409,7 @@ static int select_interface(void)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_available_interfaces() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_JTAG_INIT_FAILED;
}
@ -422,7 +422,7 @@ static int select_interface(void)
if (ret < 0) {
LOG_ERROR("jaylink_select_interface() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_JTAG_INIT_FAILED;
}
@ -442,8 +442,7 @@ static int jlink_register(void)
ret = jaylink_register(devh, &conn, connlist, &count);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_register() failed: %s.",
jaylink_strerror_name(ret));
LOG_ERROR("jaylink_register() failed: %s.", jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -482,7 +481,7 @@ static bool adjust_swd_buffer_size(void)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_free_memory() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return false;
}
@ -523,6 +522,9 @@ static int jaylink_log_handler(const struct jaylink_context *ctx,
case JAYLINK_LOG_LEVEL_DEBUG:
tmp = LOG_LVL_DEBUG;
break;
case JAYLINK_LOG_LEVEL_DEBUG_IO:
tmp = LOG_LVL_DEBUG_IO;
break;
default:
tmp = LOG_LVL_WARNING;
}
@ -544,15 +546,21 @@ static int jlink_init(void)
struct jaylink_hardware_status hwstatus;
enum jaylink_usb_address address;
size_t length;
size_t num_devices;
uint32_t host_interfaces;
LOG_DEBUG("Using libjaylink %s (compiled with %s).",
jaylink_version_package_get_string(), JAYLINK_VERSION_PACKAGE_STRING);
if (!jaylink_library_has_cap(JAYLINK_CAP_HIF_USB) && use_usb_address) {
LOG_ERROR("J-Link driver does not support USB devices.");
return ERROR_JTAG_INIT_FAILED;
}
ret = jaylink_init(&jayctx);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_init() failed: %s.",
jaylink_strerror_name(ret));
LOG_ERROR("jaylink_init() failed: %s.", jaylink_strerror(ret));
return ERROR_JTAG_INIT_FAILED;
}
@ -560,34 +568,42 @@ static int jlink_init(void)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_log_set_callback() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
}
ret = jaylink_discovery_scan(jayctx, 0);
host_interfaces = JAYLINK_HIF_USB;
if (use_serial_number)
host_interfaces |= JAYLINK_HIF_TCP;
ret = jaylink_discovery_scan(jayctx, host_interfaces);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_discovery_scan() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
}
ret = jaylink_get_devices(jayctx, &devs, NULL);
ret = jaylink_get_devices(jayctx, &devs, &num_devices);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_devices() failed: %s.",
jaylink_strerror_name(ret));
LOG_ERROR("jaylink_get_devices() failed: %s.", jaylink_strerror(ret));
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
}
if (!use_serial_number && !use_usb_address && num_devices > 1) {
LOG_ERROR("Multiple devices found, specify the desired device.");
jaylink_free_devices(devs, true);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
}
found_device = false;
if (!use_serial_number && !use_usb_address)
LOG_INFO("No device selected, using first device.");
for (i = 0; devs[i]; i++) {
if (use_serial_number) {
ret = jaylink_device_get_serial_number(devs[i], &tmp);
@ -596,7 +612,7 @@ static int jlink_init(void)
continue;
} else if (ret != JAYLINK_OK) {
LOG_WARNING("jaylink_device_get_serial_number() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
continue;
}
@ -607,9 +623,11 @@ static int jlink_init(void)
if (use_usb_address) {
ret = jaylink_device_get_usb_address(devs[i], &address);
if (ret != JAYLINK_OK) {
if (ret == JAYLINK_ERR_NOT_SUPPORTED) {
continue;
} else if (ret != JAYLINK_OK) {
LOG_WARNING("jaylink_device_get_usb_address() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
continue;
}
@ -624,7 +642,7 @@ static int jlink_init(void)
break;
}
LOG_ERROR("Failed to open device: %s.", jaylink_strerror_name(ret));
LOG_ERROR("Failed to open device: %s.", jaylink_strerror(ret));
}
jaylink_free_devices(devs, true);
@ -644,7 +662,7 @@ static int jlink_init(void)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_firmware_version() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@ -659,7 +677,7 @@ static int jlink_init(void)
ret = jaylink_get_caps(devh, caps);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_caps() failed: %s.", jaylink_strerror_name(ret));
LOG_ERROR("jaylink_get_caps() failed: %s.", jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@ -670,7 +688,7 @@ static int jlink_init(void)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_extended_caps() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@ -684,7 +702,7 @@ static int jlink_init(void)
if (ret != JAYLINK_OK) {
LOG_ERROR("Failed to retrieve hardware version: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@ -725,7 +743,7 @@ static int jlink_init(void)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_hardware_status() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
jaylink_close(devh);
jaylink_exit(jayctx);
return ERROR_JTAG_INIT_FAILED;
@ -786,8 +804,7 @@ static int jlink_quit(void)
ret = jaylink_swo_stop(devh);
if (ret != JAYLINK_OK)
LOG_ERROR("jaylink_swo_stop() failed: %s.",
jaylink_strerror_name(ret));
LOG_ERROR("jaylink_swo_stop() failed: %s.", jaylink_strerror(ret));
}
if (jaylink_has_cap(caps, JAYLINK_DEV_CAP_REGISTER)) {
@ -795,7 +812,7 @@ static int jlink_quit(void)
if (ret != JAYLINK_OK)
LOG_ERROR("jaylink_unregister() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
}
jaylink_close(devh);
@ -944,7 +961,7 @@ COMMAND_HANDLER(jlink_serial_command)
return ERROR_FAIL;
} else if (ret != JAYLINK_OK) {
command_print(CMD_CTX, "jaylink_parse_serial_number() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -963,7 +980,7 @@ COMMAND_HANDLER(jlink_handle_hwstatus_command)
if (ret != JAYLINK_OK) {
command_print(CMD_CTX, "jaylink_get_hardware_status() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -995,7 +1012,7 @@ COMMAND_HANDLER(jlink_handle_free_memory_command)
if (ret != JAYLINK_OK) {
command_print(CMD_CTX, "jaylink_get_free_memory() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1077,7 +1094,7 @@ COMMAND_HANDLER(jlink_handle_target_power_command)
if (ret != JAYLINK_OK) {
command_print(CMD_CTX, "jaylink_set_target_power() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1183,7 +1200,7 @@ static int poll_trace(uint8_t *buf, size_t *size)
ret = jaylink_swo_read(devh, buf, &length);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_swo_read() failed: %s.", jaylink_strerror_name(ret));
LOG_ERROR("jaylink_swo_read() failed: %s.", jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1204,7 +1221,7 @@ static uint32_t calculate_trace_buffer_size(void)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_get_free_memory() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1268,7 +1285,7 @@ static int config_trace(bool enabled, enum tpio_pin_protocol pin_protocol,
ret = jaylink_swo_stop(devh);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_swo_stop() failed: %s.", jaylink_strerror_name(ret));
LOG_ERROR("jaylink_swo_stop() failed: %s.", jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1294,7 +1311,7 @@ static int config_trace(bool enabled, enum tpio_pin_protocol pin_protocol,
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_swo_get_speeds() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1310,8 +1327,7 @@ static int config_trace(bool enabled, enum tpio_pin_protocol pin_protocol,
buffer_size);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_start_swo() failed: %s.",
jaylink_strerror_name(ret));
LOG_ERROR("jaylink_start_swo() failed: %s.", jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1570,7 +1586,7 @@ COMMAND_HANDLER(jlink_handle_config_write_command)
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_write_raw_config() failed: %s.",
jaylink_strerror_name(ret));
jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1655,8 +1671,7 @@ COMMAND_HANDLER(jlink_handle_emucom_write_command)
LOG_ERROR("Channel not supported by the device.");
return ERROR_FAIL;
} else if (ret != JAYLINK_OK) {
LOG_ERROR("Failed to write to channel: %s.",
jaylink_strerror_name(ret));
LOG_ERROR("Failed to write to channel: %s.", jaylink_strerror(ret));
return ERROR_FAIL;
}
@ -1704,8 +1719,7 @@ COMMAND_HANDLER(jlink_handle_emucom_read_command)
free(buf);
return ERROR_FAIL;
} else if (ret != JAYLINK_OK) {
LOG_ERROR("Failed to read from channel: %s.",
jaylink_strerror_name(ret));
LOG_ERROR("Failed to read from channel: %s.", jaylink_strerror(ret));
free(buf);
return ERROR_FAIL;
}
@ -1972,7 +1986,7 @@ static int jlink_flush(void)
tap_length, jtag_command_version);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_jtag_io() failed: %s.", jaylink_strerror_name(ret));
LOG_ERROR("jaylink_jtag_io() failed: %s.", jaylink_strerror(ret));
jlink_tap_init();
return ERROR_JTAG_QUEUE_FAILED;
}
@ -2078,7 +2092,7 @@ static int jlink_swd_run_queue(void)
ret = jaylink_swd_io(devh, tms_buffer, tdi_buffer, tdo_buffer, tap_length);
if (ret != JAYLINK_OK) {
LOG_ERROR("jaylink_swd_io() failed: %s.", jaylink_strerror_name(ret));
LOG_ERROR("jaylink_swd_io() failed: %s.", jaylink_strerror(ret));
goto skip;
}

1
src/jtag/drivers/kitprog.c
View File

@ -657,6 +657,7 @@ static int kitprog_swd_switch_seq(enum swd_special_seq seq)
LOG_DEBUG("JTAG to SWD not supported");
/* Fall through to fix target reset issue */
}
/* fallthrough */
case LINE_RESET:
LOG_DEBUG("SWD line reset");
if (kitprog_swd_seq(SEQUENCE_LINE_RESET) != ERROR_OK)

2
src/jtag/drivers/libjaylink

@ -1 +1 @@
Subproject commit 699b7001d34a79c8e7064503dde1bede786fd7f0
Subproject commit 8645845c1abebd004e991ba9a7f808f4fd0c608b

24
src/jtag/drivers/stlink_usb.c
View File

@ -1650,13 +1650,11 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
h->transport = param->transport;
const uint16_t vids[] = { param->vid, 0 };
const uint16_t pids[] = { param->pid, 0 };
const char *serial = param->serial;
for (unsigned i = 0; param->vid[i]; i++) {
LOG_DEBUG("transport: %d vid: 0x%04x pid: 0x%04x serial: %s",
param->transport, param->vid, param->pid,
param->transport, param->vid[i], param->pid[i],
param->serial ? param->serial : "");
}
/*
On certain host USB configurations(e.g. MacBook Air)
@ -1668,7 +1666,7 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
in order to become operational.
*/
do {
if (jtag_libusb_open(vids, pids, serial, &h->fd) != ERROR_OK) {
if (jtag_libusb_open(param->vid, param->pid, param->serial, &h->fd) != ERROR_OK) {
LOG_ERROR("open failed");
goto error_open;
}
@ -1683,8 +1681,14 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
/* RX EP is common for all versions */
h->rx_ep = STLINK_RX_EP;
uint16_t pid;
if (jtag_libusb_get_pid(jtag_libusb_get_device(h->fd), &pid) != ERROR_OK) {
LOG_DEBUG("libusb_get_pid failed");
goto error_open;
}
/* wrap version for first read */
switch (param->pid) {
switch (pid) {
case STLINK_V1_PID:
h->version.stlink = 1;
h->tx_ep = STLINK_TX_EP;
@ -1736,12 +1740,6 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
}
} while (1);
/* compare usb vid/pid */
if ((param->vid != h->vid) || (param->pid != h->pid))
LOG_INFO("vid/pid are not identical: 0x%04X/0x%04X 0x%04X/0x%04X",
param->vid, param->pid,
h->vid, h->pid);
/* check if mode is supported */
err = ERROR_OK;

8
src/jtag/drivers/ti_icdi_usb.c
View File

@ -688,14 +688,18 @@ static int icdi_usb_open(struct hl_interface_param_s *param, void **fd)
}
LOG_DEBUG("transport: %d vid: 0x%04x pid: 0x%04x", param->transport,
param->vid, param->pid);
param->vid[0], param->pid[0]);
/* TODO: convert libusb_ calls to jtag_libusb_ */
if (param->vid[1])
LOG_WARNING("Bad configuration: 'hla_vid_pid' command does not accept more than one VID PID pair on ti-icdi!");
if (libusb_init(&h->usb_ctx) != 0) {
LOG_ERROR("libusb init failed");
goto error_open;
}
h->usb_dev = libusb_open_device_with_vid_pid(h->usb_ctx, param->vid, param->pid);
h->usb_dev = libusb_open_device_with_vid_pid(h->usb_ctx, param->vid[0], param->pid[0]);
if (!h->usb_dev) {
LOG_ERROR("open failed");
goto error_open;

26
src/jtag/hla/hla_interface.c
View File

@ -35,7 +35,7 @@
#include <target/target.h>
static struct hl_interface_s hl_if = { {0, 0, 0, 0, 0, HL_TRANSPORT_UNKNOWN, false, -1}, 0, 0 };
static struct hl_interface_s hl_if = { {0, 0, { 0 }, { 0 }, 0, HL_TRANSPORT_UNKNOWN, false, -1}, 0, 0 };
int hl_interface_open(enum hl_transports tr)
{
@ -264,15 +264,27 @@ COMMAND_HANDLER(hl_interface_handle_layout_command)
COMMAND_HANDLER(hl_interface_handle_vid_pid_command)
{
LOG_DEBUG("hl_interface_handle_vid_pid_command");
if (CMD_ARGC != 2) {
LOG_WARNING("ignoring extra IDs in hl_vid_pid (maximum is 1 pair)");
if (CMD_ARGC > HLA_MAX_USB_IDS * 2) {
LOG_WARNING("ignoring extra IDs in hla_vid_pid "
"(maximum is %d pairs)", HLA_MAX_USB_IDS);
CMD_ARGC = HLA_MAX_USB_IDS * 2;
}
if (CMD_ARGC < 2 || (CMD_ARGC & 1)) {
LOG_WARNING("incomplete hla_vid_pid configuration directive");
return ERROR_COMMAND_SYNTAX_ERROR;
}
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], hl_if.param.vid);
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], hl_if.param.pid);
unsigned i;
for (i = 0; i < CMD_ARGC; i += 2) {
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i], hl_if.param.vid[i / 2]);
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[i + 1], hl_if.param.pid[i / 2]);
}
/*
* Explicitly terminate, in case there are multiple instances of
* hla_vid_pid.
*/
hl_if.param.vid[i / 2] = hl_if.param.pid[i / 2] = 0;
return ERROR_OK;
}

10
src/jtag/hla/hla_interface.h
View File

@ -29,15 +29,17 @@ enum e_hl_transports;
/** */
extern const char *hl_transports[];
#define HLA_MAX_USB_IDS 8
struct hl_interface_param_s {
/** */
const char *device_desc;
/** */
const char *serial;
/** */
uint16_t vid;
/** */
uint16_t pid;
/** List of recognised VIDs */
uint16_t vid[HLA_MAX_USB_IDS + 1];
/** List of recognised PIDs */
uint16_t pid[HLA_MAX_USB_IDS + 1];
/** */
unsigned api;
/** */

10
src/rtos/ChibiOS.c
View File

@ -103,7 +103,7 @@ static struct ChibiOS_params ChibiOS_params_list[] = {
};
#define CHIBIOS_NUM_PARAMS ((int)(sizeof(ChibiOS_params_list)/sizeof(struct ChibiOS_params)))
static int ChibiOS_detect_rtos(struct target *target);
static bool ChibiOS_detect_rtos(struct target *target);
static int ChibiOS_create(struct target *target);
static int ChibiOS_update_threads(struct rtos *rtos);
static int ChibiOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
@ -510,7 +510,7 @@ static int ChibiOS_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
return 0;
}
static int ChibiOS_detect_rtos(struct target *target)
static bool ChibiOS_detect_rtos(struct target *target)
{
if ((target->rtos->symbols != NULL) &&
((target->rtos->symbols[ChibiOS_VAL_rlist].address != 0) ||
@ -519,14 +519,14 @@ static int ChibiOS_detect_rtos(struct target *target)
if (target->rtos->symbols[ChibiOS_VAL_ch_debug].address == 0) {
LOG_INFO("It looks like the target may be running ChibiOS "
"without ch_debug.");
return 0;
return false;
}
/* looks like ChibiOS with memory map enabled.*/
return 1;
return true;
}
return 0;
return false;
}
static int ChibiOS_create(struct target *target)

8
src/rtos/FreeRTOS.c
View File

@ -99,7 +99,7 @@ static const struct FreeRTOS_params FreeRTOS_params_list[] = {
#define FREERTOS_NUM_PARAMS ((int)(sizeof(FreeRTOS_params_list)/sizeof(struct FreeRTOS_params)))
static int FreeRTOS_detect_rtos(struct target *target);
static bool FreeRTOS_detect_rtos(struct target *target);
static int FreeRTOS_create(struct target *target);
static int FreeRTOS_update_threads(struct rtos *rtos);
static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
@ -528,14 +528,14 @@ static int FreeRTOS_get_thread_ascii_info(struct rtos *rtos, threadid_t thread_i
#endif
static int FreeRTOS_detect_rtos(struct target *target)
static bool FreeRTOS_detect_rtos(struct target *target)
{
if ((target->rtos->symbols != NULL) &&
(target->rtos->symbols[FreeRTOS_VAL_pxReadyTasksLists].address != 0)) {
/* looks like FreeRTOS */
return 1;
return true;
}
return 0;
return false;
}
static int FreeRTOS_create(struct target *target)

8
src/rtos/ThreadX.c
View File

@ -35,7 +35,7 @@ static const struct rtos_register_stacking *get_stacking_info_arm926ejs(const st
static int is_thread_id_valid(const struct rtos *rtos, int64_t thread_id);
static int is_thread_id_valid_arm926ejs(const struct rtos *rtos, int64_t thread_id);
static int ThreadX_detect_rtos(struct target *target);
static bool ThreadX_detect_rtos(struct target *target);
static int ThreadX_create(struct target *target);
static int ThreadX_update_threads(struct rtos *rtos);
static int ThreadX_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
@ -492,14 +492,14 @@ static int ThreadX_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
return 0;
}
static int ThreadX_detect_rtos(struct target *target)
static bool ThreadX_detect_rtos(struct target *target)
{
if ((target->rtos->symbols != NULL) &&
(target->rtos->symbols[ThreadX_VAL_tx_thread_created_ptr].address != 0)) {
/* looks like ThreadX */
return 1;
return true;
}
return 0;
return false;
}
#if 0

8
src/rtos/eCos.c
View File

@ -27,7 +27,7 @@
#include "helper/types.h"
#include "rtos_ecos_stackings.h"
static int eCos_detect_rtos(struct target *target);
static bool eCos_detect_rtos(struct target *target);
static int eCos_create(struct target *target);
static int eCos_update_threads(struct rtos *rtos);
static int eCos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
@ -363,14 +363,14 @@ static int eCos_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
return 0;
}
static int eCos_detect_rtos(struct target *target)
static bool eCos_detect_rtos(struct target *target)
{
if ((target->rtos->symbols != NULL) &&
(target->rtos->symbols[eCos_VAL_thread_list].address != 0)) {
/* looks like eCos */
return 1;
return true;
}
return 0;
return false;
}
static int eCos_create(struct target *target)

8
src/rtos/embKernel.c
View File

@ -31,7 +31,7 @@
#define EMBKERNEL_MAX_THREAD_NAME_STR_SIZE (64)
static int embKernel_detect_rtos(struct target *target);
static bool embKernel_detect_rtos(struct target *target);
static int embKernel_create(struct target *target);
static int embKernel_update_threads(struct rtos *rtos);
static int embKernel_get_thread_reg_list(struct rtos *rtos, int64_t thread_id, char **hex_reg_list);
@ -107,13 +107,13 @@ static const struct embKernel_params embKernel_params_list[] = {
}
};
static int embKernel_detect_rtos(struct target *target)
static bool embKernel_detect_rtos(struct target *target)
{
if (target->rtos->symbols != NULL) {
if (target->rtos->symbols[SYMBOL_ID_sCurrentTask].address != 0)
return 1;
return true;
}
return 0;
return false;
}
static int embKernel_create(struct target *target)

4
src/rtos/linux.c
View File

@ -309,10 +309,10 @@ static int linux_os_thread_reg_list(struct rtos *rtos,
return ERROR_OK;
}
static int linux_os_detect(struct target *target)
static bool linux_os_detect(struct target *target)
{
LOG_INFO("should no be called");
return 0;
return false;
}
static int linux_os_smp_init(struct target *target);

8
src/rtos/mqx.c
View File

@ -244,9 +244,9 @@ static int mqx_is_scheduler_running(
}
/*
* API function, return 1 if MQX is present
* API function, return true if MQX is present
*/
static int mqx_detect_rtos(
static bool mqx_detect_rtos(
struct target *target
)
{
@ -254,9 +254,9 @@ static int mqx_detect_rtos(
(target->rtos->symbols != NULL) &&
(target->rtos->symbols[mqx_VAL_mqx_kernel_data].address != 0)
) {
return 1;
return true;
}
return 0;
return false;
}
/*

2
src/rtos/riscv_debug.c
View File

@ -10,7 +10,7 @@
static int riscv_gdb_thread_packet(struct connection *connection, const char *packet, int packet_size);
static int riscv_gdb_v_packet(struct connection *connection, const char *packet, int packet_size);
static int riscv_detect_rtos(struct target *target)
static bool riscv_detect_rtos(struct target *target)
{
LOG_ERROR("riscv_detect_rtos() unimplemented");
return -1;

2
src/rtos/rtos.h
View File

@ -60,7 +60,7 @@ struct rtos {
struct rtos_type {
const char *name;
int (*detect_rtos)(struct target *target);
bool (*detect_rtos)(struct target *target);
int (*create)(struct target *target);
int (*smp_init)(struct target *target);
int (*update_threads)(struct rtos *rtos);

2
src/rtos/uCOS-III.c
View File

@ -241,7 +241,7 @@ static int uCOS_III_update_thread_offsets(struct rtos *rtos)
return ERROR_OK;
}
static int uCOS_III_detect_rtos(struct target *target)
static bool uCOS_III_detect_rtos(struct target *target)
{
return target->rtos->symbols != NULL &&
target->rtos->symbols[uCOS_III_VAL_OSRunning].address != 0;

98
src/server/gdb_server.c
View File

@ -71,8 +71,8 @@ struct gdb_connection {
int ctrl_c;
enum target_state frontend_state;
struct image *vflash_image;
int closed;
int busy;
bool closed;
bool busy;
int noack_mode;
/* set flag to true if you want the next stepi to return immediately.
* allowing GDB to pick up a fresh set of register values from the target
@ -215,7 +215,7 @@ static int gdb_get_char_inner(struct connection *connection, int *next_char)
if (gdb_con->buf_cnt > 0)
break;
if (gdb_con->buf_cnt == 0) {
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
}
@ -227,10 +227,10 @@ static int gdb_get_char_inner(struct connection *connection, int *next_char)
usleep(1000);
break;
case WSAECONNABORTED:
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
case WSAECONNRESET:
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
default:
LOG_ERROR("read: %d", errno);
@ -242,14 +242,14 @@ static int gdb_get_char_inner(struct connection *connection, int *next_char)
usleep(1000);
break;
case ECONNABORTED:
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
case ECONNRESET:
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
default:
LOG_ERROR("read: %s", strerror(errno));
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
}
#endif
@ -341,7 +341,7 @@ static int gdb_write(struct connection *connection, void *data, int len)
if (connection_write(connection, data, len) == len)
return ERROR_OK;
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
}
@ -448,7 +448,7 @@ static int gdb_put_packet_inner(struct connection *connection,
return ERROR_OK;
} else {
LOG_ERROR("unknown character(1) 0x%2.2x in reply, dropping connection", reply);
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
}
} else if (reply == '$') {
@ -458,7 +458,7 @@ static int gdb_put_packet_inner(struct connection *connection,
} else {
LOG_ERROR("unknown character(2) 0x%2.2x in reply, dropping connection",
reply);
gdb_con->closed = 1;
gdb_con->closed = true;
return ERROR_SERVER_REMOTE_CLOSED;
}
}
@ -471,9 +471,9 @@ static int gdb_put_packet_inner(struct connection *connection,
int gdb_put_packet(struct connection *connection, char *buffer, int len)
{
struct gdb_connection *gdb_con = connection->priv;
gdb_con->busy = 1;
gdb_con->busy = true;
int retval = gdb_put_packet_inner(connection, buffer, len);
gdb_con->busy = 0;
gdb_con->busy = false;
/* we sent some data, reset timer for keep alive messages */
kept_alive();
@ -679,9 +679,9 @@ static int gdb_get_packet_inner(struct connection *connection,
static int gdb_get_packet(struct connection *connection, char *buffer, int *len)
{
struct gdb_connection *gdb_con = connection->priv;
gdb_con->busy = 1;
gdb_con->busy = true;
int retval = gdb_get_packet_inner(connection, buffer, len);
gdb_con->busy = 0;
gdb_con->busy = false;
return retval;
}
@ -917,10 +917,11 @@ static int gdb_target_callback_event_handler(struct target *target,
static int gdb_new_connection(struct connection *connection)
{
struct gdb_connection *gdb_connection = malloc(sizeof(struct gdb_connection));
struct gdb_service *gdb_service = connection->service->priv;
struct target *target;
int retval;
int initial_ack;
target = get_target_from_connection(connection);
connection->priv = gdb_connection;
/* initialize gdb connection information */
@ -929,8 +930,8 @@ static int gdb_new_connection(struct connection *connection)
gdb_connection->ctrl_c = 0;
gdb_connection->frontend_state = TARGET_HALTED;
gdb_connection->vflash_image = NULL;
gdb_connection->closed = 0;
gdb_connection->busy = 0;
gdb_connection->closed = false;
gdb_connection->busy = false;
gdb_connection->noack_mode = 0;
gdb_connection->sync = false;
gdb_connection->mem_write_error = false;
@ -949,12 +950,12 @@ static int gdb_new_connection(struct connection *connection)
* GDB session could leave dangling breakpoints if e.g. communication
* timed out.
*/
breakpoint_clear_target(gdb_service->target);
watchpoint_clear_target(gdb_service->target);
breakpoint_clear_target(target);
watchpoint_clear_target(target);
/* clean previous rtos session if supported*/
if ((gdb_service->target->rtos) && (gdb_service->target->rtos->type->clean))
gdb_service->target->rtos->type->clean(gdb_service->target);
if ((target->rtos) && (target->rtos->type->clean))
target->rtos->type->clean(target);
/* remove the initial ACK from the incoming buffer */
retval = gdb_get_char(connection, &initial_ack);
@ -966,7 +967,7 @@ static int gdb_new_connection(struct connection *connection)
*/
if (initial_ack != '+')
gdb_putback_char(connection, initial_ack);
target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_ATTACH);
target_call_event_callbacks(target, TARGET_EVENT_GDB_ATTACH);
if (gdb_use_memory_map) {
/* Connect must fail if the memory map can't be set up correctly.
@ -978,7 +979,7 @@ static int gdb_new_connection(struct connection *connection)
for (i = 0; i < flash_get_bank_count(); i++) {
struct flash_bank *p;
p = get_flash_bank_by_num_noprobe(i);
if (p->target != gdb_service->target)
if (p->target != target)
continue;
retval = get_flash_bank_by_num(i, &p);
if (retval != ERROR_OK) {
@ -992,8 +993,8 @@ static int gdb_new_connection(struct connection *connection)
gdb_actual_connections++;
LOG_DEBUG("New GDB Connection: %d, Target %s, state: %s",
gdb_actual_connections,
target_name(gdb_service->target),
target_state_name(gdb_service->target));
target_name(target),
target_state_name(target));
/* DANGER! If we fail subsequently, we must remove this handler,
* otherwise we occasionally see crashes as the timer can invoke the
@ -1007,9 +1008,11 @@ static int gdb_new_connection(struct connection *connection)
static int gdb_connection_closed(struct connection *connection)
{
struct gdb_service *gdb_service = connection->service->priv;
struct target *target;
struct gdb_connection *gdb_connection = connection->priv;
target = get_target_from_connection(connection);
/* we're done forwarding messages. Tear down callback before
* cleaning up connection.
*/
@ -1017,8 +1020,8 @@ static int gdb_connection_closed(struct connection *connection)
gdb_actual_connections--;
LOG_DEBUG("GDB Close, Target: %s, state: %s, gdb_actual_connections=%d",
target_name(gdb_service->target),
target_state_name(gdb_service->target),
target_name(target),
target_state_name(target),
gdb_actual_connections);
/* see if an image built with vFlash commands is left */
@ -1029,7 +1032,7 @@ static int gdb_connection_closed(struct connection *connection)
}
/* if this connection registered a debug-message receiver delete it */
delete_debug_msg_receiver(connection->cmd_ctx, gdb_service->target);
delete_debug_msg_receiver(connection->cmd_ctx, target);
if (connection->priv) {
free(connection->priv);
@ -1039,9 +1042,9 @@ static int gdb_connection_closed(struct connection *connection)
target_unregister_event_callback(gdb_target_callback_event_handler, connection);
target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_END);
target_call_event_callbacks(target, TARGET_EVENT_GDB_END);
target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_DETACH);
target_call_event_callbacks(target, TARGET_EVENT_GDB_DETACH);
return ERROR_OK;
}
@ -2583,7 +2586,6 @@ static int gdb_v_packet(struct connection *connection,
char const *packet, int packet_size)
{
struct gdb_connection *gdb_connection = connection->priv;
struct gdb_service *gdb_service = connection->service->priv;
int result;
struct target *target = get_target_from_connection(connection);
@ -2629,18 +2631,18 @@ static int gdb_v_packet(struct connection *connection,
flash_set_dirty();
/* perform any target specific operations before the erase */
target_call_event_callbacks(gdb_service->target,
target_call_event_callbacks(target,
TARGET_EVENT_GDB_FLASH_ERASE_START);
/* vFlashErase:addr,length messages require region start and
* end to be "block" aligned ... if padding is ever needed,
* GDB will have become dangerously confused.
*/
result = flash_erase_address_range(gdb_service->target,
false, addr, length);
result = flash_erase_address_range(target, false, addr,
length);
/* perform any target specific operations after the erase */
target_call_event_callbacks(gdb_service->target,
target_call_event_callbacks(target,
TARGET_EVENT_GDB_FLASH_ERASE_END);
/* perform erase */
@ -2695,10 +2697,12 @@ static int gdb_v_packet(struct connection *connection,
/* process the flashing buffer. No need to erase as GDB
* always issues a vFlashErase first. */
target_call_event_callbacks(gdb_service->target,
target_call_event_callbacks(target,
TARGET_EVENT_GDB_FLASH_WRITE_START);
result = flash_write(gdb_service->target, gdb_connection->vflash_image, &written, 0);
target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_FLASH_WRITE_END);
result = flash_write(target, gdb_connection->vflash_image,
&written, 0);
target_call_event_callbacks(target,
TARGET_EVENT_GDB_FLASH_WRITE_END);
if (result != ERROR_OK) {
if (result == ERROR_FLASH_DST_OUT_OF_BANK)
gdb_put_packet(connection, "E.memtype", 9);
@ -2722,9 +2726,8 @@ static int gdb_v_packet(struct connection *connection,
static int gdb_detach(struct connection *connection)
{
struct gdb_service *gdb_service = connection->service->priv;
target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_DETACH);
target_call_event_callbacks(get_target_from_connection(connection),
TARGET_EVENT_GDB_DETACH);
return gdb_put_packet(connection, "OK", 2);
}
@ -2803,14 +2806,15 @@ static int gdb_input_inner(struct connection *connection)
/* Do not allocate this on the stack */
static char gdb_packet_buffer[GDB_BUFFER_SIZE];
struct gdb_service *gdb_service = connection->service->priv;
struct target *target = gdb_service->target;
struct target *target;
char const *packet = gdb_packet_buffer;
int packet_size;
int retval;
struct gdb_connection *gdb_con = connection->priv;
static int extended_protocol;
target = get_target_from_connection(connection);
/* drain input buffer. If one of the packets fail, then an error
* packet is replied, if applicable.
*
@ -2980,8 +2984,8 @@ static int gdb_input_inner(struct connection *connection)
break;
case 'R':
/* handle extended restart packet */
breakpoint_clear_target(gdb_service->target);
watchpoint_clear_target(gdb_service->target);
breakpoint_clear_target(target);
watchpoint_clear_target(target);
command_run_linef(connection->cmd_ctx, "ocd_gdb_restart %s",
target_name(target));
/* set connection as attached after reset */

1
src/server/telnet_server.c
View File

@ -222,7 +222,6 @@ static int telnet_new_connection(struct connection *connection)
telnet_connection->closed = 0;
telnet_connection->line_size = 0;
telnet_connection->line_cursor = 0;
telnet_connection->option_size = 0;
telnet_connection->prompt = strdup("> ");
telnet_connection->state = TELNET_STATE_DATA;

7
src/server/telnet_server.h
View File

@ -27,11 +27,10 @@
#include <server/server.h>
#define TELNET_BUFFER_SIZE (1024)
#define TELNET_BUFFER_SIZE (10*1024)
#define TELNET_OPTION_MAX_SIZE (128)
#define TELNET_LINE_HISTORY_SIZE (128)
#define TELNET_LINE_MAX_SIZE (256)
#define TELNET_LINE_MAX_SIZE (10*256)
enum telnet_states {
TELNET_STATE_DATA,
@ -51,8 +50,6 @@ struct telnet_connection {
char line[TELNET_LINE_MAX_SIZE];
int line_size;
int line_cursor;
char option[TELNET_OPTION_MAX_SIZE];
int option_size;
char last_escape;
char *history[TELNET_LINE_HISTORY_SIZE];
int next_history;

2
src/svf/svf.c
View File

@ -661,11 +661,13 @@ static int svf_read_command_from_file(FILE *fd)
if (svf_getline(&svf_read_line, &svf_read_line_size, svf_fd) <= 0)
return ERROR_FAIL;
i = -1;
/* fallthrough */
case '\r':
slash = 0;
/* Don't save '\r' and '\n' if no data is parsed */
if (!cmd_pos)
break;
/* fallthrough */
default:
/* The parsing code currently expects a space
* before parentheses -- "TDI (123)". Also a

5
src/target/Makefile.am
View File

@ -19,6 +19,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
$(AVR32_SRC) \
$(MIPS32_SRC) \
$(NDS32_SRC) \
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
$(RISCV_SRC) \
%D%/avrt.c \
@ -125,6 +126,9 @@ NDS32_SRC = \
%D%/nds32_v3m.c \
%D%/nds32_aice.c
STM8_SRC = \
%D%/stm8.c
INTEL_IA32_SRC = \
%D%/quark_x10xx.c \
%D%/quark_d20xx.c \
@ -213,6 +217,7 @@ RISCV_SRC = \
%D%/nds32_v3.h \
%D%/nds32_v3m.h \
%D%/nds32_aice.h \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
%D%/arm_cti.h

5
src/target/adi_v5_swd.c
View File

@ -427,7 +427,10 @@ static int swd_init(struct command_context *ctx)
/* First connect after init is not reconnecting. */
dap->do_reconnect = false;
return swd_connect(dap);
int retval = swd_connect(dap);
if (retval != ERROR_OK)
LOG_ERROR("SWD connect failed");
return retval;
}
static struct transport swd_transport = {

3
src/target/arm.h
View File

@ -157,6 +157,9 @@ struct arm {
int (*setup_semihosting)(struct target *target, int enable);
/** Semihosting command line. */
char *semihosting_cmdline;
/** Backpointer to the target. */
struct target *target;

8
src/target/arm_adi_v5.c
View File

@ -346,8 +346,10 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz
case 4:
outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
/* fallthrough */
case 2:
outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
/* fallthrough */
case 1:
outvalue |= (uint32_t)*buffer++ << 8 * (address++ & 3);
}
@ -509,8 +511,10 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint
case 4:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
/* fallthrough */
case 2:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
/* fallthrough */
case 1:
*buffer++ = *read_ptr >> 8 * (3 - (address++ & 3));
}
@ -519,8 +523,10 @@ static int mem_ap_read(struct adiv5_ap *ap, uint8_t *buffer, uint32_t size, uint
case 4:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
*buffer++ = *read_ptr >> 8 * (address++ & 3);
/* fallthrough */
case 2:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
/* fallthrough */
case 1:
*buffer++ = *read_ptr >> 8 * (address++ & 3);
}
@ -1053,7 +1059,7 @@ static int dap_rom_display(struct command_context *cmd_ctx,
int retval;
uint64_t pid;
uint32_t cid;
char tabs[7] = "";
char tabs[16] = "";
if (depth > 16) {
command_print(cmd_ctx, "\tTables too deep");

1
src/target/arm_disassembler.c
View File

@ -3299,6 +3299,7 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
case 0x10:
case 0x12:
is_signed = true;
/* fallthrough */
case 0x18:
case 0x1a:
/* signed/unsigned saturated add */

2
src/target/arm_semihosting.c
View File

@ -465,7 +465,7 @@ static int do_semihosting(struct target *target)
else {
uint32_t a = target_buffer_get_u32(target, params+0);
uint32_t l = target_buffer_get_u32(target, params+4);
char *arg = "foobar";
char *arg = arm->semihosting_cmdline != NULL ? arm->semihosting_cmdline : "";
uint32_t s = strlen(arg) + 1;
if (l < s)
arm->semihosting_result = -1;

43
src/target/armv4_5.c
View File

@ -1091,6 +1091,42 @@ COMMAND_HANDLER(handle_arm_semihosting_fileio_command)
return ERROR_OK;
}
COMMAND_HANDLER(handle_arm_semihosting_cmdline)
{
struct target *target = get_current_target(CMD_CTX);
unsigned int i;
if (target == NULL) {
LOG_ERROR("No target selected");
return ERROR_FAIL;
}
struct arm *arm = target_to_arm(target);
if (!is_arm(arm)) {
command_print(CMD_CTX, "current target isn't an ARM");
return ERROR_FAIL;
}
if (!arm->setup_semihosting) {
command_print(CMD_CTX, "semihosting not supported for current target");
return ERROR_FAIL;
}
free(arm->semihosting_cmdline);
arm->semihosting_cmdline = CMD_ARGC > 0 ? strdup(CMD_ARGV[0]) : NULL;
for (i = 1; i < CMD_ARGC; i++) {
char *cmdline = alloc_printf("%s %s", arm->semihosting_cmdline, CMD_ARGV[i]);
if (cmdline == NULL)
break;
free(arm->semihosting_cmdline);
arm->semihosting_cmdline = cmdline;
}
return ERROR_OK;
}
static const struct command_registration arm_exec_command_handlers[] = {
{
.name = "reg",
@ -1133,6 +1169,13 @@ static const struct command_registration arm_exec_command_handlers[] = {
.usage = "['enable'|'disable']",
.help = "activate support for semihosting operations",
},
{
"semihosting_cmdline",
.handler = handle_arm_semihosting_cmdline,
.mode = COMMAND_EXEC,
.usage = "arguments",
.help = "command line arguments to be passed to program",
},
{
"semihosting_fileio",
.handler = handle_arm_semihosting_fileio_command,

2
src/target/armv7a.c
View File

@ -355,7 +355,7 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
break;
case 7:
LOG_INFO("inner: Write-Back, no Write-Allocate");
break;
default:
LOG_INFO("inner: %" PRIx32 " ???", INNER);
}

2
src/target/armv7m.h
View File

@ -174,7 +174,7 @@ target_to_armv7m(struct target *target)
return container_of(target->arch_info, struct armv7m_common, arm);
}
static inline bool is_armv7m(struct armv7m_common *armv7m)
static inline bool is_armv7m(const struct armv7m_common *armv7m)
{
return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
}

14
src/target/cortex_m.c
View File

@ -168,12 +168,8 @@ static int cortex_m_single_step_core(struct target *target)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
uint32_t dhcsr_save;
int retval;
/* backup dhcsr reg */
dhcsr_save = cortex_m->dcb_dhcsr;
/* Mask interrupts before clearing halt, if done already. This avoids
* Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
* HALT can put the core into an unknown state.
@ -191,7 +187,6 @@ static int cortex_m_single_step_core(struct target *target)
LOG_DEBUG(" ");
/* restore dhcsr reg */
cortex_m->dcb_dhcsr = dhcsr_save;
cortex_m_clear_halt(target);
return ERROR_OK;
@ -242,7 +237,7 @@ static int cortex_m_endreset_event(struct target *target)
if (retval != ERROR_OK)
return retval;
if (!(cortex_m->dcb_dhcsr & C_DEBUGEN)) {
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
if (retval != ERROR_OK)
return retval;
}
@ -1005,12 +1000,12 @@ static int cortex_m_assert_reset(struct target *target)
/* Store important errors instead of failing and proceed to reset assert */
if (retval != ERROR_OK || !(cortex_m->dcb_dhcsr & C_DEBUGEN))
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_DEBUGEN);
retval = cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP | C_MASKINTS);
/* If the processor is sleeping in a WFI or WFE instruction, the
* C_HALT bit must be asserted to regain control */
if (retval == ERROR_OK && (cortex_m->dcb_dhcsr & S_SLEEP))
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
retval = cortex_m_write_debug_halt_mask(target, C_HALT, 0);
mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
/* Ignore less important errors */
@ -1018,8 +1013,7 @@ static int cortex_m_assert_reset(struct target *target)
if (!target->reset_halt) {
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m->dcb_dhcsr & C_MASKINTS)
mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DHCSR,
DBGKEY | C_DEBUGEN | C_HALT);
cortex_m_write_debug_halt_mask(target, 0, C_MASKINTS);
/* clear any debug flags before resuming */
cortex_m_clear_halt(target);

2
src/target/nds32_cmd.c
View File

@ -816,7 +816,7 @@ static int jim_nds32_bulk_read(Jim_Interp *interp, int argc, Jim_Obj * const *ar
uint32_t *data = malloc(count * sizeof(uint32_t));
int result;
result = target_read_buffer(target, address, count * 4, (uint8_t *)data);
char data_str[11];
char data_str[12];
jim_wide i;
Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));

1
src/target/openrisc/jsp_server.c
View File

@ -88,7 +88,6 @@ static int jsp_new_connection(struct connection *connection)
telnet_connection->closed = 0;
telnet_connection->line_size = 0;
telnet_connection->line_cursor = 0;
telnet_connection->option_size = 0;
telnet_connection->state = TELNET_STATE_DATA;
/* negotiate telnet options */

4
src/target/register.h
View File

@ -114,9 +114,9 @@ struct reg_data_type {
};
struct reg {
/** Canonical name of the register. */
/* Canonical name of the register. */
const char *name;
/** Number that gdb uses to access this register. */
/* Number that gdb uses to access this register. */
uint32_t number;
/* TODO. This should probably be const. */
struct reg_feature *feature;

2219
src/target/stm8.c Normal file
View File

File diff suppressed because it is too large Load Diff

75
src/target/stm8.h Normal file
View File

@ -0,0 +1,75 @@
/*
OpenOCD STM8 target driver
Copyright (C) 2017 Ake Rehnman
ake.rehnman(at)gmail.com
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef OPENOCD_TARGET_STM8_H
#define OPENOCD_TARGET_STM8_H
struct target;
#define STM8_COMMON_MAGIC 0x53544D38
#define STM8_NUM_CORE_REGS 6
struct stm8_common {
uint32_t common_magic;
void *arch_info;
struct reg_cache *core_cache;
uint32_t core_regs[STM8_NUM_CORE_REGS];
/* working area for fastdata access */
struct working_area *fast_data_area;
bool swim_configured;
bool bp_scanned;
uint8_t num_hw_bpoints;
uint8_t num_hw_bpoints_avail;
struct stm8_comparator *hw_break_list;
uint32_t blocksize;
uint32_t flashstart;
uint32_t flashend;
uint32_t eepromstart;
uint32_t eepromend;
uint32_t optionstart;
uint32_t optionend;
bool enable_step_irq;
bool enable_stm8l;
uint32_t flash_cr2;
uint32_t flash_ncr2;
uint32_t flash_iapsr;
uint32_t flash_dukr;
uint32_t flash_pukr;
/* cc value used for interrupt flags restore */
uint32_t cc;
bool cc_valid;
/* register cache to processor synchronization */
int (*read_core_reg)(struct target *target, unsigned int num);
int (*write_core_reg)(struct target *target, unsigned int num);
};
static inline struct stm8_common *
target_to_stm8(struct target *target)
{
return target->arch_info;
}
const struct command_registration stm8_command_handlers[];
#endif /* OPENOCD_TARGET_STM8_H */

8
src/target/target.c
View File

@ -105,6 +105,7 @@ extern struct target_type nds32_v3m_target;
extern struct target_type or1k_target;
extern struct target_type quark_x10xx_target;
extern struct target_type quark_d20xx_target;
extern struct target_type stm8_target;
extern struct target_type riscv_target;
static struct target_type *target_types[] = {
@ -137,6 +138,7 @@ static struct target_type *target_types[] = {
&or1k_target,
&quark_x10xx_target,
&quark_d20xx_target,
&stm8_target,
&riscv_target,
#if BUILD_TARGET64
&aarch64_target,
@ -204,10 +206,6 @@ static const Jim_Nvp nvp_target_event[] = {
{ .value = TARGET_EVENT_RESET_ASSERT_POST, .name = "reset-assert-post" },
{ .value = TARGET_EVENT_RESET_DEASSERT_PRE, .name = "reset-deassert-pre" },
{ .value = TARGET_EVENT_RESET_DEASSERT_POST, .name = "reset-deassert-post" },
{ .value = TARGET_EVENT_RESET_HALT_PRE, .name = "reset-halt-pre" },
{ .value = TARGET_EVENT_RESET_HALT_POST, .name = "reset-halt-post" },
{ .value = TARGET_EVENT_RESET_WAIT_PRE, .name = "reset-wait-pre" },
{ .value = TARGET_EVENT_RESET_WAIT_POST, .name = "reset-wait-post" },
{ .value = TARGET_EVENT_RESET_INIT, .name = "reset-init" },
{ .value = TARGET_EVENT_RESET_END, .name = "reset-end" },
@ -3699,7 +3697,7 @@ COMMAND_HANDLER(handle_bp_command)
addr = 0;
return handle_bp_command_set(CMD_CTX, addr, asid, length, hw);
}
/* fallthrough */
case 4:
hw = BKPT_HARD;
COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr);

4
src/target/target.h
View File

@ -253,10 +253,6 @@ enum target_event {
TARGET_EVENT_RESET_ASSERT_POST,
TARGET_EVENT_RESET_DEASSERT_PRE,
TARGET_EVENT_RESET_DEASSERT_POST,
TARGET_EVENT_RESET_HALT_PRE,
TARGET_EVENT_RESET_HALT_POST,
TARGET_EVENT_RESET_WAIT_PRE,
TARGET_EVENT_RESET_WAIT_POST,
TARGET_EVENT_RESET_INIT,
TARGET_EVENT_RESET_END,

7
tcl/board/gti/espressobin.cfg Normal file
View File

@ -0,0 +1,7 @@
# config for ESPRESSObin from
# Globalscale Technologies Inc.
# srst is isolated through missing resistor
reset_config trst_only
source [find target/marvell/88f3720.cfg]

2
tcl/board/openrd.cfg
View File

@ -3,6 +3,8 @@
source [find interface/ftdi/openrd.cfg]
source [find target/feroceon.cfg]
adapter_khz 2000
$_TARGETNAME configure \
-work-area-phys 0x10000000 \
-work-area-size 65536 \

2
tcl/board/st_nucleo_f0.cfg
View File

@ -6,7 +6,7 @@
# STM32F091RC
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260944
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/st_nucleo_f103rb.cfg
View File

@ -1,7 +1,7 @@
# This is an ST NUCLEO F103RB board with a single STM32F103RBT6 chip.
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF259875
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/st_nucleo_f3.cfg
View File

@ -1,7 +1,7 @@
# This is an ST NUCLEO F334R8 board with a single STM32F334R8T6 chip.
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260004
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/st_nucleo_f4.cfg
View File

@ -4,7 +4,7 @@
# STM32F411RET6
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260320
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

10
tcl/board/st_nucleo_h743zi.cfg Normal file
View File

@ -0,0 +1,10 @@
# This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip.
# http://www.st.com/en/evaluation-tools/nucleo-h743zi.html
source [find interface/stlink-v2-1.cfg]
transport select hla_swd
source [find target/stm32h7x_dual_bank.cfg]
reset_config srst_only

2
tcl/board/st_nucleo_l1.cfg
View File

@ -1,7 +1,7 @@
# This is an ST NUCLEO L152RE board with a single STM32L152RET6 chip.
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF260002
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/st_nucleo_l476rg.cfg
View File

@ -1,7 +1,7 @@
# This is a ST NUCLEO L476RG board with a single STM32L476RGT6 chip.
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1847/PF261636
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm320518_eval_stlink.cfg
View File

@ -4,7 +4,7 @@
#
# This is for using the onboard STLINK/V2
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm3220g_eval_stlink.cfg
View File

@ -4,7 +4,7 @@
#
# This is for using the onboard STLINK/V2
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm3241g_eval_stlink.cfg
View File

@ -4,7 +4,7 @@
#
# This is for using the onboard STLINK/V2
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32429i_eval_stlink.cfg
View File

@ -4,7 +4,7 @@
#
# This is for using the onboard STLINK/V2
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32439i_eval_stlink.cfg
View File

@ -4,7 +4,7 @@
#
# This is for using the onboard STLINK/V2
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32f0discovery.cfg
View File

@ -1,7 +1,7 @@
# This is an STM32F0 discovery board with a single STM32F051R8T6 chip.
# http://www.st.com/internet/evalboard/product/253215.jsp
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32f3discovery.cfg
View File

@ -1,7 +1,7 @@
# This is an STM32F3 discovery board with a single STM32F303VCT6 chip.
# http://www.st.com/internet/evalboard/product/254044.jsp
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32f429disc1.cfg
View File

@ -3,7 +3,7 @@
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
#
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32f429discovery.cfg
View File

@ -3,7 +3,7 @@
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/PF259090
#
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32f469discovery.cfg
View File

@ -3,7 +3,7 @@
# http://www.st.com/web/catalog/tools/FM116/CL1620/SC959/SS1532/LN1848/PF262395
#
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32f4discovery.cfg
View File

@ -1,7 +1,7 @@
# This is an STM32F4 discovery board with a single STM32F407VGT6 chip.
# http://www.st.com/internet/evalboard/product/252419.jsp
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32f7discovery.cfg
View File

@ -2,7 +2,7 @@
# http://www.st.com/web/catalog/tools/FM116/SC959/SS1532/LN1848/PF261641
# This is for using the onboard STLINK/V2-1
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

13
tcl/board/stm32h7x3i_eval.cfg Normal file
View File

@ -0,0 +1,13 @@
# STM32H7[4|5]3I-EVAL: this is for the H7 eval boards.
# This is an ST EVAL-H743XI board with single STM32H743XI chip.
# http://www.st.com/en/evaluation-tools/stm32h743i-eval.html
# This is an ST EVAL-H753XI board with single STM32H753XI chip.
# http://www.st.com/en/evaluation-tools/stm32h753i-eval.html
source [find interface/stlink-v2-1.cfg]
transport select hla_swd
source [find target/stm32h7x_dual_bank.cfg]
reset_config srst_only

2
tcl/board/stm32l0discovery.cfg
View File

@ -1,7 +1,7 @@
# This is an STM32L053 discovery board with a single STM32L053 chip.
# http://www.st.com/web/en/catalog/tools/PF260319
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32l4discovery.cfg
View File

@ -4,7 +4,7 @@
# an stlink-v2-1 interface.
# This is for STM32L4 boards that are connected via stlink-v2-1.
source [find interface/stlink-v2-1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32ldiscovery.cfg
View File

@ -1,7 +1,7 @@
# This is an STM32L discovery board with a single STM32L152RBT6 chip.
# http://www.st.com/internet/evalboard/product/250990.jsp
source [find interface/stlink-v2.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

2
tcl/board/stm32vldiscovery.cfg
View File

@ -1,7 +1,7 @@
# This is an STM32VL discovery board with a single STM32F100RB chip.
# http://www.st.com/internet/evalboard/product/250863.jsp
source [find interface/stlink-v1.cfg]
source [find interface/stlink.cfg]
transport select hla_swd

28
tcl/board/tocoding_poplar.cfg Normal file
View File

@ -0,0 +1,28 @@
#
# board configuration for Tocoding Poplar
#
# board does not feature anything but JTAG
transport select jtag
adapter_khz 10000
# SRST-only reset configuration
reset_config srst_only srst_push_pull
source [find tcl/target/hi3798.cfg]
# halt the cores when gdb attaches
${_TARGETNAME}0 configure -event gdb-attach "halt"
# make sure the default target is the boot core
targets ${_TARGETNAME}0
proc core_up { args } {
global _TARGETNAME
# examine remaining cores
foreach _core [set args] {
${_TARGETNAME}$_core arp_examine
}
}

2
tcl/board/tp-link_tl-mr3020.cfg
View File

@ -42,3 +42,5 @@ $_TARGETNAME configure -event reset-init {
set ram_boot_address 0xa0000000
$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0

160
tcl/board/tp-link_wdr4300.cfg Normal file
View File

@ -0,0 +1,160 @@
source [find target/atheros_ar9344.cfg]
reset_config trst_only separate
proc ar9344_40mhz_pll_init {} {
# QCA_PLL_SRIF_CPU_DPLL2_REG
mww 0xb81161C4 0x13210f00
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x03000000
# QCA_PLL_SRIF_DDR_DPLL2_REG
mww 0xb8116244 0x13210f00
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x03000000
# QCA_PLL_SRIF_BB_DPLL_BASE_REG
mww 0xb8116188 0x03000000
# QCA_PLL_CPU_DDR_CLK_CTRL_REG
mww 0xb8050008 0x0130001C
mww 0xb8050008 0x0130001C
mww 0xb8050008 0x0130001C
# QCA_PLL_CPU_PLL_CFG_REG
mww 0xb8050000 0x40021380
# QCA_PLL_DDR_PLL_CFG_REG
mww 0xb8050004 0x40815800
# QCA_PLL_CPU_DDR_CLK_CTRL_REG
mww 0xb8050008 0x0130801C
# QCA_PLL_SRIF_CPU_DPLL2_REG
mww 0xb81161C4 0x10810F00
mww 0xb81161C0 0x41C00000
# QCA_PLL_SRIF_CPU_DPLL2_REG
mww 0xb81161C4 0xD0810F00
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x03000000
# QCA_PLL_SRIF_CPU_DPLL2_REG
mww 0xb81161C4 0xD0800F00
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x03000000
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x43000000
# QCA_PLL_SRIF_CPU_DPLL3_REG
mww 0xb81161C8 0x030003E8
# QCA_PLL_SRIF_DDR_DPLL2_REG
mww 0xb8116244 0x10810F00
mww 0xb8116240 0x41680000
# QCA_PLL_SRIF_DDR_DPLL2_REG
mww 0xb8116244 0xD0810F00
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x03000000
# QCA_PLL_SRIF_DDR_DPLL2_REG
mww 0xb8116244 0xD0800F00
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x03000000
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x43000000
# QCA_PLL_SRIF_DDR_DPLL3_REG
mww 0xb8116248 0x03000718
# QCA_PLL_CPU_DDR_CLK_CTRL_REG
mww 0xb8050008 0x01308018
mww 0xb8050008 0x01308010
mww 0xb8050008 0x01308000
# QCA_PLL_DDR_PLL_DITHER_REG
mww 0xb8050044 0x78180200
# QCA_PLL_CPU_PLL_DITHER_REG
mww 0xb8050048 0x41C00000
}
proc ar9344_ddr_init {} {
# QCA_DDR_CTRL_CFG_REG
mww 0xb8000108 0x40
# QCA_DDR_RD_DATA_THIS_CYCLE_REG
mww 0xb8000018 0xFF
# QCA_DDR_BURST_REG
mww 0xb80000C4 0x74444444
# QCA_DDR_BURST2_REG
mww 0xb80000C8 0x0222
# QCA_AHB_MASTER_TOUT_MAX_REG
mww 0xb80000CC 0xFFFFF
# QCA_DDR_CFG_REG
mww 0xb8000000 0xC7D48CD0
# QCA_DDR_CFG2_REG
mww 0xb8000004 0x9DD0E6A8
# QCA_DDR_DDR2_CFG_REG
mww 0xb80000B8 0x0E59
# QCA_DDR_CFG2_REG
mww 0xb8000004 0x9DD0E6A8
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x08
mww 0xb8000010 0x08
mww 0xb8000010 0x10
mww 0xb8000010 0x20
# QCA_DDR_EMR_REG
mww 0xb800000C 0x02
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x02
# QCA_DDR_MR_REG
mww 0xb8000008 0x0133
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x1
mww 0xb8000010 0x8
mww 0xb8000010 0x8
mww 0xb8000010 0x4
mww 0xb8000010 0x4
# QCA_DDR_MR_REG
mww 0xb8000008 0x33
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x1
# QCA_DDR_EMR_REG
mww 0xb800000C 0x0382
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x2
# QCA_DDR_EMR_REG
mww 0xb800000C 0x0402
# QCA_DDR_CTRL_REG
mww 0xb8000010 0x2
# QCA_DDR_REFRESH_REG
mww 0xb8000014 0x4270
# QCA_DDR_TAP_CTRL_0_REG
mww 0xb800001C 0x0e
# QCA_DDR_TAP_CTRL_1_REG
mww 0xb8000020 0x0e
# QCA_DDR_TAP_CTRL_2_REG
mww 0xb8000024 0x0e
# QCA_DDR_TAP_CTRL_3_REG
mww 0xb8000028 0x0e
}
$_TARGETNAME configure -event reset-init {
# mww 0xb806001c 0x1000000
ar9344_40mhz_pll_init
sleep 100
# flash remap
# SPI_CONTROL_ADDR
mww 0xbF000004 0x43
ar9344_ddr_init
sleep 100
}
set ram_boot_address 0xa0000000
$_TARGETNAME configure -work-area-phys 0x1d000000 -work-area-size 0x1000
flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0

13
tcl/interface/ftdi/minimodule.cfg
View File

@ -4,14 +4,13 @@
# http://www.ftdichip.com/Support/Documents/DataSheets/Modules/DS_FT2232H_Mini_Module.pdf
#
echo "WARNING!"
echo "This file was not tested with real interface, it is based on code in ft2232.c."
echo "Please report your experience with this file to openocd-devel mailing list,"
echo "so it could be marked as working or fixed."
interface ftdi
ftdi_device_desc "FT2232H MiniModule"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0018 0x05fb
ftdi_layout_signal nSRST -data 0x0020
# Every pin set as high impedance except TCK, TDI, TDO and TMS
ftdi_layout_init 0x0008 0x000b
# nSRST defined on pin CN2-13 of the MiniModule (pin ADBUS5 [AD5] on the FT2232H chip)
# This choice is arbitrary. Use other GPIO pin if desired.
ftdi_layout_signal nSRST -data 0x0020 -oe 0x0020

9
tcl/interface/ftdi/openrd.cfg
View File

@ -4,15 +4,10 @@
# http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp
#
echo "WARNING!"
echo "This file was not tested with real interface, it is based on code in ft2232.c."
echo "Please report your experience with this file to openocd-devel mailing list,"
echo "so it could be marked as working or fixed."
interface ftdi
ftdi_device_desc "OpenRD JTAGKey FT2232D"
ftdi_device_desc "OpenRD JTAGKey FT2232D B"
ftdi_vid_pid 0x0403 0x9e90
ftdi_channel 1
ftdi_channel 0
ftdi_layout_init 0x0608 0x0f1b
ftdi_layout_signal nTRST -data 0x0200

2
tcl/interface/ftdi/sheevaplug.cfg
View File

@ -7,7 +7,7 @@
interface ftdi
ftdi_device_desc "SheevaPlug JTAGKey FT2232D B"
ftdi_vid_pid 0x9e88 0x9e8f
ftdi_channel 1
ftdi_channel 0
ftdi_layout_init 0x0608 0x0f1b
ftdi_layout_signal nTRST -data 0x0200

11
tcl/interface/stlink-v1.cfg
View File

@ -1,9 +1,2 @@
#
# STMicroelectronics ST-LINK/V1 in-circuit debugger/programmer
#
interface hla
hla_layout stlink
hla_device_desc "ST-LINK/V1"
hla_vid_pid 0x0483 0x3744
echo "WARNING: interface/stlink-v1.cfg is deprecated, please switch to interface/stlink.cfg"
source [find interface/stlink.cfg]

18
tcl/interface/stlink-v2-1.cfg
View File

@ -1,16 +1,2 @@
#
# STMicroelectronics ST-LINK/V2-1 in-circuit debugger/programmer
#
interface hla
hla_layout stlink
hla_device_desc "ST-LINK/V2-1"
hla_vid_pid 0x0483 0x374b
# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
# number reset issues.
# eg.
#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
echo "WARNING: interface/stlink-v2-1.cfg is deprecated, please switch to interface/stlink.cfg"
source [find interface/stlink.cfg]

18
tcl/interface/stlink-v2.cfg
View File

@ -1,16 +1,2 @@
#
# STMicroelectronics ST-LINK/V2 in-circuit debugger/programmer
#
interface hla
hla_layout stlink
hla_device_desc "ST-LINK/V2"
hla_vid_pid 0x0483 0x3748
# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
# number reset issues.
# eg.
#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"
echo "WARNING: interface/stlink-v2.cfg is deprecated, please switch to interface/stlink.cfg"
source [find interface/stlink.cfg]

17
tcl/interface/stlink.cfg Normal file
View File

@ -0,0 +1,17 @@
#
# STMicroelectronics ST-LINK/V1, ST-LINK/V2, ST-LINK/V2-1 in-circuit
# debugger/programmer
#
interface hla
hla_layout stlink
hla_device_desc "ST-LINK"
hla_vid_pid 0x0483 0x3744 0x0483 0x3748 0x0483 0x374b
# Optionally specify the serial number of ST-LINK/V2 usb device. ST-LINK/V2
# devices seem to have serial numbers with unreadable characters. ST-LINK/V2
# firmware version >= V2.J21.S4 recommended to avoid issues with adapter serial
# number reset issues.
# eg.
#hla_serial "\xaa\xbc\x6e\x06\x50\x75\xff\x55\x17\x42\x19\x3f"

39
tcl/target/atheros_ar9344.cfg Normal file
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@ -0,0 +1,39 @@
if { [info exists CHIPNAME] } {
set _CHIPNAME $_CHIPNAME
} else {
set _CHIPNAME ar9344
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x00000001
}
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
proc test_ar9344_uart0_tx {} {
echo "configuring uart0.."
mww 0xb802000c 0x87
mww 0xb8020000 0x15
mww 0xb8020004 0
mww 0xb802000c 7
mww 0xb8020004 0
echo "send message: hallo world"
mww 0xb8020000 0x68
mww 0xb8020000 0x65
mww 0xb8020000 0x6c
mww 0xb8020000 0x6c
mww 0xb8020000 0x6f
mww 0xb8020000 0x20
mww 0xb8020000 0x77
mww 0xb8020000 0x6f
mww 0xb8020000 0x72
mww 0xb8020000 0x6c
mww 0xb8020000 0x64
mww 0xb8020000 0x0a
}

49
tcl/target/hi3798.cfg Normal file
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# Hisilicon Hi3798 Target
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME hi3798
}
#
# Main DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x5ba00477
}
# declare the one JTAG tap to access the DAP
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
# declare the 4 main application cores
set _TARGETNAME $_CHIPNAME.cpu
set _smp_command ""
set $_TARGETNAME.cti(0) 0x80020000
set $_TARGETNAME.cti(1) 0x80120000
set $_TARGETNAME.cti(2) 0x80220000
set $_TARGETNAME.cti(3) 0x80320000
set _cores 4
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
set _command "target create ${_TARGETNAME}$_core aarch64 \
-chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"
if { $_core != 0 } {
# non-boot core examination may fail
#set _command "$_command -defer-examine"
set _smp_command "$_smp_command ${_TARGETNAME}$_core"
} else {
# uncomment when "hawt" rtos is merged
# set _command "$_command -rtos hawt"
set _smp_command "target smp ${_TARGETNAME}$_core"
}
eval $_command
}
eval $_smp_command

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