swd: Convert API to asynchronous
Change-Id: I859568dbb2ad4e92411980751c3f747bd70638b8 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1959 Tested-by: jenkins Reviewed-by: Andrey Yurovsky <yurovsky@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Andreas Fritiofson
parent
2268b77142
commit
d2bb14e36a
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@ -479,8 +479,13 @@ static int cmsis_dap_cmd_DAP_Delay(uint16_t delay_us)
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}
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#endif
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static int cmsis_dap_swd_read_reg(uint8_t cmd, uint32_t *value)
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static int queued_retval;
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static void cmsis_dap_swd_read_reg(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value)
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{
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if (queued_retval != ERROR_OK)
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return;
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uint8_t *buffer = cmsis_dap_handle->packet_buffer;
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int retval;
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uint32_t val;
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@ -497,7 +502,8 @@ static int cmsis_dap_swd_read_reg(uint8_t cmd, uint32_t *value)
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/* TODO - need better response checking */
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if (retval != ERROR_OK || buffer[1] != 0x01) {
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LOG_ERROR("CMSIS-DAP: Read Error (0x%02" PRIx8 ")", buffer[2]);
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return buffer[2];
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queued_retval = buffer[2];
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return;
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}
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val = le_to_h_u32(&buffer[3]);
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@ -506,11 +512,14 @@ static int cmsis_dap_swd_read_reg(uint8_t cmd, uint32_t *value)
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if (value)
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*value = val;
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return retval;
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queued_retval = retval;
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}
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static int cmsis_dap_swd_write_reg(uint8_t cmd, uint32_t value)
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static void cmsis_dap_swd_write_reg(struct adiv5_dap *dap, uint8_t cmd, uint32_t value)
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{
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if (queued_retval != ERROR_OK)
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return;
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uint8_t *buffer = cmsis_dap_handle->packet_buffer;
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DEBUG_IO("CMSIS-DAP: Write Reg 0x%02" PRIx8 " 0x%08" PRIx32, cmd, value);
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@ -531,6 +540,13 @@ static int cmsis_dap_swd_write_reg(uint8_t cmd, uint32_t value)
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retval = buffer[2];
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}
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queued_retval = retval;
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}
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static int cmsis_dap_swd_run(struct adiv5_dap *dap)
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{
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int retval = queued_retval;
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queued_retval = ERROR_OK;
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return retval;
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}
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@ -994,9 +1010,10 @@ static const struct command_registration cmsis_dap_command_handlers[] = {
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};
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static const struct swd_driver cmsis_dap_swd_driver = {
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.init = cmsis_dap_swd_init,
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.read_reg = cmsis_dap_swd_read_reg,
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.write_reg = cmsis_dap_swd_write_reg,
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.init = cmsis_dap_swd_init,
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.read_reg = cmsis_dap_swd_read_reg,
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.write_reg = cmsis_dap_swd_write_reg,
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.run = cmsis_dap_swd_run,
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};
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const char *cmsis_dap_transport[] = {"cmsis-dap", NULL};
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@ -20,6 +20,8 @@
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#ifndef SWD_H
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#define SWD_H
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#include <target/arm_adi_v5.h>
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/* Bits in SWD command packets, written from host to target
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* first bit on the wire is START
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*/
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@ -53,51 +55,47 @@ static inline uint8_t swd_cmd(bool is_read, bool is_ap, uint8_t regnum)
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/* SWD_ACK_* bits are defined in <target/arm_adi_v5.h> */
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/*
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* FOR NOW ... SWD driver ops are synchronous and return ACK
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* status ... no queuing.
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*
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* Individual ops are request/response, and fast-fail permits much
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* better fault handling. Upper layers may queue if desired.
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*/
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struct swd_driver {
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/**
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* Initialize the debug link so it can perform
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* synchronous SWD operations.
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* Initialize the debug link so it can perform SWD operations.
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* @param trn value from WCR: how many clocks
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* to not drive the SWDIO line at certain points in
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* the SWD protocol (at least 1 clock).
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*
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* As an example, this would switch a dual-mode debug adapter
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* into SWD mode and out of JTAG mode.
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*
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* @return ERROR_OK on success, else a negative fault code.
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*
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* @return ERROR_OK on success, else a negative fault code.
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*/
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int (*init)(uint8_t trn);
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/**
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* Synchronous read of an AP or DP register.
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*
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* @param cmd with APnDP/RnW/addr/parity bits
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* @param where to store value to read from register
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*
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* @return SWD_ACK_* code for the transaction
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* or (negative) fault code
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*/
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int (*read_reg)(uint8_t cmd, uint32_t *value);
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/**
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* Queued read of an AP or DP register.
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*
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* @param dap The DAP controlled by the SWD link.
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* @param Command byte with APnDP/RnW/addr/parity bits
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* @param Where to store value to read from register
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*/
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void (*read_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t *value);
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/**
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* Synchronous write of an AP or DP register.
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*
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* @param cmd with APnDP/RnW/addr/parity bits
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* @param value to be written to the register
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*
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* @return SWD_ACK_* code for the transaction
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* or (negative) fault code
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*/
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int (*write_reg)(uint8_t cmd, uint32_t value);
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/**
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* Queued write of an AP or DP register.
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*
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* @param dap The DAP controlled by the SWD link.
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* @param Command byte with APnDP/RnW/addr/parity bits
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* @param Value to be written to the register
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*/
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void (*write_reg)(struct adiv5_dap *dap, uint8_t cmd, uint32_t value);
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/**
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* Execute any queued transactions and collect the result.
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*
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* @param dap The DAP controlled by the SWD link.
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* @return ERROR_OK on success, Ack response code on WAIT/FAULT
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* or negative error code on other kinds of failure.
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*/
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int (*run)(struct adiv5_dap *dap);
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/**
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* Configures data collection from the Single-wire
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@ -108,10 +106,10 @@ struct swd_driver {
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* is normally connected to a microcontroller's UART TX,
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* but which may instead be connected to SWO for use in
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* collecting ITM (and possibly ETM) trace data.
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*
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* @return ERROR_OK on success, else a negative fault code.
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*
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* @return ERROR_OK on success, else a negative fault code.
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*/
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int *(*trace)(bool swo);
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int *(*trace)(struct adiv5_dap *dap, bool swo);
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};
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int swd_init_reset(struct command_context *cmd_ctx);
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@ -61,8 +61,9 @@ static int cmsis_dap_clear_sticky_errors(struct adiv5_dap *dap)
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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return swd->write_reg(swd_cmd(false, false, DP_ABORT),
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STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
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swd->write_reg(dap, (CMSIS_CMD_DP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(DP_ABORT)),
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STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
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return ERROR_OK;
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}
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static int cmsis_dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
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@ -72,21 +73,20 @@ static int cmsis_dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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return swd->write_reg(swd_cmd(false, false, DP_ABORT),
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DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
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swd->write_reg(dap, (CMSIS_CMD_DP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(DP_ABORT)),
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DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
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return ERROR_OK;
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}
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static int cmsis_dap_queue_dp_read(struct adiv5_dap *dap, unsigned reg, uint32_t *data)
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{
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LOG_DEBUG("reg = %d", reg);
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int retval = jtag_interface->swd->read_reg(
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(CMSIS_CMD_DP | CMSIS_CMD_READ | CMSIS_CMD_A32(reg)), data);
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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if (retval != ERROR_OK)
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cmsis_dap_clear_sticky_errors(dap);
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return retval;
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swd->read_reg(dap, (CMSIS_CMD_DP | CMSIS_CMD_READ | CMSIS_CMD_A32(reg)), data);
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return ERROR_OK;
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}
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static int (cmsis_dap_queue_dp_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data)
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@ -100,13 +100,11 @@ static int (cmsis_dap_queue_dp_write)(struct adiv5_dap *dap, unsigned reg, uint3
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data &= ~CORUNDETECT;
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}
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int retval = jtag_interface->swd->write_reg(
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(CMSIS_CMD_DP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(reg)), data);
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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if (retval != ERROR_OK)
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cmsis_dap_clear_sticky_errors(dap);
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return retval;
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swd->write_reg(dap, (CMSIS_CMD_DP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(reg)), data);
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return ERROR_OK;
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}
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/** Select the AP register bank matching bits 7:4 of reg. */
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@ -120,58 +118,47 @@ static int cmsis_dap_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
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dap->ap_bank_value = select_ap_bank;
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select_ap_bank |= dap->ap_current;
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return cmsis_dap_queue_dp_write(dap, DP_SELECT, select_ap_bank);
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cmsis_dap_queue_dp_write(dap, DP_SELECT, select_ap_bank);
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return ERROR_OK;
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}
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static int (cmsis_dap_queue_ap_read)(struct adiv5_dap *dap, unsigned reg, uint32_t *data)
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{
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int retval = cmsis_dap_ap_q_bankselect(dap, reg);
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if (retval != ERROR_OK)
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return retval;
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cmsis_dap_ap_q_bankselect(dap, reg);
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LOG_DEBUG("reg = %d", reg);
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retval = jtag_interface->swd->read_reg(
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(CMSIS_CMD_AP | CMSIS_CMD_READ | CMSIS_CMD_A32(reg)), data);
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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if (retval != ERROR_OK)
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cmsis_dap_clear_sticky_errors(dap);
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swd->read_reg(dap, (CMSIS_CMD_AP | CMSIS_CMD_READ | CMSIS_CMD_A32(reg)), data);
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return retval;
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return ERROR_OK;
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}
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static int (cmsis_dap_queue_ap_write)(struct adiv5_dap *dap, unsigned reg, uint32_t data)
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{
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/* TODO: CSW_DBGSWENABLE (bit31) causes issues for some targets
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* disable until we find out why */
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if (reg == AP_REG_CSW)
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data &= ~CSW_DBGSWENABLE;
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int retval = cmsis_dap_ap_q_bankselect(dap, reg);
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if (retval != ERROR_OK)
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return retval;
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cmsis_dap_ap_q_bankselect(dap, reg);
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LOG_DEBUG("reg = %d, data = 0x%08" PRIx32, reg, data);
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retval = jtag_interface->swd->write_reg(
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(CMSIS_CMD_AP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(reg)), data);
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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if (retval != ERROR_OK)
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cmsis_dap_clear_sticky_errors(dap);
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swd->write_reg(dap, (CMSIS_CMD_AP | CMSIS_CMD_WRITE | CMSIS_CMD_A32(reg)), data);
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return retval;
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return ERROR_OK;
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}
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/** Executes all queued DAP operations. */
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static int cmsis_dap_run(struct adiv5_dap *dap)
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{
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LOG_DEBUG(" ");
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/* FIXME: for now the CMSIS-DAP interface hard-wires a zero-size queue. */
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int ret;
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uint32_t ctrlstat;
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/*
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Some debug dongles do more than asked for(e.g. EDBG from
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Atmel) behind the scene and issuing an AP write
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@ -182,23 +169,22 @@ static int cmsis_dap_run(struct adiv5_dap *dap)
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differently and not guarantee to be report those failures
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via status byte of the return USB packet from CMSIS-DAP, so
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we need to check CTRL/STAT and if that happens to clear it.
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Note that once the CMSIS-DAP SWD implementation starts queueing
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transfers this will cause loss of the transfers after the
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failed one. At least a warning is printed.
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*/
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ret = cmsis_dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
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if (ret != ERROR_OK) {
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LOG_ERROR("Failed to read CTRL/STAT register");
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return ret;
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}
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uint32_t ctrlstat;
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cmsis_dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
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if (ctrlstat & SSTICKYERR) {
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LOG_WARNING("SSTICKYERR was set, clearing it");
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ret = cmsis_dap_clear_sticky_errors(dap);
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if (ret != ERROR_OK) {
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LOG_ERROR("Failed to clear sticky errors");
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return ret;
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}
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}
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int retval = jtag_interface->swd->run(dap);
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return ret;
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if (retval == ERROR_OK && (ctrlstat & SSTICKYERR))
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LOG_WARNING("Adapter returned success despite SSTICKYERR being set.");
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if (retval != ERROR_OK || (ctrlstat & SSTICKYERR))
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cmsis_dap_clear_sticky_errors(dap);
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return retval;
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}
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const struct dap_ops cmsis_dap_ops = {
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@ -240,7 +226,7 @@ static const struct command_registration cmsis_dap_handlers[] = {
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static int cmsis_dap_select(struct command_context *ctx)
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{
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LOG_DEBUG(" ");
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LOG_DEBUG("CMSIS-ADI: cmsis_dap_select");
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int retval = register_commands(ctx, NULL, cmsis_dap_handlers);
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@ -57,179 +57,146 @@
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/* YUK! - but this is currently a global.... */
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extern struct jtag_interface *jtag_interface;
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static bool do_sync;
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static int swd_finish_read(struct adiv5_dap *dap)
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static void swd_finish_read(struct adiv5_dap *dap)
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{
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const struct swd_driver *swd = jtag_interface->swd;
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int retval = ERROR_OK;
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if (dap->last_read != NULL) {
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retval = swd->read_reg(swd_cmd(true, false, DP_RDBUFF), dap->last_read);
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swd->read_reg(dap, swd_cmd(true, false, DP_RDBUFF), dap->last_read);
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dap->last_read = NULL;
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}
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return retval;
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}
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static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
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static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
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uint32_t data);
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static int swd_clear_sticky_errors(struct adiv5_dap *dap)
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static void swd_clear_sticky_errors(struct adiv5_dap *dap)
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{
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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return swd->write_reg(swd_cmd(false, false, DP_ABORT),
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swd->write_reg(dap, swd_cmd(false, false, DP_ABORT),
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STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
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}
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static int swd_run_inner(struct adiv5_dap *dap)
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{
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const struct swd_driver *swd = jtag_interface->swd;
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int retval = swd->run(dap);
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if (retval != ERROR_OK) {
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/* fault response */
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swd_clear_sticky_errors(dap);
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}
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return retval;
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}
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static inline int check_sync(struct adiv5_dap *dap)
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{
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return do_sync ? swd_run_inner(dap) : ERROR_OK;
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}
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static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
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{
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const struct swd_driver *swd = jtag_interface->swd;
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assert(swd);
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return swd->write_reg(swd_cmd(false, false, DP_ABORT),
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swd->write_reg(dap, swd_cmd(false, false, DP_ABORT),
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DAPABORT | STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR);
|
||||
return check_sync(dap);
|
||||
}
|
||||
|
||||
/** Select the DP register bank matching bits 7:4 of reg. */
|
||||
static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
|
||||
static void swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned reg)
|
||||
{
|
||||
uint32_t select_dp_bank = (reg & 0x000000F0) >> 4;
|
||||
|
||||
if (reg == DP_SELECT)
|
||||
return ERROR_OK;
|
||||
return;
|
||||
|
||||
if (select_dp_bank == dap->dp_bank_value)
|
||||
return ERROR_OK;
|
||||
return;
|
||||
|
||||
dap->dp_bank_value = select_dp_bank;
|
||||
select_dp_bank |= dap->ap_current | dap->ap_bank_value;
|
||||
|
||||
return swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
|
||||
swd_queue_dp_write(dap, DP_SELECT, select_dp_bank);
|
||||
}
|
||||
|
||||
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
|
||||
uint32_t *data)
|
||||
{
|
||||
int retval;
|
||||
/* REVISIT status return vs ack ... */
|
||||
const struct swd_driver *swd = jtag_interface->swd;
|
||||
assert(swd);
|
||||
|
||||
retval = swd_queue_dp_bankselect(dap, reg);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
swd_queue_dp_bankselect(dap, reg);
|
||||
swd->read_reg(dap, swd_cmd(true, false, reg), data);
|
||||
|
||||
retval = swd->read_reg(swd_cmd(true, false, reg), data);
|
||||
|
||||
if (retval != ERROR_OK) {
|
||||
/* fault response */
|
||||
swd_clear_sticky_errors(dap);
|
||||
}
|
||||
|
||||
return retval;
|
||||
return check_sync(dap);
|
||||
}
|
||||
|
||||
|
||||
static int (swd_queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
|
||||
static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
|
||||
uint32_t data)
|
||||
{
|
||||
int retval;
|
||||
/* REVISIT status return vs ack ... */
|
||||
const struct swd_driver *swd = jtag_interface->swd;
|
||||
assert(swd);
|
||||
|
||||
retval = swd_finish_read(dap);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
swd_finish_read(dap);
|
||||
swd_queue_dp_bankselect(dap, reg);
|
||||
swd->write_reg(dap, swd_cmd(false, false, reg), data);
|
||||
|
||||
retval = swd_queue_dp_bankselect(dap, reg);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = swd->write_reg(swd_cmd(false, false, reg), data);
|
||||
|
||||
if (retval != ERROR_OK) {
|
||||
/* fault response */
|
||||
swd_clear_sticky_errors(dap);
|
||||
}
|
||||
|
||||
return retval;
|
||||
return check_sync(dap);
|
||||
}
|
||||
|
||||
/** Select the AP register bank matching bits 7:4 of reg. */
|
||||
static int swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
|
||||
static void swd_queue_ap_bankselect(struct adiv5_dap *dap, unsigned reg)
|
||||
{
|
||||
uint32_t select_ap_bank = reg & 0x000000F0;
|
||||
|
||||
if (select_ap_bank == dap->ap_bank_value)
|
||||
return ERROR_OK;
|
||||
return;
|
||||
|
||||
dap->ap_bank_value = select_ap_bank;
|
||||
select_ap_bank |= dap->ap_current | dap->dp_bank_value;
|
||||
|
||||
return swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
|
||||
swd_queue_dp_write(dap, DP_SELECT, select_ap_bank);
|
||||
}
|
||||
|
||||
static int (swd_queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
|
||||
static int swd_queue_ap_read(struct adiv5_dap *dap, unsigned reg,
|
||||
uint32_t *data)
|
||||
{
|
||||
/* REVISIT status return ... */
|
||||
const struct swd_driver *swd = jtag_interface->swd;
|
||||
assert(swd);
|
||||
|
||||
int retval = swd_queue_ap_bankselect(dap, reg);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = swd->read_reg(swd_cmd(true, true, reg), dap->last_read);
|
||||
swd_queue_ap_bankselect(dap, reg);
|
||||
swd->read_reg(dap, swd_cmd(true, true, reg), dap->last_read);
|
||||
dap->last_read = data;
|
||||
|
||||
if (retval != ERROR_OK) {
|
||||
/* fault response */
|
||||
swd_clear_sticky_errors(dap);
|
||||
return retval;
|
||||
}
|
||||
|
||||
return retval;
|
||||
return check_sync(dap);
|
||||
}
|
||||
|
||||
static int (swd_queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
|
||||
static int swd_queue_ap_write(struct adiv5_dap *dap, unsigned reg,
|
||||
uint32_t data)
|
||||
{
|
||||
/* REVISIT status return ... */
|
||||
const struct swd_driver *swd = jtag_interface->swd;
|
||||
assert(swd);
|
||||
int retval;
|
||||
|
||||
retval = swd_finish_read(dap);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
swd_finish_read(dap);
|
||||
swd_queue_ap_bankselect(dap, reg);
|
||||
swd->write_reg(dap, swd_cmd(false, true, reg), data);
|
||||
|
||||
retval = swd_queue_ap_bankselect(dap, reg);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
|
||||
retval = swd->write_reg(swd_cmd(false, true, reg), data);
|
||||
|
||||
if (retval != ERROR_OK) {
|
||||
/* fault response */
|
||||
swd_clear_sticky_errors(dap);
|
||||
}
|
||||
|
||||
return retval;
|
||||
return check_sync(dap);
|
||||
}
|
||||
|
||||
/** Executes all queued DAP operations. */
|
||||
static int swd_run(struct adiv5_dap *dap)
|
||||
{
|
||||
/* for now the SWD interface hard-wires a zero-size queue. */
|
||||
|
||||
int retval = swd_finish_read(dap);
|
||||
|
||||
/* FIXME but we still need to check and scrub
|
||||
* any hardware errors ...
|
||||
*/
|
||||
return retval;
|
||||
swd_finish_read(dap);
|
||||
return swd_run_inner(dap);
|
||||
}
|
||||
|
||||
const struct dap_ops swd_dap_ops = {
|
||||
|
|
@ -452,14 +419,16 @@ static int swd_init(struct command_context *ctx)
|
|||
|
||||
/* Note, debugport_init() does setup too */
|
||||
|
||||
status = swd_queue_dp_read(dap, DP_IDCODE, &idcode);
|
||||
|
||||
if (status == ERROR_OK)
|
||||
LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
|
||||
swd_queue_dp_read(dap, DP_IDCODE, &idcode);
|
||||
|
||||
/* force clear all sticky faults */
|
||||
swd_clear_sticky_errors(dap);
|
||||
|
||||
status = swd_run(dap);
|
||||
|
||||
if (status == ERROR_OK)
|
||||
LOG_INFO("SWD IDCODE %#8.8" PRIx32, idcode);
|
||||
|
||||
/* this is a workaround to get polling working */
|
||||
jtag_add_reset(0, 0);
|
||||
|
||||
|
|
|
|||
|
|
@ -40,9 +40,9 @@
|
|||
#define JTAG_DP_APACC 0xB
|
||||
|
||||
/* three-bit ACK values for SWD access (sent LSB first) */
|
||||
#define SWD_ACK_OK 0x4
|
||||
#define SWD_ACK_WAIT 0x2
|
||||
#define SWD_ACK_FAULT 0x1
|
||||
#define SWD_ACK_OK 0x1
|
||||
#define SWD_ACK_WAIT 0x2
|
||||
#define SWD_ACK_FAULT 0x4
|
||||
|
||||
#define DPAP_WRITE 0
|
||||
#define DPAP_READ 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue