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target/arc: do not invalidate icache when (un)setting breakpoints 

Currently, instruction cache is being invalidated in
arc_{un,}set_breakpoint() regardless of whether the breakpoint's type is
HW or SW. For SW breakpoints, this has no net effect as the caches are
flushed as a by-product of overwriting instructions in main memory and
is thus merely unnecessary; but for HW breakpoints this invalidation is
not preceded by a flush and might lead to loss of data. This patch
removes the invalidate() call altogether to correct this undesired
behavior for HW breakpoints.

With this patch applied, all supported HW breakpoint tests from the gdb
testsuite are now passing with the arc-openocd backend.

Change-Id: I3d252b97f01f1a1e2bf0eb8fb257bdab0c544bc2
Signed-off-by: Artemiy Volkov <artemiy@synopsys.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7767
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Artemiy Volkov 2023-07-06 13:25:00 +02:00 committed by Antonio Borneo
parent bdf73617e7
commit d20304b3fb
1 changed files with 0 additions and 6 deletions
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6
src/target/arc.c
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@ -1573,9 +1573,6 @@ static int arc_set_breakpoint(struct target *target,
return ERROR_FAIL; return ERROR_FAIL;
} }
/* core instruction cache is now invalid. */
CHECK_RETVAL(arc_cache_invalidate(target));
return ERROR_OK; return ERROR_OK;
} }
@ -1658,9 +1655,6 @@ static int arc_unset_breakpoint(struct target *target,
return ERROR_FAIL; return ERROR_FAIL;
} }
/* core instruction cache is now invalid. */
CHECK_RETVAL(arc_cache_invalidate(target));
return retval; return retval;
} }