nds32: add new target type nds32_v2, nds32_v3, nds32_v3m

Add target code for Andes targets.

Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1259
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

src/target/Makefile.am

@@ -109,7 +109,16 @@ MIPS32_SRC = \
 	mips_ejtag.c
 
 NDS32_SRC = \
-	nds32_reg.c
+	nds32.c \
+	nds32_reg.c \
+	nds32_cmd.c \
+	nds32_disassembler.c \
+	nds32_tlb.c \
+	nds32_v2.c \
+	nds32_v3_common.c \
+	nds32_v3.c \
+	nds32_v3m.c \
+	nds32_aice.c
 
 
 noinst_HEADERS = \
@@ -168,9 +177,17 @@ noinst_HEADERS = \
 	avr32_mem.h \
 	avr32_regs.h \
 	nds32.h \
+	nds32_cmd.h \
+	nds32_disassembler.h \
 	nds32_edm.h \
 	nds32_insn.h \
-	nds32_reg.h
+	nds32_reg.h \
+	nds32_tlb.h \
+	nds32_v2.h \
+	nds32_v3_common.h \
+	nds32_v3.h \
+	nds32_v3m.h \
+	nds32_aice.h
 
 ocddatadir = $(pkglibdir)
 nobase_dist_ocddata_DATA =

src/target/nds32.h

@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
+ *   Copyright (C) 2013 Andes Technology                                   *
  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -22,7 +22,6 @@
 #define __NDS32_H__
 
 #include <jtag/jtag.h>
-#include <jtag/aice/aice_port.h>
 #include "target.h"
 #include "target_type.h"
 #include "register.h"
@@ -31,6 +30,8 @@
 #include "nds32_insn.h"
 #include "nds32_edm.h"
 
+#define NDS32_EDM_OPERATION_MAX_NUM 64
+
 #define CHECK_RETVAL(action)			\
 	do {					\
 		int __retval = (action);	\
@@ -62,18 +63,11 @@ enum nds32_debug_reason {
 	NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP,
 };
 
-enum nds32_tdesc_type {
-	NDS32_CORE_TDESC = 0,
-	NDS32_SYSTEM_TDESC,
-	NDS32_AUDIO_TDESC,
-	NDS32_FPU_TDESC,
-	NDS32_NUM_TDESC,
-};
-
 #define NDS32_STRUCT_STAT_SIZE 60
 #define NDS32_STRUCT_TIMEVAL_SIZE 8
 
 enum nds32_syscall_id {
+	NDS32_SYSCALL_UNDEFINED = 0,
 	NDS32_SYSCALL_EXIT = 1,
 	NDS32_SYSCALL_OPEN = 2,
 	NDS32_SYSCALL_CLOSE = 3,
@@ -100,7 +94,8 @@ struct nds32_edm {
 	/** The number of hardware breakpoints */
 	int breakpoint_num;
 
-	/** EDM_CFG.DALM, indicate if direct local memory access feature is supported or not */
+	/** EDM_CFG.DALM, indicate if direct local memory access
+	 * feature is supported or not */
 	bool direct_access_local_memory;
 
 	/** Support ACC_CTL register */
@@ -173,10 +168,10 @@ struct nds32_memory {
 	int dlm_end;
 
 	/** Memory access method */
-	enum aice_memory_access access_channel;
+	enum nds_memory_access access_channel;
 
 	/** Memory access mode */
-	enum aice_memory_mode mode;
+	enum nds_memory_select mode;
 
 	/** Address translation */
 	bool address_translation;
@@ -275,7 +270,7 @@ struct nds32 {
 	/** Backup target registers may be modified in debug state */
 	int (*enter_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
 
-	/** Get address hitted watchpoint */
+	/** Get address hit watchpoint */
 	int (*get_watched_address)(struct nds32 *nds32, uint32_t *address, uint32_t reason);
 
 	/** maximum interrupt level */
@@ -289,24 +284,28 @@ struct nds32 {
 	/** Flag reporting whether virtual hosting is active. */
 	bool virtual_hosting;
 
-	/** Flag reporting whether continue/step hits syscall or not */
-	bool hit_syscall;
-
-	/** Value to be returned by virtual hosting SYS_ERRNO request. */
-	int virtual_hosting_errno;
-
-	/** Flag reporting whether syscall is aborted */
-	bool virtual_hosting_ctrl_c;
-
-	/** Record syscall ID for other operations to do special processing for target */
-	int active_syscall_id;
-
 	/** Flag reporting whether global stop is active. */
 	bool global_stop;
 
+	/** Flag reporting whether to use soft-reset-halt or not as issuing reset-halt. */
+	bool soft_reset_halt;
+
 	/** reset-halt as target examine */
 	bool reset_halt_as_examine;
 
+	/** backup/restore target EDM_CTL value. As debugging target debug
+	 * handler, it should be true. */
+	bool keep_target_edm_ctl;
+
+	/** always use word-aligned address to access memory */
+	bool word_access_mem;
+
+	/** EDM passcode for debugging secure MCU */
+	char *edm_passcode;
+
+	/** current privilege_level if using secure MCU. value 0 is the highest level.  */
+	int privilege_level;
+
 	/** Period to wait after SRST. */
 	uint32_t boot_time;
 
@@ -322,12 +321,19 @@ struct nds32 {
 	/** Flag to indicate fpu-extension is enabled or not */
 	bool fpu_enable;
 
+	/* Andes Core has mixed endian model. Instruction is always big-endian.
+	 * Data may be big or little endian. Device registers may have different
+	 * endian from data and instruction. */
+	/** Endian of data memory */
+	enum target_endianness data_endian;
+
+	/** Endian of device registers */
+	enum target_endianness device_reg_endian;
+
 	/** Flag to indicate if auto convert software breakpoints to
 	 *  hardware breakpoints or not in ROM */
 	bool auto_convert_hw_bp;
 
-	int (*setup_virtual_hosting)(struct target *target, int enable);
-
 	/** Backpointer to the target. */
 	struct target *target;
 
@@ -343,6 +349,11 @@ struct nds32_reg {
 	bool enable;
 };
 
+struct nds32_edm_operation {
+	uint32_t reg_no;
+	uint32_t value;
+};
+
 extern int nds32_config(struct nds32 *nds32);
 extern int nds32_init_arch_info(struct target *target, struct nds32 *nds32);
 extern int nds32_full_context(struct nds32 *nds32);
@@ -352,12 +363,8 @@ extern int nds32_add_software_breakpoint(struct target *target,
 extern int nds32_remove_software_breakpoint(struct target *target,
 		struct breakpoint *breakpoint);
 
-extern int nds32_get_gdb_general_reg_list(struct target *target,
-					struct reg **reg_list[], int *reg_list_size);
 extern int nds32_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size);
-extern int nds32_get_gdb_target_description(struct target *target, char **xml,
-					char *annex, int32_t offset, uint32_t length);
 
 extern int nds32_write_buffer(struct target *target, uint32_t address,
 		uint32_t size, const uint8_t *buffer);
@@ -377,15 +384,14 @@ extern int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *
 extern int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value);
 
 extern int nds32_edm_config(struct nds32 *nds32);
-extern int nds32_check_extension(struct nds32 *nds32);
 extern int nds32_cache_sync(struct target *target, uint32_t address, uint32_t length);
 extern int nds32_mmu(struct target *target, int *enabled);
-extern int nds32_virtual_to_physical(struct target *target, uint32_t address, uint32_t *physical);
+extern int nds32_virtual_to_physical(struct target *target, uint32_t address,
+		uint32_t *physical);
 extern int nds32_read_phys_memory(struct target *target, uint32_t address,
 		uint32_t size, uint32_t count, uint8_t *buffer);
 extern int nds32_write_phys_memory(struct target *target, uint32_t address,
 		uint32_t size, uint32_t count, const uint8_t *buffer);
-extern int nds32_soft_reset_halt(struct target *target);
 extern uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address);
 extern int nds32_examine_debug_reason(struct nds32 *nds32);
 extern int nds32_step(struct target *target, int current,
@@ -397,11 +403,8 @@ extern int nds32_resume(struct target *target, int current,
 		uint32_t address, int handle_breakpoints, int debug_execution);
 extern int nds32_assert_reset(struct target *target);
 extern int nds32_init(struct nds32 *nds32);
-extern int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info);
-extern int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address,
-						uint32_t size, const uint8_t *buffer);
-extern int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c);
 extern int nds32_reset_halt(struct nds32 *nds32);
+extern int nds32_login(struct nds32 *nds32);
 
 /** Convert target handle to generic Andes target state handle. */
 static inline struct nds32 *target_to_nds32(struct target *target)

src/target/nds32_aice.c

@@ -0,0 +1,157 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes technology.                                  *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/log.h>
+#include "nds32_aice.h"
+
+int aice_read_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t *val)
+{
+	if (aice->port->api->read_reg_64 == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->read_reg_64(num, val);
+}
+
+int aice_write_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t val)
+{
+	if (aice->port->api->write_reg_64 == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->write_reg_64(num, val);
+}
+
+int aice_select_target(struct aice_port_s *aice, uint32_t target_id)
+{
+	if (aice->port->api->select_target == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->select_target(target_id);
+}
+
+int aice_read_tlb(struct aice_port_s *aice, uint32_t virtual_address,
+		uint32_t *physical_address)
+{
+	if (aice->port->api->read_tlb == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->read_tlb(virtual_address, physical_address);
+}
+
+int aice_cache_ctl(struct aice_port_s *aice, uint32_t subtype, uint32_t address)
+{
+	if (aice->port->api->cache_ctl == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->cache_ctl(subtype, address);
+}
+
+int aice_set_retry_times(struct aice_port_s *aice, uint32_t a_retry_times)
+{
+	if (aice->port->api->set_retry_times == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->set_retry_times(a_retry_times);
+}
+
+int aice_program_edm(struct aice_port_s *aice, char *command_sequence)
+{
+	if (aice->port->api->program_edm == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->program_edm(command_sequence);
+}
+
+int aice_pack_command(struct aice_port_s *aice, bool enable_pack_command)
+{
+	if (aice->port->api->pack_command == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->pack_command(enable_pack_command);
+}
+
+int aice_execute(struct aice_port_s *aice, uint32_t *instructions,
+		uint32_t instruction_num)
+{
+	if (aice->port->api->execute == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->execute(instructions, instruction_num);
+}
+
+int aice_set_custom_srst_script(struct aice_port_s *aice, const char *script)
+{
+	if (aice->port->api->set_custom_srst_script == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->set_custom_srst_script(script);
+}
+
+int aice_set_custom_trst_script(struct aice_port_s *aice, const char *script)
+{
+	if (aice->port->api->set_custom_trst_script == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->set_custom_trst_script(script);
+}
+
+int aice_set_custom_restart_script(struct aice_port_s *aice, const char *script)
+{
+	if (aice->port->api->set_custom_restart_script == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->set_custom_restart_script(script);
+}
+
+int aice_set_count_to_check_dbger(struct aice_port_s *aice, uint32_t count_to_check)
+{
+	if (aice->port->api->set_count_to_check_dbger == NULL) {
+		LOG_WARNING("Not implemented: %s", __func__);
+		return ERROR_FAIL;
+	}
+
+	return aice->port->api->set_count_to_check_dbger(count_to_check);
+}

src/target/nds32_aice.h

@@ -0,0 +1,160 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes technology.                                  *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+#ifndef __NDS32_AICE_H__
+#define __NDS32_AICE_H__
+
+#include <jtag/aice/aice_port.h>
+
+int aice_read_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t *val);
+int aice_write_reg_64(struct aice_port_s *aice, uint32_t num, uint64_t val);
+int aice_select_target(struct aice_port_s *aice, uint32_t target_id);
+int aice_read_tlb(struct aice_port_s *aice, uint32_t virtual_address,
+		uint32_t *physical_address);
+int aice_cache_ctl(struct aice_port_s *aice, uint32_t subtype, uint32_t address);
+int aice_set_retry_times(struct aice_port_s *aice, uint32_t a_retry_times);
+int aice_program_edm(struct aice_port_s *aice, char *command_sequence);
+int aice_pack_command(struct aice_port_s *aice, bool enable_pack_command);
+int aice_execute(struct aice_port_s *aice, uint32_t *instructions,
+		uint32_t instruction_num);
+int aice_set_custom_srst_script(struct aice_port_s *aice, const char *script);
+int aice_set_custom_trst_script(struct aice_port_s *aice, const char *script);
+int aice_set_custom_restart_script(struct aice_port_s *aice, const char *script);
+int aice_set_count_to_check_dbger(struct aice_port_s *aice, uint32_t count_to_check);
+
+static inline int aice_open(struct aice_port_s *aice, struct aice_port_param_s *param)
+{
+	return aice->port->api->open(param);
+}
+
+static inline int aice_close(struct aice_port_s *aice)
+{
+	return aice->port->api->close();
+}
+
+static inline int aice_reset(struct aice_port_s *aice)
+{
+	return aice->port->api->reset();
+}
+
+static inline int aice_assert_srst(struct aice_port_s *aice,
+		enum aice_srst_type_s srst)
+{
+	return aice->port->api->assert_srst(srst);
+}
+
+static inline int aice_run(struct aice_port_s *aice)
+{
+	return aice->port->api->run();
+}
+
+static inline int aice_halt(struct aice_port_s *aice)
+{
+	return aice->port->api->halt();
+}
+
+static inline int aice_step(struct aice_port_s *aice)
+{
+	return aice->port->api->step();
+}
+
+static inline int aice_read_register(struct aice_port_s *aice, uint32_t num,
+		uint32_t *val)
+{
+	return aice->port->api->read_reg(num, val);
+}
+
+static inline int aice_write_register(struct aice_port_s *aice, uint32_t num,
+		uint32_t val)
+{
+	return aice->port->api->write_reg(num, val);
+}
+
+static inline int aice_read_debug_reg(struct aice_port_s *aice, uint32_t addr,
+		uint32_t *val)
+{
+	return aice->port->api->read_debug_reg(addr, val);
+}
+
+static inline int aice_write_debug_reg(struct aice_port_s *aice, uint32_t addr,
+		const uint32_t val)
+{
+	return aice->port->api->write_debug_reg(addr, val);
+}
+
+static inline int aice_read_mem_unit(struct aice_port_s *aice, uint32_t addr,
+		uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	return aice->port->api->read_mem_unit(addr, size, count, buffer);
+}
+
+static inline int aice_write_mem_unit(struct aice_port_s *aice, uint32_t addr,
+		uint32_t size, uint32_t count, const uint8_t *buffer)
+{
+	return aice->port->api->write_mem_unit(addr, size, count, buffer);
+}
+
+static inline int aice_read_mem_bulk(struct aice_port_s *aice, uint32_t addr,
+		uint32_t length, uint8_t *buffer)
+{
+	return aice->port->api->read_mem_bulk(addr, length, buffer);
+}
+
+static inline int aice_write_mem_bulk(struct aice_port_s *aice, uint32_t addr,
+		uint32_t length, const uint8_t *buffer)
+{
+	return aice->port->api->write_mem_bulk(addr, length, buffer);
+}
+
+static inline int aice_idcode(struct aice_port_s *aice, uint32_t *idcode,
+		uint8_t *num_of_idcode)
+{
+	return aice->port->api->idcode(idcode, num_of_idcode);
+}
+
+static inline int aice_state(struct aice_port_s *aice,
+		enum aice_target_state_s *state)
+{
+	return aice->port->api->state(state);
+}
+
+static inline int aice_set_jtag_clock(struct aice_port_s *aice, uint32_t a_clock)
+{
+	return aice->port->api->set_jtag_clock(a_clock);
+}
+
+static inline int aice_memory_access(struct aice_port_s *aice,
+		enum nds_memory_access a_access)
+{
+	return aice->port->api->memory_access(a_access);
+}
+
+static inline int aice_memory_mode(struct aice_port_s *aice,
+		enum nds_memory_select mem_select)
+{
+	return aice->port->api->memory_mode(mem_select);
+}
+
+static inline int aice_set_data_endian(struct aice_port_s *aice,
+		enum aice_target_endian target_data_endian)
+{
+	return aice->port->api->set_data_endian(target_data_endian);
+}
+
+#endif

src/target/nds32_cmd.h

@@ -0,0 +1,27 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#ifndef __NDS32_CMD_H__
+#define __NDS32_CMD_H__
+#include <helper/command.h>
+
+extern const struct command_registration nds32_command_handlers[];
+
+#endif /* __NDS32_CMD_H__ */

src/target/nds32_disassembler.h

@@ -0,0 +1,58 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#ifndef __NDS32_DISASSEMBLER_H__
+#define __NDS32_DISASSEMBLER_H__
+
+#include <target/nds32.h>
+
+enum nds32_instruction_type {
+	NDS32_INSN_DATA_PROC = 0,
+	NDS32_INSN_LOAD_STORE,
+	NDS32_INSN_JUMP_BRANCH,
+	NDS32_INSN_RESOURCE_ACCESS,
+	NDS32_INSN_MISC,
+};
+
+struct nds32_instruction {
+	enum nds32_instruction_type type;
+	char text[128];
+	uint32_t opcode;
+	uint8_t instruction_size;
+	uint32_t access_start;
+	uint32_t access_end;
+
+	struct {
+		uint8_t opc_6;
+		uint8_t rt;
+		uint8_t ra;
+		uint8_t rb;
+		uint8_t rd;
+		uint8_t sub_opc;
+		int32_t imm;
+	} info;
+
+};
+
+int nds32_read_opcode(struct nds32 *nds32, uint32_t address, uint32_t *value);
+int nds32_evaluate_opcode(struct nds32 *nds32, uint32_t opcode, uint32_t address,
+		struct nds32_instruction *instruction);
+
+#endif /* __NDS32_DISASSEMBLER_H__ */

src/target/nds32_edm.h

@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
+ *   Copyright (C) 2013 Andes Technology                                   *
  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *

src/target/nds32_insn.h

@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
+ *   Copyright (C) 2013 Andes Technology                                   *
  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *

src/target/nds32_reg.c

@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
+ *   Copyright (C) 2013 Andes Technology                                   *
  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -21,10 +21,24 @@
 #include "config.h"
 #endif
 
+#include <helper/log.h>
 #include "nds32_reg.h"
 
 static bool nds32_reg_init_done;
 static struct nds32_reg_s nds32_regs[TOTAL_REG_NUM];
+static struct nds32_reg_exception_s nds32_ex_reg_values[] = {
+	{IR0, 3, 0x3, 2},
+	{IR0, 3, 0x3, 3},
+	{IR1, 3, 0x3, 2},
+	{IR1, 3, 0x3, 3},
+	{IR2, 3, 0x3, 2},
+	{IR2, 3, 0x3, 3},
+	{MR3, 1, 0x7, 0},
+	{MR3, 1, 0x7, 4},
+	{MR3, 1, 0x7, 6},
+	{MR3, 8, 0x7, 3},
+	{0, 0, 0, 0},
+};
 
 static inline void nds32_reg_set(uint32_t number, const char *simple_mnemonic,
 		const char *symbolic_mnemonic, uint32_t sr_index,
@@ -117,6 +131,11 @@ void nds32_reg_init(void)
 	nds32_reg_set(IR23, "ir23", "", SRIDX(1, 10, 5), NDS32_REG_TYPE_IR, 32);
 	nds32_reg_set(IR24, "ir24", "", SRIDX(1, 10, 6), NDS32_REG_TYPE_IR, 32);
 	nds32_reg_set(IR25, "ir25", "", SRIDX(1, 10, 7), NDS32_REG_TYPE_IR, 32);
+	nds32_reg_set(IR26, "ir26", "", SRIDX(1, 8, 1), NDS32_REG_TYPE_IR, 32);
+	nds32_reg_set(IR27, "ir27", "", SRIDX(1, 9, 1), NDS32_REG_TYPE_IR, 32);
+	nds32_reg_set(IR28, "ir28", "", SRIDX(1, 11, 1), NDS32_REG_TYPE_IR, 32);
+	nds32_reg_set(IR29, "ir29", "", SRIDX(1, 9, 4), NDS32_REG_TYPE_IR, 32);
+	nds32_reg_set(IR30, "ir30", "", SRIDX(1, 1, 3), NDS32_REG_TYPE_IR, 32);
 
 	nds32_reg_set(MR0, "mr0", "MMU_CTL", SRIDX(2, 0, 0), NDS32_REG_TYPE_MR, 32);
 	nds32_reg_set(MR1, "mr1", "L1_PPTB", SRIDX(2, 1, 0), NDS32_REG_TYPE_MR, 32);
@@ -335,3 +354,29 @@ const char *nds32_reg_symbolic_name(uint32_t number)
 {
 	return nds32_regs[number].symbolic_mnemonic;
 }
+
+bool nds32_reg_exception(uint32_t number, uint32_t value)
+{
+	int i;
+	struct nds32_reg_exception_s *ex_reg_value;
+	uint32_t field_value;
+
+	i = 0;
+	while (nds32_ex_reg_values[i].reg_num != 0) {
+		ex_reg_value = nds32_ex_reg_values + i;
+
+		if (ex_reg_value->reg_num == number) {
+			field_value = (value >> ex_reg_value->ex_value_bit_pos) &
+				ex_reg_value->ex_value_mask;
+			if (field_value == ex_reg_value->ex_value) {
+				LOG_WARNING("It will generate exceptions as setting %d to %s",
+						value, nds32_regs[number].simple_mnemonic);
+				return true;
+			}
+		}
+
+		i++;
+	}
+
+	return false;
+}

src/target/nds32_reg.h

@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2013 by Andes Technology                                *
+ *   Copyright (C) 2013 Andes Technology                                   *
  *   Hsiangkai Wang <hkwang@andestech.com>                                 *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -24,8 +24,7 @@
 #define NDS32_REGISTER_DISABLE		(0x0)
 
 enum nds32_reg_number_s {
-	/* general registers */
+	R0 = 0, /* general registers */
-	R0 = 0,
 	R1,
 	R2,
 	R3,
@@ -64,9 +63,7 @@ enum nds32_reg_number_s {
 	D1HI,
 	ITB,
 	IFC_LP,
-
+	CR0, /* system registers */
-	/* system registers */
-	CR0,
 	CR1,
 	CR2,
 	CR3,
@@ -99,6 +96,11 @@ enum nds32_reg_number_s {
 	IR23,
 	IR24,
 	IR25,
+	IR26,
+	IR27,
+	IR28,
+	IR29,
+	IR30,
 	MR0,
 	MR1,
 	MR2,
@@ -180,9 +182,7 @@ enum nds32_reg_number_s {
 	IDR0,
 	IDR1,
 	SECUR0,
-
+	D0L24, /* audio registers */
-	/* audio registers */
-	D0L24,
 	D1L24,
 	I0,
 	I1,
@@ -214,9 +214,7 @@ enum nds32_reg_number_s {
 	CBE1,
 	CBE2,
 	CBE3,
-
+	FPCSR, /* fpu */
-	/* fpu */
-	FPCSR,
 	FPCFG,
 	FS0,
 	FS1,
@@ -310,11 +308,19 @@ struct nds32_reg_s {
 	uint8_t size;
 };
 
+struct nds32_reg_exception_s {
+	uint32_t reg_num;
+	uint32_t ex_value_bit_pos;
+	uint32_t ex_value_mask;
+	uint32_t ex_value;
+};
+
 void nds32_reg_init(void);
 uint32_t nds32_reg_sr_index(uint32_t number);
 enum nds32_reg_type_s nds32_reg_type(uint32_t number);
 uint8_t nds32_reg_size(uint32_t number);
 const char *nds32_reg_simple_name(uint32_t number);
 const char *nds32_reg_symbolic_name(uint32_t number);
+bool nds32_reg_exception(uint32_t number, uint32_t value);
 
 #endif

src/target/nds32_tlb.c

@@ -0,0 +1,80 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "nds32_aice.h"
+#include "nds32_tlb.h"
+
+int nds32_probe_tlb(struct nds32 *nds32, const uint32_t virtual_address,
+		uint32_t *physical_address)
+{
+	struct target *target = nds32->target;
+	struct aice_port_s *aice = target_to_aice(target);
+
+	return aice_read_tlb(aice, virtual_address, physical_address);
+}
+
+struct page_table_walker_info_s page_table_info[PAGE_SIZE_NUM] = {
+	/* 4K page */
+	{0xFFC00000, 20, 0x003FF000, 10, 0x00000FFF, 0xFFFFF000, 0xFFFFF000, 0xFFFFF000},
+	/* 8K page */
+	{0xFF000000, 22, 0x00FFE000, 11, 0x00001FFF, 0xFFFFF000, 0xFFFFE000, 0xFFFFE000},
+};
+
+int nds32_walk_page_table(struct nds32 *nds32, const uint32_t virtual_address,
+		uint32_t *physical_address)
+{
+	struct target *target = nds32->target;
+	uint32_t value_mr1;
+	uint32_t load_address;
+	uint32_t L1_page_table_entry;
+	uint32_t L2_page_table_entry;
+	uint32_t page_size_index = nds32->mmu_config.default_min_page_size;
+	struct page_table_walker_info_s *page_table_info_p =
+		&(page_table_info[page_size_index]);
+
+	/* Read L1 Physical Page Table */
+	nds32_get_mapped_reg(nds32, MR1, &value_mr1);
+	load_address = (value_mr1 & page_table_info_p->L1_base_mask) |
+		((virtual_address & page_table_info_p->L1_offset_mask) >>
+		 page_table_info_p->L1_offset_shift);
+	/* load_address is physical address */
+	nds32_read_buffer(target, load_address, 4, (uint8_t *)&L1_page_table_entry);
+
+	/* Read L2 Physical Page Table */
+	if (L1_page_table_entry & 0x1) /* L1_PTE not present */
+		return ERROR_FAIL;
+
+	load_address = (L1_page_table_entry & page_table_info_p->L2_base_mask) |
+		((virtual_address & page_table_info_p->L2_offset_mask) >>
+		 page_table_info_p->L2_offset_shift);
+	/* load_address is physical address */
+	nds32_read_buffer(target, load_address, 4, (uint8_t *)&L2_page_table_entry);
+
+	if ((L2_page_table_entry & 0x1) != 0x1) /* L2_PTE not valid */
+		return ERROR_FAIL;
+
+	*physical_address = (L2_page_table_entry & page_table_info_p->ppn_mask) |
+		(virtual_address & page_table_info_p->va_offset_mask);
+
+	return ERROR_OK;
+}

src/target/nds32_tlb.h

@@ -0,0 +1,48 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+#ifndef __NDS32_TLB_H__
+#define __NDS32_TLB_H__
+
+#include "nds32.h"
+
+enum {
+	PAGE_SIZE_4K = 0,
+	PAGE_SIZE_8K,
+	PAGE_SIZE_NUM,
+};
+
+struct page_table_walker_info_s {
+
+	uint32_t L1_offset_mask;
+	uint32_t L1_offset_shift;
+	uint32_t L2_offset_mask;
+	uint32_t L2_offset_shift;
+	uint32_t va_offset_mask;
+	uint32_t L1_base_mask;
+	uint32_t L2_base_mask;
+	uint32_t ppn_mask;
+};
+
+extern int nds32_probe_tlb(struct nds32 *nds32, const uint32_t virtual_address,
+		uint32_t *physical_address);
+extern int nds32_walk_page_table(struct nds32 *nds32, const uint32_t virtual_address,
+		uint32_t *physical_address);
+
+#endif

src/target/nds32_v2.c

@@ -0,0 +1,763 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/time_support.h>
+#include <helper/binarybuffer.h>
+#include "breakpoints.h"
+#include "nds32_insn.h"
+#include "nds32_reg.h"
+#include "nds32_edm.h"
+#include "nds32_cmd.h"
+#include "nds32_v2.h"
+#include "nds32_aice.h"
+#include "target_type.h"
+
+static int nds32_v2_register_mapping(struct nds32 *nds32, int reg_no)
+{
+	uint32_t max_level = nds32->max_interrupt_level;
+	uint32_t cur_level = nds32->current_interrupt_level;
+
+	if ((1 <= cur_level) && (cur_level < max_level)) {
+		if (IR0 == reg_no) {
+			LOG_DEBUG("Map PSW to IPSW");
+			return IR1;
+		} else if (PC == reg_no) {
+			LOG_DEBUG("Map PC to IPC");
+			return IR9;
+		}
+	} else if ((2 <= cur_level) && (cur_level < max_level)) {
+		if (R26 == reg_no) {
+			LOG_DEBUG("Mapping P0 to P_P0");
+			return IR12;
+		} else if (R27 == reg_no) {
+			LOG_DEBUG("Mapping P1 to P_P1");
+			return IR13;
+		} else if (IR1 == reg_no) {
+			LOG_DEBUG("Mapping IPSW to P_IPSW");
+			return IR2;
+		} else if (IR4 == reg_no) {
+			LOG_DEBUG("Mapping EVA to P_EVA");
+			return IR5;
+		} else if (IR6 == reg_no) {
+			LOG_DEBUG("Mapping ITYPE to P_ITYPE");
+			return IR7;
+		} else if (IR9 == reg_no) {
+			LOG_DEBUG("Mapping IPC to P_IPC");
+			return IR10;
+		}
+	} else if (cur_level == max_level) {
+		if (PC == reg_no) {
+			LOG_DEBUG("Mapping PC to O_IPC");
+			return IR11;
+		}
+	}
+
+	return reg_no;
+}
+
+static int nds32_v2_get_debug_reason(struct nds32 *nds32, uint32_t *reason)
+{
+	uint32_t val_itype;
+	struct aice_port_s *aice = target_to_aice(nds32->target);
+
+	aice_read_register(aice, IR6, &val_itype);
+
+	*reason = val_itype & 0x0F;
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_activate_hardware_breakpoint(struct target *target)
+{
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
+	struct aice_port_s *aice = target_to_aice(target);
+	struct breakpoint *bp;
+	int32_t hbr_index = 0;
+
+	for (bp = target->breakpoints; bp; bp = bp->next) {
+		if (bp->type == BKPT_SOFT) {
+			/* already set at nds32_v2_add_breakpoint() */
+			continue;
+		} else if (bp->type == BKPT_HARD) {
+			/* set address */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address);
+			/* set mask */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0);
+			/* set value */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0);
+
+			if (nds32_v2->nds32.memory.address_translation)
+				/* enable breakpoint (virtual address) */
+				aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2);
+			else
+				/* enable breakpoint (physical address) */
+				aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
+
+			LOG_DEBUG("Add hardware BP %d at %08" PRIx32, hbr_index,
+					bp->address);
+
+			hbr_index++;
+		} else {
+			return ERROR_FAIL;
+		}
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_deactivate_hardware_breakpoint(struct target *target)
+{
+	struct aice_port_s *aice = target_to_aice(target);
+	struct breakpoint *bp;
+	int32_t hbr_index = 0;
+
+	for (bp = target->breakpoints; bp; bp = bp->next) {
+		if (bp->type == BKPT_SOFT)
+			continue;
+		else if (bp->type == BKPT_HARD)
+			/* disable breakpoint */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0);
+		else
+			return ERROR_FAIL;
+
+		LOG_DEBUG("Remove hardware BP %d at %08" PRIx32, hbr_index,
+				bp->address);
+
+		hbr_index++;
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_activate_hardware_watchpoint(struct target *target)
+{
+	struct aice_port_s *aice = target_to_aice(target);
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
+	struct watchpoint *wp;
+	int32_t wp_num = nds32_v2->next_hbr_index;
+	uint32_t wp_config = 0;
+
+	for (wp = target->watchpoints; wp; wp = wp->next) {
+
+		wp_num--;
+		wp->mask = wp->length - 1;
+		if ((wp->address % wp->length) != 0)
+			wp->mask = (wp->mask << 1) + 1;
+
+		if (wp->rw == WPT_READ)
+			wp_config = 0x3;
+		else if (wp->rw == WPT_WRITE)
+			wp_config = 0x5;
+		else if (wp->rw == WPT_ACCESS)
+			wp_config = 0x7;
+
+		/* set/unset physical address bit of BPCn according to PSW.DT */
+		if (nds32_v2->nds32.memory.address_translation == false)
+			wp_config |= 0x8;
+
+		/* set address */
+		aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
+				wp->address - (wp->address % wp->length));
+		/* set mask */
+		aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
+		/* enable watchpoint */
+		aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
+		/* set value */
+		aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
+
+		LOG_DEBUG("Add hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32, wp_num,
+				wp->address, wp->mask);
+
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_deactivate_hardware_watchpoint(struct target *target)
+{
+	struct aice_port_s *aice = target_to_aice(target);
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
+	int32_t wp_num = nds32_v2->next_hbr_index;
+	struct watchpoint *wp;
+
+	for (wp = target->watchpoints; wp; wp = wp->next) {
+		wp_num--;
+		/* disable watchpoint */
+		aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
+
+		LOG_DEBUG("Remove hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32,
+				wp_num, wp->address, wp->mask);
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_check_interrupt_stack(struct nds32_v2_common *nds32_v2)
+{
+	struct nds32 *nds32 = &(nds32_v2->nds32);
+	struct aice_port_s *aice = target_to_aice(nds32->target);
+	uint32_t val_ir0;
+	uint32_t val_ir1;
+	uint32_t val_ir2;
+	uint32_t modified_psw;
+
+	/* Save interrupt level */
+	aice_read_register(aice, IR0, &val_ir0); /* get $IR0 directly */
+
+	/* backup $IR0 */
+	nds32_v2->backup_ir0 = val_ir0;
+
+	nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
+
+	if (nds32_reach_max_interrupt_level(nds32)) {
+		LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %d. -->",
+				nds32->current_interrupt_level);
+
+		/* decrease interrupt level */
+		modified_psw = val_ir0 - 0x2;
+
+		/* disable GIE, IT, DT, HSS */
+		modified_psw &= (~0x8C1);
+
+		aice_write_register(aice, IR0, modified_psw);
+
+		return ERROR_OK;
+	}
+
+
+	/* There is a case that single step also trigger another interrupt,
+	   then HSS bit in psw(ir0) will push to ipsw(ir1).
+	   Then hit debug interrupt HSS bit in ipsw(ir1) will push to (p_ipsw)ir2
+	   Therefore, HSS bit in p_ipsw(ir2) also need clear.
+
+	   Only update $ir2 as current interrupt level is 2, because $ir2 will be random
+	   value if the target never reaches interrupt level 2. */
+	if ((nds32->max_interrupt_level == 3) && (nds32->current_interrupt_level == 2)) {
+		aice_read_register(aice, IR2, &val_ir2); /* get $IR2 directly */
+		val_ir2 &= ~(0x01 << 11);
+		aice_write_register(aice, IR2, val_ir2);
+	}
+
+	/* get origianl DT bit and set to current state let debugger has same memory view
+	   PSW.IT MUST be turned off.  Otherwise, DIM could not operate normally. */
+	aice_read_register(aice, IR1, &val_ir1);
+	modified_psw = val_ir0 | (val_ir1 & 0x80);
+	aice_write_register(aice, IR0, modified_psw);
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_restore_interrupt_stack(struct nds32_v2_common *nds32_v2)
+{
+	struct nds32 *nds32 = &(nds32_v2->nds32);
+	struct aice_port_s *aice = target_to_aice(nds32->target);
+
+	/* restore origin $IR0 */
+	aice_write_register(aice, IR0, nds32_v2->backup_ir0);
+
+	return ERROR_OK;
+}
+
+/**
+ * Save processor state.  This is called after a HALT instruction
+ * succeeds, and on other occasions the processor enters debug mode
+ * (breakpoint, watchpoint, etc).
+ */
+static int nds32_v2_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
+{
+	LOG_DEBUG("nds32_v2_debug_entry");
+
+	jtag_poll_set_enabled(false);
+
+	if (nds32->virtual_hosting)
+		LOG_WARNING("<-- TARGET WARNING! Virtual hosting is not supported "
+				"under V1/V2 architecture. -->");
+
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
+
+	CHECK_RETVAL(nds32_v2_deactivate_hardware_breakpoint(nds32->target));
+
+	if (enable_watchpoint)
+		CHECK_RETVAL(nds32_v2_deactivate_hardware_watchpoint(nds32->target));
+
+	nds32->target->state = TARGET_HALTED;
+	nds32_examine_debug_reason(nds32);
+
+	if (nds32->init_arch_info_after_halted == false) {
+		/* init architecture info according to config registers */
+		CHECK_RETVAL(nds32_config(nds32));
+
+		nds32->init_arch_info_after_halted = true;
+	}
+
+	/* REVISIT entire cache should already be invalid !!! */
+	register_cache_invalidate(nds32->core_cache);
+
+	/* check interrupt level before .full_context(), because
+	 * get_mapped_reg needs current_interrupt_level information */
+	nds32_v2_check_interrupt_stack(nds32_v2);
+
+	/* Save registers. */
+	nds32_full_context(nds32);
+
+	return ERROR_OK;
+}
+
+/* target request support */
+static int nds32_v2_target_request_data(struct target *target,
+		uint32_t size, uint8_t *buffer)
+{
+	/* AndesCore could use DTR register to communicate with OpenOCD
+	 * to output messages
+	 * Target data will be put in buffer
+	 * The format of DTR is as follow
+	 * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd
+	 * target_req_cmd has three possible values:
+	 *   TARGET_REQ_TRACEMSG
+	 *   TARGET_REQ_DEBUGMSG
+	 *   TARGET_REQ_DEBUGCHAR
+	 * if size == 0, target will call target_asciimsg(),
+	 * else call target_hexmsg()
+	 */
+	LOG_WARNING("Not implemented: %s", __func__);
+
+	return ERROR_OK;
+}
+
+/**
+ * Restore processor state.
+ */
+static int nds32_v2_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
+{
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(nds32->target);
+
+	/* activate all hardware breakpoints */
+	CHECK_RETVAL(nds32_v2_activate_hardware_breakpoint(nds32->target));
+
+	if (enable_watchpoint) {
+		/* activate all watchpoints */
+		CHECK_RETVAL(nds32_v2_activate_hardware_watchpoint(nds32->target));
+	}
+
+	/* restore interrupt stack */
+	nds32_v2_restore_interrupt_stack(nds32_v2);
+
+	/* restore PSW, PC, and R0 ... after flushing any modified
+	 * registers.
+	 */
+	CHECK_RETVAL(nds32_restore_context(nds32->target));
+
+	register_cache_invalidate(nds32->core_cache);
+
+	jtag_poll_set_enabled(true);
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_soft_reset_halt(struct target *target)
+{
+	/* TODO: test it */
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct aice_port_s *aice = target_to_aice(target);
+
+	aice_assert_srst(aice, AICE_SRST);
+
+	/* halt core and set pc to 0x0 */
+	int retval = target_halt(target);
+	if (retval != ERROR_OK)
+		return retval;
+
+	/* start fetching from IVB */
+	uint32_t value_ir3;
+	nds32_get_mapped_reg(nds32, IR3, &value_ir3);
+	nds32_set_mapped_reg(nds32, PC, value_ir3 & 0xFFFF0000);
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_deassert_reset(struct target *target)
+{
+	int retval;
+
+	CHECK_RETVAL(nds32_poll(target));
+
+	if (target->state != TARGET_HALTED) {
+		/* reset only */
+		LOG_WARNING("%s: ran after reset and before halt ...",
+				target_name(target));
+		retval = target_halt(target);
+		if (retval != ERROR_OK)
+			return retval;
+		/* call target_poll() to avoid "Halt timed out" */
+		CHECK_RETVAL(target_poll(target));
+	} else {
+		jtag_poll_set_enabled(false);
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_checksum_memory(struct target *target,
+		uint32_t address, uint32_t count, uint32_t *checksum)
+{
+	LOG_WARNING("Not implemented: %s", __func__);
+
+	return ERROR_FAIL;
+}
+
+static int nds32_v2_add_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
+{
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
+	struct nds32 *nds32 = &(nds32_v2->nds32);
+	int result;
+
+	if (breakpoint->type == BKPT_HARD) {
+		/* check hardware resource */
+		if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
+			LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
+					"breakpoints/watchpoints!  The limit of "
+					"combined hardware breakpoints/watchpoints "
+					"is %d. -->", nds32_v2->n_hbr);
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
+
+		/* update next place to put hardware breakpoint */
+		nds32_v2->next_hbr_index++;
+
+		/* hardware breakpoint insertion occurs before 'continue' actually */
+		return ERROR_OK;
+	} else if (breakpoint->type == BKPT_SOFT) {
+		result = nds32_add_software_breakpoint(target, breakpoint);
+		if (ERROR_OK != result) {
+			/* auto convert to hardware breakpoint if failed */
+			if (nds32->auto_convert_hw_bp) {
+				/* convert to hardware breakpoint */
+				breakpoint->type = BKPT_HARD;
+
+				return nds32_v2_add_breakpoint(target, breakpoint);
+			}
+		}
+
+		return result;
+	} else /* unrecognized breakpoint type */
+		return ERROR_FAIL;
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_remove_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
+{
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
+
+	if (breakpoint->type == BKPT_HARD) {
+		if (nds32_v2->next_hbr_index <= 0)
+			return ERROR_FAIL;
+
+		/* update next place to put hardware breakpoint */
+		nds32_v2->next_hbr_index--;
+
+		/* hardware breakpoint removal occurs after 'halted' actually */
+		return ERROR_OK;
+	} else if (breakpoint->type == BKPT_SOFT) {
+		return nds32_remove_software_breakpoint(target, breakpoint);
+	} else /* unrecognized breakpoint type */
+		return ERROR_FAIL;
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_add_watchpoint(struct target *target,
+		struct watchpoint *watchpoint)
+{
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
+
+	/* check hardware resource */
+	if (nds32_v2->n_hbr <= nds32_v2->next_hbr_index) {
+		LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
+				"breakpoints/watchpoints!  The limit of "
+				"combined hardware breakpoints/watchpoints is %d. -->", nds32_v2->n_hbr);
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	/* update next place to put hardware watchpoint */
+	nds32_v2->next_hbr_index++;
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_remove_watchpoint(struct target *target,
+		struct watchpoint *watchpoint)
+{
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
+
+	if (nds32_v2->next_hbr_index <= 0)
+		return ERROR_FAIL;
+
+	/* update next place to put hardware breakpoint */
+	nds32_v2->next_hbr_index--;
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_get_exception_address(struct nds32 *nds32,
+		uint32_t *address, uint32_t reason)
+{
+	struct aice_port_s *aice = target_to_aice(nds32->target);
+
+	aice_read_register(aice, IR4, address); /* read $EVA directly */
+
+	/* TODO: hit multiple watchpoints */
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_run_algorithm(struct target *target,
+		int num_mem_params,
+		struct mem_param *mem_params,
+		int num_reg_params,
+		struct reg_param *reg_params,
+		uint32_t entry_point,
+		uint32_t exit_point,
+		int timeout_ms,
+		void *arch_info)
+{
+	LOG_WARNING("Not implemented: %s", __func__);
+
+	return ERROR_FAIL;
+}
+
+static int nds32_v2_target_create(struct target *target, Jim_Interp *interp)
+{
+	struct nds32_v2_common *nds32_v2;
+
+	nds32_v2 = calloc(1, sizeof(*nds32_v2));
+	if (!nds32_v2)
+		return ERROR_FAIL;
+
+	nds32_v2->nds32.register_map = nds32_v2_register_mapping;
+	nds32_v2->nds32.get_debug_reason = nds32_v2_get_debug_reason;
+	nds32_v2->nds32.enter_debug_state = nds32_v2_debug_entry;
+	nds32_v2->nds32.leave_debug_state = nds32_v2_leave_debug_state;
+	nds32_v2->nds32.get_watched_address = nds32_v2_get_exception_address;
+
+	nds32_init_arch_info(target, &(nds32_v2->nds32));
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_init_target(struct command_context *cmd_ctx,
+		struct target *target)
+{
+	/* Initialize anything we can set up without talking to the target */
+
+	struct nds32 *nds32 = target_to_nds32(target);
+
+	nds32_init(nds32);
+
+	return ERROR_OK;
+}
+
+/* talk to the target and set things up */
+static int nds32_v2_examine(struct target *target)
+{
+	struct nds32_v2_common *nds32_v2 = target_to_nds32_v2(target);
+	struct nds32 *nds32 = &(nds32_v2->nds32);
+	struct aice_port_s *aice = target_to_aice(target);
+
+	if (!target_was_examined(target)) {
+		CHECK_RETVAL(nds32_edm_config(nds32));
+
+		if (nds32->reset_halt_as_examine)
+			CHECK_RETVAL(nds32_reset_halt(nds32));
+	}
+
+	uint32_t edm_cfg;
+	aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
+
+	/* get the number of hardware breakpoints */
+	nds32_v2->n_hbr = (edm_cfg & 0x7) + 1;
+
+	nds32_v2->next_hbr_index = 0;
+
+	LOG_INFO("%s: total hardware breakpoint %d", target_name(target),
+			nds32_v2->n_hbr);
+
+	nds32->target->state = TARGET_RUNNING;
+	nds32->target->debug_reason = DBG_REASON_NOTHALTED;
+
+	target_set_examined(target);
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_translate_address(struct target *target, uint32_t *address)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+	uint32_t physical_address;
+
+	/* Following conditions need to do address translation
+	 * 1. BUS mode
+	 * 2. CPU mode under maximum interrupt level */
+	if ((NDS_MEMORY_ACC_BUS == memory->access_channel) ||
+			((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			 nds32_reach_max_interrupt_level(nds32))) {
+		if (ERROR_OK == target->type->virt2phys(target, *address, &physical_address))
+			*address = physical_address;
+		else
+			return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v2_read_buffer(struct target *target, uint32_t address,
+		uint32_t size, uint8_t *buffer)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+
+	if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			(target->state != TARGET_HALTED)) {
+		LOG_WARNING("target was not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* BUG: If access range crosses multiple pages, the translation will not correct
+	 * for second page or so. */
+
+	nds32_v2_translate_address(target, &address);
+
+	return nds32_read_buffer(target, address, size, buffer);
+}
+
+static int nds32_v2_write_buffer(struct target *target, uint32_t address,
+		uint32_t size, const uint8_t *buffer)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+
+	if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			(target->state != TARGET_HALTED)) {
+		LOG_WARNING("target was not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* BUG: If access range crosses multiple pages, the translation will not correct
+	 * for second page or so. */
+
+	nds32_v2_translate_address(target, &address);
+
+	return nds32_write_buffer(target, address, size, buffer);
+}
+
+static int nds32_v2_read_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+
+	if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			(target->state != TARGET_HALTED)) {
+		LOG_WARNING("target was not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* BUG: If access range crosses multiple pages, the translation will not correct
+	 * for second page or so. */
+
+	nds32_v2_translate_address(target, &address);
+
+	return nds32_read_memory(target, address, size, count, buffer);
+}
+
+static int nds32_v2_write_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, const uint8_t *buffer)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+
+	if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			(target->state != TARGET_HALTED)) {
+		LOG_WARNING("target was not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* BUG: If access range crosses multiple pages, the translation will not correct
+	 * for second page or so. */
+
+	nds32_v2_translate_address(target, &address);
+
+	return nds32_write_memory(target, address, size, count, buffer);
+}
+
+/** Holds methods for V2 targets. */
+struct target_type nds32_v2_target = {
+	.name = "nds32_v2",
+
+	.poll = nds32_poll,
+	.arch_state = nds32_arch_state,
+
+	.target_request_data = nds32_v2_target_request_data,
+
+	.halt = nds32_halt,
+	.resume = nds32_resume,
+	.step = nds32_step,
+
+	.assert_reset = nds32_assert_reset,
+	.deassert_reset = nds32_v2_deassert_reset,
+	.soft_reset_halt = nds32_v2_soft_reset_halt,
+
+	/* register access */
+	.get_gdb_reg_list = nds32_get_gdb_reg_list,
+
+	/* memory access */
+	.read_buffer = nds32_v2_read_buffer,
+	.write_buffer = nds32_v2_write_buffer,
+	.read_memory = nds32_v2_read_memory,
+	.write_memory = nds32_v2_write_memory,
+
+	.checksum_memory = nds32_v2_checksum_memory,
+
+	/* breakpoint/watchpoint */
+	.add_breakpoint = nds32_v2_add_breakpoint,
+	.remove_breakpoint = nds32_v2_remove_breakpoint,
+	.add_watchpoint = nds32_v2_add_watchpoint,
+	.remove_watchpoint = nds32_v2_remove_watchpoint,
+
+	/* MMU */
+	.mmu = nds32_mmu,
+	.virt2phys = nds32_virtual_to_physical,
+	.read_phys_memory = nds32_read_phys_memory,
+	.write_phys_memory = nds32_write_phys_memory,
+
+	.run_algorithm = nds32_v2_run_algorithm,
+
+	.commands = nds32_command_handlers,
+	.target_create = nds32_v2_target_create,
+	.init_target = nds32_v2_init_target,
+	.examine = nds32_v2_examine,
+};

src/target/nds32_v2.h

@@ -0,0 +1,44 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+#ifndef __NDS32_V2_H__
+#define __NDS32_V2_H__
+
+#include "nds32.h"
+
+struct nds32_v2_common {
+	struct nds32 nds32;
+
+	uint32_t backup_ir0;
+
+	/** number of hardware breakpoints */
+	int32_t n_hbr;
+
+	/** next hardware breakpoint index */
+	/** increase from low index to high index */
+	int32_t next_hbr_index;
+};
+
+static inline struct nds32_v2_common *target_to_nds32_v2(struct target *target)
+{
+	return container_of(target->arch_info, struct nds32_v2_common, nds32);
+}
+
+
+#endif	/* __NDS32_V2_H__ */

src/target/nds32_v3.c

@@ -0,0 +1,522 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "breakpoints.h"
+#include "nds32_cmd.h"
+#include "nds32_aice.h"
+#include "nds32_v3.h"
+#include "nds32_v3_common.h"
+
+static int nds32_v3_activate_hardware_breakpoint(struct target *target)
+{
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+	struct aice_port_s *aice = target_to_aice(target);
+	struct breakpoint *bp;
+	int32_t hbr_index = nds32_v3->next_hbr_index;
+
+	for (bp = target->breakpoints; bp; bp = bp->next) {
+		if (bp->type == BKPT_SOFT) {
+			/* already set at nds32_v3_add_breakpoint() */
+			continue;
+		} else if (bp->type == BKPT_HARD) {
+			hbr_index--;
+			/* set address */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + hbr_index, bp->address);
+			/* set mask */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + hbr_index, 0);
+			/* set value */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + hbr_index, 0);
+
+			if (nds32_v3->nds32.memory.address_translation)
+				/* enable breakpoint (virtual address) */
+				aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x2);
+			else
+				/* enable breakpoint (physical address) */
+				aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0xA);
+
+			LOG_DEBUG("Add hardware BP %d at %08" PRIx32, hbr_index,
+					bp->address);
+		} else {
+			return ERROR_FAIL;
+		}
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_deactivate_hardware_breakpoint(struct target *target)
+{
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+	struct aice_port_s *aice = target_to_aice(target);
+	struct breakpoint *bp;
+	int32_t hbr_index = nds32_v3->next_hbr_index;
+
+	for (bp = target->breakpoints; bp; bp = bp->next) {
+		if (bp->type == BKPT_SOFT) {
+			continue;
+		} else if (bp->type == BKPT_HARD) {
+			hbr_index--;
+			/* disable breakpoint */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + hbr_index, 0x0);
+		} else {
+			return ERROR_FAIL;
+		}
+
+		LOG_DEBUG("Remove hardware BP %d at %08" PRIx32, hbr_index,
+				bp->address);
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_activate_hardware_watchpoint(struct target *target)
+{
+	struct aice_port_s *aice = target_to_aice(target);
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+	struct watchpoint *wp;
+	int32_t wp_num = 0;
+	uint32_t wp_config = 0;
+	bool ld_stop, st_stop;
+
+	if (nds32_v3->nds32.global_stop)
+		ld_stop = st_stop = false;
+
+	for (wp = target->watchpoints; wp; wp = wp->next) {
+
+		if (wp_num < nds32_v3->used_n_wp) {
+			wp->mask = wp->length - 1;
+			if ((wp->address % wp->length) != 0)
+				wp->mask = (wp->mask << 1) + 1;
+
+			if (wp->rw == WPT_READ)
+				wp_config = 0x3;
+			else if (wp->rw == WPT_WRITE)
+				wp_config = 0x5;
+			else if (wp->rw == WPT_ACCESS)
+				wp_config = 0x7;
+
+			/* set/unset physical address bit of BPCn according to PSW.DT */
+			if (nds32_v3->nds32.memory.address_translation == false)
+				wp_config |= 0x8;
+
+			/* set address */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
+					wp->address - (wp->address % wp->length));
+			/* set mask */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
+			/* enable watchpoint */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
+			/* set value */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPV0 + wp_num, 0);
+
+			LOG_DEBUG("Add hardware wathcpoint %d at %08" PRIx32 " mask %08" PRIx32,
+					wp_num, wp->address, wp->mask);
+
+			wp_num++;
+		} else if (nds32_v3->nds32.global_stop) {
+			if (wp->rw == WPT_READ)
+				ld_stop = true;
+			else if (wp->rw == WPT_WRITE)
+				st_stop = true;
+			else if (wp->rw == WPT_ACCESS)
+				ld_stop = st_stop = true;
+		}
+	}
+
+	if (nds32_v3->nds32.global_stop) {
+		uint32_t edm_ctl;
+		aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
+		if (ld_stop)
+			edm_ctl |= 0x10;
+		if (st_stop)
+			edm_ctl |= 0x20;
+		aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_deactivate_hardware_watchpoint(struct target *target)
+{
+	struct aice_port_s *aice = target_to_aice(target);
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+	int32_t wp_num = 0;
+	struct watchpoint *wp;
+	bool clean_global_stop = false;
+
+	for (wp = target->watchpoints; wp; wp = wp->next) {
+
+		if (wp_num < nds32_v3->used_n_wp) {
+			/* disable watchpoint */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
+
+			LOG_DEBUG("Remove hardware wathcpoint %d at %08" PRIx32
+					" mask %08" PRIx32, wp_num,
+					wp->address, wp->mask);
+			wp_num++;
+		} else if (nds32_v3->nds32.global_stop) {
+			clean_global_stop = true;
+		}
+	}
+
+	if (clean_global_stop) {
+		uint32_t edm_ctl;
+		aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
+		edm_ctl = edm_ctl & (~0x30);
+		aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_check_interrupt_stack(struct nds32 *nds32)
+{
+	uint32_t val_ir0;
+	uint32_t value;
+
+	/* Save interrupt level */
+	nds32_get_mapped_reg(nds32, IR0, &val_ir0);
+	nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
+
+	if (nds32_reach_max_interrupt_level(nds32))
+		LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %d. -->",
+				nds32->current_interrupt_level);
+
+	/* backup $ir4 & $ir6 to avoid suppressed exception overwrite */
+	nds32_get_mapped_reg(nds32, IR4, &value);
+	nds32_get_mapped_reg(nds32, IR6, &value);
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_restore_interrupt_stack(struct nds32 *nds32)
+{
+	uint32_t value;
+
+	/* get backup value from cache */
+	/* then set back to make the register dirty */
+	nds32_get_mapped_reg(nds32, IR0, &value);
+	nds32_set_mapped_reg(nds32, IR0, value);
+
+	nds32_get_mapped_reg(nds32, IR4, &value);
+	nds32_set_mapped_reg(nds32, IR4, value);
+
+	nds32_get_mapped_reg(nds32, IR6, &value);
+	nds32_set_mapped_reg(nds32, IR6, value);
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_deassert_reset(struct target *target)
+{
+	int retval;
+	struct aice_port_s *aice = target_to_aice(target);
+	bool switch_to_v3_stack = false;
+	uint32_t value_edm_ctl;
+
+	aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &value_edm_ctl);
+	if (((value_edm_ctl >> 6) & 0x1) == 0) { /* reset to V2 EDM mode */
+		aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, value_edm_ctl | (0x1 << 6));
+		aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &value_edm_ctl);
+		if (((value_edm_ctl >> 6) & 0x1) == 1)
+			switch_to_v3_stack = true;
+	} else
+		switch_to_v3_stack = false;
+
+	CHECK_RETVAL(nds32_poll(target));
+
+	if (target->state != TARGET_HALTED) {
+		/* reset only */
+		LOG_WARNING("%s: ran after reset and before halt ...",
+				target_name(target));
+		retval = target_halt(target);
+		if (retval != ERROR_OK)
+			return retval;
+
+		/* call target_poll() to avoid "Halt timed out" */
+		CHECK_RETVAL(target_poll(target));
+	} else {
+		/* reset-halt */
+		jtag_poll_set_enabled(false);
+
+		struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+		struct nds32 *nds32 = &(nds32_v3->nds32);
+		uint32_t value;
+		uint32_t interrupt_level;
+
+		if (switch_to_v3_stack == true) {
+			/* PSW.INTL-- */
+			nds32_get_mapped_reg(nds32, IR0, &value);
+			interrupt_level = (value >> 1) & 0x3;
+			interrupt_level--;
+			value &= ~(0x6);
+			value |= (interrupt_level << 1);
+			value |= 0x400;  /* set PSW.DEX */
+			nds32_set_mapped_reg(nds32, IR0, value);
+
+			/* copy IPC to OIPC */
+			if ((interrupt_level + 1) < nds32->max_interrupt_level) {
+				nds32_get_mapped_reg(nds32, IR9, &value);
+				nds32_set_mapped_reg(nds32, IR11, value);
+			}
+		}
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_add_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
+{
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+	struct nds32 *nds32 = &(nds32_v3->nds32);
+	int result;
+
+	if (breakpoint->type == BKPT_HARD) {
+		/* check hardware resource */
+		if (nds32_v3->n_hbr <= nds32_v3->next_hbr_index) {
+			LOG_WARNING("<-- TARGET WARNING! Insert too many "
+					"hardware breakpoints/watchpoints! "
+					"The limit of combined hardware "
+					"breakpoints/watchpoints is %d. -->",
+					nds32_v3->n_hbr);
+			LOG_WARNING("<-- TARGET STATUS: Inserted number of "
+					"hardware breakpoint: %d, hardware "
+					"watchpoints: %d. -->",
+					nds32_v3->next_hbr_index - nds32_v3->used_n_wp,
+					nds32_v3->used_n_wp);
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
+
+		/* update next place to put hardware breakpoint */
+		nds32_v3->next_hbr_index++;
+
+		/* hardware breakpoint insertion occurs before 'continue' actually */
+		return ERROR_OK;
+	} else if (breakpoint->type == BKPT_SOFT) {
+		result = nds32_add_software_breakpoint(target, breakpoint);
+		if (ERROR_OK != result) {
+			/* auto convert to hardware breakpoint if failed */
+			if (nds32->auto_convert_hw_bp) {
+				/* convert to hardware breakpoint */
+				breakpoint->type = BKPT_HARD;
+
+				return nds32_v3_add_breakpoint(target, breakpoint);
+			}
+		}
+
+		return result;
+	} else /* unrecognized breakpoint type */
+		return ERROR_FAIL;
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_remove_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
+{
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+
+	if (breakpoint->type == BKPT_HARD) {
+		if (nds32_v3->next_hbr_index <= 0)
+			return ERROR_FAIL;
+
+		/* update next place to put hardware breakpoint */
+		nds32_v3->next_hbr_index--;
+
+		/* hardware breakpoint removal occurs after 'halted' actually */
+		return ERROR_OK;
+	} else if (breakpoint->type == BKPT_SOFT) {
+		return nds32_remove_software_breakpoint(target, breakpoint);
+	} else /* unrecognized breakpoint type */
+		return ERROR_FAIL;
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_add_watchpoint(struct target *target,
+		struct watchpoint *watchpoint)
+{
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+
+	/* check hardware resource */
+	if (nds32_v3->n_hbr <= nds32_v3->next_hbr_index) {
+		/* No hardware resource */
+		if (nds32_v3->nds32.global_stop) {
+			LOG_WARNING("<-- TARGET WARNING! The number of "
+					"watchpoints exceeds the hardware "
+					"resources. Stop at every load/store "
+					"instruction to check for watchpoint matches. -->");
+			return ERROR_OK;
+		}
+
+		LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
+				"breakpoints/watchpoints! The limit of combined "
+				"hardware breakpoints/watchpoints is %d. -->",
+				nds32_v3->n_hbr);
+		LOG_WARNING("<-- TARGET STATUS: Inserted number of "
+				"hardware breakpoint: %d, hardware "
+				"watchpoints: %d. -->",
+				nds32_v3->next_hbr_index - nds32_v3->used_n_wp,
+				nds32_v3->used_n_wp);
+
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	/* update next place to put hardware watchpoint */
+	nds32_v3->next_hbr_index++;
+	nds32_v3->used_n_wp++;
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_remove_watchpoint(struct target *target,
+		struct watchpoint *watchpoint)
+{
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+
+	if (nds32_v3->next_hbr_index <= 0) {
+		if (nds32_v3->nds32.global_stop)
+			return ERROR_OK;
+
+		return ERROR_FAIL;
+	}
+
+	/* update next place to put hardware breakpoint */
+	nds32_v3->next_hbr_index--;
+	nds32_v3->used_n_wp--;
+
+	return ERROR_OK;
+}
+
+struct nds32_v3_common_callback nds32_v3_common_callback = {
+	.check_interrupt_stack = nds32_v3_check_interrupt_stack,
+	.restore_interrupt_stack = nds32_v3_restore_interrupt_stack,
+	.activate_hardware_breakpoint = nds32_v3_activate_hardware_breakpoint,
+	.activate_hardware_watchpoint = nds32_v3_activate_hardware_watchpoint,
+	.deactivate_hardware_breakpoint = nds32_v3_deactivate_hardware_breakpoint,
+	.deactivate_hardware_watchpoint = nds32_v3_deactivate_hardware_watchpoint,
+};
+
+static int nds32_v3_target_create(struct target *target, Jim_Interp *interp)
+{
+	struct nds32_v3_common *nds32_v3;
+
+	nds32_v3 = calloc(1, sizeof(*nds32_v3));
+	if (!nds32_v3)
+		return ERROR_FAIL;
+
+	nds32_v3_common_register_callback(&nds32_v3_common_callback);
+	nds32_v3_target_create_common(target, &(nds32_v3->nds32));
+
+	return ERROR_OK;
+}
+
+/* talk to the target and set things up */
+static int nds32_v3_examine(struct target *target)
+{
+	struct nds32_v3_common *nds32_v3 = target_to_nds32_v3(target);
+	struct nds32 *nds32 = &(nds32_v3->nds32);
+	struct aice_port_s *aice = target_to_aice(target);
+
+	if (!target_was_examined(target)) {
+		CHECK_RETVAL(nds32_edm_config(nds32));
+
+		if (nds32->reset_halt_as_examine)
+			CHECK_RETVAL(nds32_reset_halt(nds32));
+	}
+
+	uint32_t edm_cfg;
+	aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
+
+	/* get the number of hardware breakpoints */
+	nds32_v3->n_hbr = (edm_cfg & 0x7) + 1;
+
+	/* low interference profiling */
+	if (edm_cfg & 0x100)
+		nds32_v3->low_interference_profile = true;
+	else
+		nds32_v3->low_interference_profile = false;
+
+	nds32_v3->next_hbr_index = 0;
+	nds32_v3->used_n_wp = 0;
+
+	LOG_INFO("%s: total hardware breakpoint %d", target_name(target),
+			nds32_v3->n_hbr);
+
+	nds32->target->state = TARGET_RUNNING;
+	nds32->target->debug_reason = DBG_REASON_NOTHALTED;
+
+	target_set_examined(target);
+
+	return ERROR_OK;
+}
+
+/** Holds methods for Andes1337 targets. */
+struct target_type nds32_v3_target = {
+	.name = "nds32_v3",
+
+	.poll = nds32_poll,
+	.arch_state = nds32_arch_state,
+
+	.target_request_data = nds32_v3_target_request_data,
+
+	.halt = nds32_halt,
+	.resume = nds32_resume,
+	.step = nds32_step,
+
+	.assert_reset = nds32_assert_reset,
+	.deassert_reset = nds32_v3_deassert_reset,
+	.soft_reset_halt = nds32_v3_soft_reset_halt,
+
+	/* register access */
+	.get_gdb_reg_list = nds32_get_gdb_reg_list,
+
+	/* memory access */
+	.read_buffer = nds32_v3_read_buffer,
+	.write_buffer = nds32_v3_write_buffer,
+	.read_memory = nds32_v3_read_memory,
+	.write_memory = nds32_v3_write_memory,
+
+	.checksum_memory = nds32_v3_checksum_memory,
+
+	/* breakpoint/watchpoint */
+	.add_breakpoint = nds32_v3_add_breakpoint,
+	.remove_breakpoint = nds32_v3_remove_breakpoint,
+	.add_watchpoint = nds32_v3_add_watchpoint,
+	.remove_watchpoint = nds32_v3_remove_watchpoint,
+
+	/* MMU */
+	.mmu = nds32_mmu,
+	.virt2phys = nds32_virtual_to_physical,
+	.read_phys_memory = nds32_read_phys_memory,
+	.write_phys_memory = nds32_write_phys_memory,
+
+	.run_algorithm = nds32_v3_run_algorithm,
+
+	.commands = nds32_command_handlers,
+	.target_create = nds32_v3_target_create,
+	.init_target = nds32_v3_init_target,
+	.examine = nds32_v3_examine,
+};

src/target/nds32_v3.h

@@ -0,0 +1,46 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+#ifndef __NDS32_V3_H__
+#define __NDS32_V3_H__
+
+#include "nds32.h"
+
+struct nds32_v3_common {
+	struct nds32 nds32;
+
+	/** number of hardware breakpoints */
+	int32_t n_hbr;
+
+	/** number of used hardware watchpoints */
+	int32_t used_n_wp;
+
+	/** next hardware breakpoint index */
+	int32_t next_hbr_index;
+
+	/** low interference profiling */
+	bool low_interference_profile;
+};
+
+static inline struct nds32_v3_common *target_to_nds32_v3(struct target *target)
+{
+	return container_of(target->arch_info, struct nds32_v3_common, nds32);
+}
+
+#endif	/* __NDS32_V3_H__ */

src/target/nds32_v3_common.c

@@ -0,0 +1,492 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "breakpoints.h"
+#include "nds32_reg.h"
+#include "nds32_disassembler.h"
+#include "nds32.h"
+#include "nds32_aice.h"
+#include "nds32_v3_common.h"
+
+static struct nds32_v3_common_callback *v3_common_callback;
+
+static int nds32_v3_register_mapping(struct nds32 *nds32, int reg_no)
+{
+	if (reg_no == PC)
+		return IR11;
+
+	return reg_no;
+}
+
+static int nds32_v3_get_debug_reason(struct nds32 *nds32, uint32_t *reason)
+{
+	uint32_t edmsw;
+	struct aice_port_s *aice = target_to_aice(nds32->target);
+	aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw);
+
+	*reason = (edmsw >> 12) & 0x0F;
+
+	return ERROR_OK;
+}
+
+/**
+ * Save processor state.  This is called after a HALT instruction
+ * succeeds, and on other occasions the processor enters debug mode
+ * (breakpoint, watchpoint, etc).
+ */
+static int nds32_v3_debug_entry(struct nds32 *nds32, bool enable_watchpoint)
+{
+	LOG_DEBUG("nds32_v3_debug_entry");
+
+	jtag_poll_set_enabled(false);
+
+	enum target_state backup_state = nds32->target->state;
+	nds32->target->state = TARGET_HALTED;
+
+	if (nds32->init_arch_info_after_halted == false) {
+		/* init architecture info according to config registers */
+		CHECK_RETVAL(nds32_config(nds32));
+
+		nds32->init_arch_info_after_halted = true;
+	}
+
+	/* REVISIT entire cache should already be invalid !!! */
+	register_cache_invalidate(nds32->core_cache);
+
+	/* deactivate all hardware breakpoints */
+	CHECK_RETVAL(v3_common_callback->deactivate_hardware_breakpoint(nds32->target));
+
+	if (enable_watchpoint)
+		CHECK_RETVAL(v3_common_callback->deactivate_hardware_watchpoint(nds32->target));
+
+	if (ERROR_OK != nds32_examine_debug_reason(nds32)) {
+		nds32->target->state = backup_state;
+
+		/* re-activate all hardware breakpoints & watchpoints */
+		CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(nds32->target));
+
+		if (enable_watchpoint)
+			CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(nds32->target));
+
+		jtag_poll_set_enabled(true);
+
+		return ERROR_FAIL;
+	}
+
+	/* Save registers. */
+	nds32_full_context(nds32);
+
+	/* check interrupt level */
+	v3_common_callback->check_interrupt_stack(nds32);
+
+	return ERROR_OK;
+}
+
+/**
+ * Restore processor state.
+ */
+static int nds32_v3_leave_debug_state(struct nds32 *nds32, bool enable_watchpoint)
+{
+	LOG_DEBUG("nds32_v3_leave_debug_state");
+
+	struct target *target = nds32->target;
+
+	/* activate all hardware breakpoints */
+	CHECK_RETVAL(v3_common_callback->activate_hardware_breakpoint(target));
+
+	if (enable_watchpoint) {
+		/* activate all watchpoints */
+		CHECK_RETVAL(v3_common_callback->activate_hardware_watchpoint(target));
+	}
+
+	/* restore interrupt stack */
+	v3_common_callback->restore_interrupt_stack(nds32);
+
+	/* REVISIT once we start caring about MMU and cache state,
+	 * address it here ...
+	 */
+
+	/* restore PSW, PC, and R0 ... after flushing any modified
+	 * registers.
+	 */
+	CHECK_RETVAL(nds32_restore_context(target));
+
+	/* enable polling */
+	jtag_poll_set_enabled(true);
+
+	return ERROR_OK;
+}
+
+static int nds32_v3_get_exception_address(struct nds32 *nds32,
+		uint32_t *address, uint32_t reason)
+{
+	LOG_DEBUG("nds32_v3_get_exception_address");
+
+	struct aice_port_s *aice = target_to_aice(nds32->target);
+	struct target *target = nds32->target;
+	uint32_t edmsw;
+	uint32_t edm_cfg;
+	uint32_t match_bits;
+	uint32_t match_count;
+	int32_t i;
+	static int32_t number_of_hard_break;
+
+	if (number_of_hard_break == 0) {
+		aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
+		number_of_hard_break = (edm_cfg & 0x7) + 1;
+	}
+
+	aice_read_debug_reg(aice, NDS_EDM_SR_EDMSW, &edmsw);
+	/* clear matching bits (write-one-clear) */
+	aice_write_debug_reg(aice, NDS_EDM_SR_EDMSW, edmsw);
+	match_bits = (edmsw >> 4) & 0xFF;
+	match_count = 0;
+	for (i = 0 ; i < number_of_hard_break ; i++) {
+		if (match_bits & (1 << i)) {
+			aice_read_debug_reg(aice, NDS_EDM_SR_BPA0 + i, address);
+			match_count++;
+		}
+	}
+
+	if (match_count > 1) { /* multiple hits */
+		*address = 0;
+		return ERROR_OK;
+	} else if (match_count == 1) {
+		uint32_t val_pc;
+		uint32_t opcode;
+		struct nds32_instruction instruction;
+		struct watchpoint *wp;
+		bool hit;
+
+		nds32_get_mapped_reg(nds32, PC, &val_pc);
+
+		if ((NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE == reason) ||
+				(NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE == reason)) {
+			if (edmsw & 0x4) /* check EDMSW.IS_16BIT */
+				val_pc -= 2;
+			else
+				val_pc -= 4;
+		}
+
+		nds32_read_opcode(nds32, val_pc, &opcode);
+		nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction);
+
+		LOG_DEBUG("PC: 0x%08x, access start: 0x%08x, end: 0x%08x", val_pc,
+				instruction.access_start, instruction.access_end);
+
+		/* check if multiple hits in the access range */
+		uint32_t in_range_watch_count = 0;
+		for (wp = target->watchpoints; wp; wp = wp->next) {
+			if ((instruction.access_start <= wp->address) &&
+					(wp->address < instruction.access_end))
+				in_range_watch_count++;
+		}
+		if (in_range_watch_count > 1) {
+			/* Hit LSMW instruction. */
+			*address = 0;
+			return ERROR_OK;
+		}
+
+		/* dispel false match */
+		hit = false;
+		for (wp = target->watchpoints; wp; wp = wp->next) {
+			if (((*address ^ wp->address) & (~wp->mask)) == 0) {
+				uint32_t watch_start;
+				uint32_t watch_end;
+
+				watch_start = wp->address;
+				watch_end = wp->address + wp->length;
+
+				if ((watch_end <= instruction.access_start) ||
+						(instruction.access_end <= watch_start))
+					continue;
+
+				hit = true;
+				break;
+			}
+		}
+
+		if (hit)
+			return ERROR_OK;
+		else
+			return ERROR_FAIL;
+	} else if (match_count == 0) {
+		/* global stop is precise exception */
+		if ((NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP == reason) && nds32->global_stop) {
+			/* parse instruction to get correct access address */
+			uint32_t val_pc;
+			uint32_t opcode;
+			struct nds32_instruction instruction;
+
+			nds32_get_mapped_reg(nds32, PC, &val_pc);
+			nds32_read_opcode(nds32, val_pc, &opcode);
+			nds32_evaluate_opcode(nds32, opcode, val_pc, &instruction);
+
+			*address = instruction.access_start;
+
+			return ERROR_OK;
+		}
+	}
+
+	*address = 0xFFFFFFFF;
+	return ERROR_FAIL;
+}
+
+void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback)
+{
+	v3_common_callback = callback;
+}
+
+/** target_type functions: */
+/* target request support */
+int nds32_v3_target_request_data(struct target *target,
+		uint32_t size, uint8_t *buffer)
+{
+	/* AndesCore could use DTR register to communicate with OpenOCD
+	 * to output messages
+	 * Target data will be put in buffer
+	 * The format of DTR is as follow
+	 * DTR[31:16] => length, DTR[15:8] => size, DTR[7:0] => target_req_cmd
+	 * target_req_cmd has three possible values:
+	 *   TARGET_REQ_TRACEMSG
+	 *   TARGET_REQ_DEBUGMSG
+	 *   TARGET_REQ_DEBUGCHAR
+	 * if size == 0, target will call target_asciimsg(),
+	 * else call target_hexmsg()
+	 */
+	LOG_WARNING("Not implemented: %s", __func__);
+
+	return ERROR_OK;
+}
+
+int nds32_v3_soft_reset_halt(struct target *target)
+{
+	struct aice_port_s *aice = target_to_aice(target);
+	return aice_assert_srst(aice, AICE_RESET_HOLD);
+}
+
+int nds32_v3_checksum_memory(struct target *target,
+		uint32_t address, uint32_t count, uint32_t *checksum)
+{
+	LOG_WARNING("Not implemented: %s", __func__);
+
+	return ERROR_FAIL;
+}
+
+int nds32_v3_target_create_common(struct target *target, struct nds32 *nds32)
+{
+	nds32->register_map = nds32_v3_register_mapping;
+	nds32->get_debug_reason = nds32_v3_get_debug_reason;
+	nds32->enter_debug_state = nds32_v3_debug_entry;
+	nds32->leave_debug_state = nds32_v3_leave_debug_state;
+	nds32->get_watched_address = nds32_v3_get_exception_address;
+
+	/* Init target->arch_info in nds32_init_arch_info().
+	 * After this, user could use target_to_nds32() to get nds32 object */
+	nds32_init_arch_info(target, nds32);
+
+	return ERROR_OK;
+}
+
+int nds32_v3_run_algorithm(struct target *target,
+		int num_mem_params,
+		struct mem_param *mem_params,
+		int num_reg_params,
+		struct reg_param *reg_params,
+		uint32_t entry_point,
+		uint32_t exit_point,
+		int timeout_ms,
+		void *arch_info)
+{
+	LOG_WARNING("Not implemented: %s", __func__);
+
+	return ERROR_FAIL;
+}
+
+int nds32_v3_read_buffer(struct target *target, uint32_t address,
+		uint32_t size, uint8_t *buffer)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+
+	if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			(target->state != TARGET_HALTED)) {
+		LOG_WARNING("target was not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	uint32_t physical_address;
+	/* BUG: If access range crosses multiple pages, the translation will not correct
+	 * for second page or so. */
+
+	/* When DEX is set to one, hardware will enforce the following behavior without
+	 * modifying the corresponding control bits in PSW.
+	 *
+	 * Disable all interrupts
+	 * Become superuser mode
+	 * Turn off IT/DT
+	 * Use MMU_CFG.DE as the data access endian
+	 * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
+	 * Disable audio special features
+	 * Disable inline function call
+	 *
+	 * Because hardware will turn off IT/DT by default, it MUST translate virtual address
+	 * to physical address.
+	 */
+	if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
+		address = physical_address;
+	else
+		return ERROR_FAIL;
+
+	return nds32_read_buffer(target, address, size, buffer);
+}
+
+int nds32_v3_write_buffer(struct target *target, uint32_t address,
+		uint32_t size, const uint8_t *buffer)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+
+	if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			(target->state != TARGET_HALTED)) {
+		LOG_WARNING("target was not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	uint32_t physical_address;
+	/* BUG: If access range crosses multiple pages, the translation will not correct
+	 * for second page or so. */
+
+	/* When DEX is set to one, hardware will enforce the following behavior without
+	 * modifying the corresponding control bits in PSW.
+	 *
+	 * Disable all interrupts
+	 * Become superuser mode
+	 * Turn off IT/DT
+	 * Use MMU_CFG.DE as the data access endian
+	 * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
+	 * Disable audio special features
+	 * Disable inline function call
+	 *
+	 * Because hardware will turn off IT/DT by default, it MUST translate virtual address
+	 * to physical address.
+	 */
+	if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
+		address = physical_address;
+	else
+		return ERROR_FAIL;
+
+	return nds32_write_buffer(target, address, size, buffer);
+}
+
+int nds32_v3_read_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+
+	if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			(target->state != TARGET_HALTED)) {
+		LOG_WARNING("target was not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	uint32_t physical_address;
+	/* BUG: If access range crosses multiple pages, the translation will not correct
+	 * for second page or so. */
+
+	/* When DEX is set to one, hardware will enforce the following behavior without
+	 * modifying the corresponding control bits in PSW.
+	 *
+	 * Disable all interrupts
+	 * Become superuser mode
+	 * Turn off IT/DT
+	 * Use MMU_CFG.DE as the data access endian
+	 * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
+	 * Disable audio special features
+	 * Disable inline function call
+	 *
+	 * Because hardware will turn off IT/DT by default, it MUST translate virtual address
+	 * to physical address.
+	 */
+	if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
+		address = physical_address;
+	else
+		return ERROR_FAIL;
+
+	int result;
+
+	result = nds32_read_memory(target, address, size, count, buffer);
+
+	return result;
+}
+
+int nds32_v3_write_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, const uint8_t *buffer)
+{
+	struct nds32 *nds32 = target_to_nds32(target);
+	struct nds32_memory *memory = &(nds32->memory);
+
+	if ((NDS_MEMORY_ACC_CPU == memory->access_channel) &&
+			(target->state != TARGET_HALTED)) {
+		LOG_WARNING("target was not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	uint32_t physical_address;
+	/* BUG: If access range crosses multiple pages, the translation will not correct
+	 * for second page or so. */
+
+	/* When DEX is set to one, hardware will enforce the following behavior without
+	 * modifying the corresponding control bits in PSW.
+	 *
+	 * Disable all interrupts
+	 * Become superuser mode
+	 * Turn off IT/DT
+	 * Use MMU_CFG.DE as the data access endian
+	 * Use MMU_CFG.DRDE as the device register access endian if MMU_CTL.DREE is asserted
+	 * Disable audio special features
+	 * Disable inline function call
+	 *
+	 * Because hardware will turn off IT/DT by default, it MUST translate virtual address
+	 * to physical address.
+	 */
+	if (ERROR_OK == target->type->virt2phys(target, address, &physical_address))
+		address = physical_address;
+	else
+		return ERROR_FAIL;
+
+	return nds32_write_memory(target, address, size, count, buffer);
+}
+
+int nds32_v3_init_target(struct command_context *cmd_ctx,
+		struct target *target)
+{
+	/* Initialize anything we can set up without talking to the target */
+	struct nds32 *nds32 = target_to_nds32(target);
+
+	nds32_init(nds32);
+
+	return ERROR_OK;
+}

src/target/nds32_v3_common.h

@@ -0,0 +1,63 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+#ifndef __NDS32_V3_COMMON_H__
+#define __NDS32_V3_COMMON_H__
+
+#include "target.h"
+
+struct nds32_v3_common_callback {
+	int (*check_interrupt_stack)(struct nds32 *nds32);
+	int (*restore_interrupt_stack)(struct nds32 *nds32);
+	int (*activate_hardware_breakpoint)(struct target *target);
+	int (*activate_hardware_watchpoint)(struct target *target);
+	int (*deactivate_hardware_breakpoint)(struct target *target);
+	int (*deactivate_hardware_watchpoint)(struct target *target);
+};
+
+void nds32_v3_common_register_callback(struct nds32_v3_common_callback *callback);
+int nds32_v3_target_request_data(struct target *target,
+		uint32_t size, uint8_t *buffer);
+int nds32_v3_soft_reset_halt(struct target *target);
+int nds32_v3_checksum_memory(struct target *target,
+		uint32_t address, uint32_t count, uint32_t *checksum);
+int nds32_v3_hit_watchpoint(struct target *target,
+		struct watchpoint **hit_watchpoint);
+int nds32_v3_target_create_common(struct target *target, struct nds32 *nds32);
+int nds32_v3_run_algorithm(struct target *target,
+		int num_mem_params,
+		struct mem_param *mem_params,
+		int num_reg_params,
+		struct reg_param *reg_params,
+		uint32_t entry_point,
+		uint32_t exit_point,
+		int timeout_ms,
+		void *arch_info);
+int nds32_v3_read_buffer(struct target *target, uint32_t address,
+		uint32_t size, uint8_t *buffer);
+int nds32_v3_write_buffer(struct target *target, uint32_t address,
+		uint32_t size, const uint8_t *buffer);
+int nds32_v3_read_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer);
+int nds32_v3_write_memory(struct target *target, uint32_t address,
+		uint32_t size, uint32_t count, const uint8_t *buffer);
+int nds32_v3_init_target(struct command_context *cmd_ctx,
+		struct target *target);
+
+#endif	/* __NDS32_V3_COMMON_H__ */

src/target/nds32_v3m.c

@@ -0,0 +1,510 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "breakpoints.h"
+#include "nds32_cmd.h"
+#include "nds32_aice.h"
+#include "nds32_v3m.h"
+#include "nds32_v3_common.h"
+
+static int nds32_v3m_activate_hardware_breakpoint(struct target *target)
+{
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+	struct aice_port_s *aice = target_to_aice(target);
+	struct breakpoint *bp;
+	unsigned brp_num = nds32_v3m->n_hbr - 1;
+
+	for (bp = target->breakpoints; bp; bp = bp->next) {
+		if (bp->type == BKPT_SOFT) {
+			/* already set at nds32_v3m_add_breakpoint() */
+			continue;
+		} else if (bp->type == BKPT_HARD) {
+			/* set address */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + brp_num, bp->address);
+			/* set mask */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + brp_num, 0);
+
+			if (nds32_v3m->nds32.memory.address_translation)
+				/* enable breakpoint (virtual address) */
+				aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0x2);
+			else
+				/* enable breakpoint (physical address) */
+				aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0xA);
+
+			LOG_DEBUG("Add hardware BP %d at %08" PRIx32, brp_num,
+					bp->address);
+
+			brp_num--;
+		} else {
+			return ERROR_FAIL;
+		}
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_deactivate_hardware_breakpoint(struct target *target)
+{
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+	struct aice_port_s *aice = target_to_aice(target);
+	struct breakpoint *bp;
+	unsigned brp_num = nds32_v3m->n_hbr - 1;
+
+	for (bp = target->breakpoints; bp; bp = bp->next) {
+		if (bp->type == BKPT_SOFT)
+			continue;
+		else if (bp->type == BKPT_HARD)
+			/* disable breakpoint */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + brp_num, 0x0);
+		else
+			return ERROR_FAIL;
+
+		LOG_DEBUG("Remove hardware BP %d at %08" PRIx32, brp_num,
+				bp->address);
+
+		brp_num--;
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_activate_hardware_watchpoint(struct target *target)
+{
+	struct aice_port_s *aice = target_to_aice(target);
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+	struct watchpoint *wp;
+	int32_t  wp_num = 0;
+	uint32_t wp_config = 0;
+	bool ld_stop, st_stop;
+
+	if (nds32_v3m->nds32.global_stop)
+		ld_stop = st_stop = false;
+
+	for (wp = target->watchpoints; wp; wp = wp->next) {
+
+		if (wp_num < nds32_v3m->used_n_wp) {
+			wp->mask = wp->length - 1;
+			if ((wp->address % wp->length) != 0)
+				wp->mask = (wp->mask << 1) + 1;
+
+			if (wp->rw == WPT_READ)
+				wp_config = 0x3;
+			else if (wp->rw == WPT_WRITE)
+				wp_config = 0x5;
+			else if (wp->rw == WPT_ACCESS)
+				wp_config = 0x7;
+
+			/* set/unset physical address bit of BPCn according to PSW.DT */
+			if (nds32_v3m->nds32.memory.address_translation == false)
+				wp_config |= 0x8;
+
+			/* set address */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPA0 + wp_num,
+					wp->address - (wp->address % wp->length));
+			/* set mask */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPAM0 + wp_num, wp->mask);
+			/* enable watchpoint */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, wp_config);
+
+			LOG_DEBUG("Add hardware wathcpoint %d at %08" PRIx32
+					" mask %08" PRIx32, wp_num,
+					wp->address, wp->mask);
+
+			wp_num++;
+		} else if (nds32_v3m->nds32.global_stop) {
+			if (wp->rw == WPT_READ)
+				ld_stop = true;
+			else if (wp->rw == WPT_WRITE)
+				st_stop = true;
+			else if (wp->rw == WPT_ACCESS)
+				ld_stop = st_stop = true;
+		}
+	}
+
+	if (nds32_v3m->nds32.global_stop) {
+		uint32_t edm_ctl;
+		aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
+		if (ld_stop)
+			edm_ctl |= 0x10;
+		if (st_stop)
+			edm_ctl |= 0x20;
+		aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_deactivate_hardware_watchpoint(struct target *target)
+{
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+	struct aice_port_s *aice = target_to_aice(target);
+	struct watchpoint *wp;
+	int32_t wp_num = 0;
+	bool clean_global_stop = false;
+
+	for (wp = target->watchpoints; wp; wp = wp->next) {
+
+		if (wp_num < nds32_v3m->used_n_wp) {
+			/* disable watchpoint */
+			aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + wp_num, 0x0);
+
+			LOG_DEBUG("Remove hardware wathcpoint %d at %08" PRIx32
+					" mask %08" PRIx32, wp_num,
+					wp->address, wp->mask);
+			wp_num++;
+		} else if (nds32_v3m->nds32.global_stop) {
+			clean_global_stop = true;
+		}
+	}
+
+	if (clean_global_stop) {
+		uint32_t edm_ctl;
+		aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CTL, &edm_ctl);
+		edm_ctl = edm_ctl & (~0x30);
+		aice_write_debug_reg(aice, NDS_EDM_SR_EDM_CTL, edm_ctl);
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_check_interrupt_stack(struct nds32 *nds32)
+{
+	uint32_t val_ir0;
+	uint32_t value;
+
+	/* Save interrupt level */
+	nds32_get_mapped_reg(nds32, IR0, &val_ir0);
+	nds32->current_interrupt_level = (val_ir0 >> 1) & 0x3;
+
+	if (nds32_reach_max_interrupt_level(nds32))
+		LOG_ERROR("<-- TARGET ERROR! Reaching the max interrupt stack level %d. -->",
+				nds32->current_interrupt_level);
+
+	/* backup $ir6 to avoid suppressed exception overwrite */
+	nds32_get_mapped_reg(nds32, IR6, &value);
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_restore_interrupt_stack(struct nds32 *nds32)
+{
+	uint32_t value;
+
+	/* get backup value from cache */
+	/* then set back to make the register dirty */
+	nds32_get_mapped_reg(nds32, IR0, &value);
+	nds32_set_mapped_reg(nds32, IR0, value);
+
+	nds32_get_mapped_reg(nds32, IR6, &value);
+	nds32_set_mapped_reg(nds32, IR6, value);
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_deassert_reset(struct target *target)
+{
+	int retval;
+
+	CHECK_RETVAL(nds32_poll(target));
+
+	if (target->state != TARGET_HALTED) {
+		/* reset only */
+		LOG_WARNING("%s: ran after reset and before halt ...",
+				target_name(target));
+		retval = target_halt(target);
+		if (retval != ERROR_OK)
+			return retval;
+		/* call target_poll() to avoid "Halt timed out" */
+		CHECK_RETVAL(target_poll(target));
+	} else {
+		jtag_poll_set_enabled(false);
+	}
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_add_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
+{
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+	struct nds32 *nds32 = &(nds32_v3m->nds32);
+	int result;
+
+	if (breakpoint->type == BKPT_HARD) {
+		/* check hardware resource */
+		if (nds32_v3m->next_hbr_index < nds32_v3m->next_hwp_index) {
+			LOG_WARNING("<-- TARGET WARNING! Insert too many "
+					"hardware breakpoints/watchpoints! "
+					"The limit of combined hardware "
+					"breakpoints/watchpoints is %d. -->",
+					nds32_v3m->n_hbr);
+			LOG_WARNING("<-- TARGET STATUS: Inserted number of "
+					"hardware breakpoint: %d, hardware "
+					"watchpoints: %d. -->",
+					nds32_v3m->n_hbr - nds32_v3m->next_hbr_index - 1,
+					nds32_v3m->used_n_wp);
+			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+		}
+
+		/* update next place to put hardware breakpoint */
+		nds32_v3m->next_hbr_index--;
+
+		/* hardware breakpoint insertion occurs before 'continue' actually */
+		return ERROR_OK;
+	} else if (breakpoint->type == BKPT_SOFT) {
+		result = nds32_add_software_breakpoint(target, breakpoint);
+		if (ERROR_OK != result) {
+			/* auto convert to hardware breakpoint if failed */
+			if (nds32->auto_convert_hw_bp) {
+				/* convert to hardware breakpoint */
+				breakpoint->type = BKPT_HARD;
+
+				return nds32_v3m_add_breakpoint(target, breakpoint);
+			}
+		}
+
+		return result;
+	} else /* unrecognized breakpoint type */
+		return ERROR_FAIL;
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_remove_breakpoint(struct target *target,
+		struct breakpoint *breakpoint)
+{
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+
+	if (breakpoint->type == BKPT_HARD) {
+		if (nds32_v3m->next_hbr_index >= nds32_v3m->n_hbr - 1)
+			return ERROR_FAIL;
+
+		/* update next place to put hardware breakpoint */
+		nds32_v3m->next_hbr_index++;
+
+		/* hardware breakpoint removal occurs after 'halted' actually */
+		return ERROR_OK;
+	} else if (breakpoint->type == BKPT_SOFT) {
+		return nds32_remove_software_breakpoint(target, breakpoint);
+	} else /* unrecognized breakpoint type */
+		return ERROR_FAIL;
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_add_watchpoint(struct target *target,
+		struct watchpoint *watchpoint)
+{
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+
+	/* check hardware resource */
+	if (nds32_v3m->next_hwp_index >= nds32_v3m->n_hwp) {
+		/* No hardware resource */
+		if (nds32_v3m->nds32.global_stop) {
+			LOG_WARNING("<-- TARGET WARNING! The number of "
+					"watchpoints exceeds the hardware "
+					"resources. Stop at every load/store "
+					"instruction to check for watchpoint matches. -->");
+			return ERROR_OK;
+		}
+
+		LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
+				"watchpoints! The limit of hardware watchpoints "
+				"is %d. -->", nds32_v3m->n_hwp);
+		LOG_WARNING("<-- TARGET STATUS: Inserted number of "
+				"hardware watchpoint: %d. -->",
+				nds32_v3m->used_n_wp);
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	if (nds32_v3m->next_hwp_index > nds32_v3m->next_hbr_index) {
+		/* No hardware resource */
+		if (nds32_v3m->nds32.global_stop) {
+			LOG_WARNING("<-- TARGET WARNING! The number of "
+					"watchpoints exceeds the hardware "
+					"resources. Stop at every load/store "
+					"instruction to check for watchpoint matches. -->");
+			return ERROR_OK;
+		}
+
+		LOG_WARNING("<-- TARGET WARNING! Insert too many hardware "
+				"breakpoints/watchpoints! The limit of combined "
+				"hardware breakpoints/watchpoints is %d. -->",
+				nds32_v3m->n_hbr);
+		LOG_WARNING("<-- TARGET STATUS: Inserted number of "
+				"hardware breakpoint: %d, hardware "
+				"watchpoints: %d. -->",
+				nds32_v3m->n_hbr - nds32_v3m->next_hbr_index - 1,
+				nds32_v3m->used_n_wp);
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	/* update next place to put hardware watchpoint */
+	nds32_v3m->next_hwp_index++;
+	nds32_v3m->used_n_wp++;
+
+	return ERROR_OK;
+}
+
+static int nds32_v3m_remove_watchpoint(struct target *target,
+		struct watchpoint *watchpoint)
+{
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+
+	if (nds32_v3m->next_hwp_index <= 0) {
+		if (nds32_v3m->nds32.global_stop)
+			return ERROR_OK;
+
+		return ERROR_FAIL;
+	}
+
+	/* update next place to put hardware watchpoint */
+	nds32_v3m->next_hwp_index--;
+	nds32_v3m->used_n_wp--;
+
+	return ERROR_OK;
+}
+
+struct nds32_v3_common_callback nds32_v3m_common_callback = {
+	.check_interrupt_stack = nds32_v3m_check_interrupt_stack,
+	.restore_interrupt_stack = nds32_v3m_restore_interrupt_stack,
+	.activate_hardware_breakpoint = nds32_v3m_activate_hardware_breakpoint,
+	.activate_hardware_watchpoint = nds32_v3m_activate_hardware_watchpoint,
+	.deactivate_hardware_breakpoint = nds32_v3m_deactivate_hardware_breakpoint,
+	.deactivate_hardware_watchpoint = nds32_v3m_deactivate_hardware_watchpoint,
+};
+
+static int nds32_v3m_target_create(struct target *target, Jim_Interp *interp)
+{
+	struct nds32_v3m_common *nds32_v3m;
+
+	nds32_v3m = calloc(1, sizeof(*nds32_v3m));
+	if (!nds32_v3m)
+		return ERROR_FAIL;
+
+	nds32_v3_common_register_callback(&nds32_v3m_common_callback);
+	nds32_v3_target_create_common(target, &(nds32_v3m->nds32));
+
+	return ERROR_OK;
+}
+
+/* talk to the target and set things up */
+static int nds32_v3m_examine(struct target *target)
+{
+	struct nds32_v3m_common *nds32_v3m = target_to_nds32_v3m(target);
+	struct nds32 *nds32 = &(nds32_v3m->nds32);
+	struct aice_port_s *aice = target_to_aice(target);
+
+	if (!target_was_examined(target)) {
+		CHECK_RETVAL(nds32_edm_config(nds32));
+
+		if (nds32->reset_halt_as_examine)
+			CHECK_RETVAL(nds32_reset_halt(nds32));
+	}
+
+	uint32_t edm_cfg;
+	aice_read_debug_reg(aice, NDS_EDM_SR_EDM_CFG, &edm_cfg);
+
+	/* get the number of hardware breakpoints */
+	nds32_v3m->n_hbr = (edm_cfg & 0x7) + 1;
+	nds32_v3m->used_n_wp = 0;
+
+	/* get the number of hardware watchpoints */
+	/* If the WP field is hardwired to zero, it means this is a
+	 * simple breakpoint.  Otherwise, if the WP field is writable
+	 * then it means this is a regular watchpoints. */
+	nds32_v3m->n_hwp = 0;
+	for (int32_t i = 0 ; i < nds32_v3m->n_hbr ; i++) {
+		/** check the hardware breakpoint is simple or not */
+		uint32_t tmp_value;
+		aice_write_debug_reg(aice, NDS_EDM_SR_BPC0 + i, 0x1);
+		aice_read_debug_reg(aice, NDS_EDM_SR_BPC0 + i, &tmp_value);
+
+		if (tmp_value)
+			nds32_v3m->n_hwp++;
+	}
+	/* hardware breakpoint is inserted from high index to low index */
+	nds32_v3m->next_hbr_index = nds32_v3m->n_hbr - 1;
+	/* hardware watchpoint is inserted from low index to high index */
+	nds32_v3m->next_hwp_index = 0;
+
+	LOG_INFO("%s: total hardware breakpoint %d (simple breakpoint %d)",
+			target_name(target), nds32_v3m->n_hbr, nds32_v3m->n_hbr - nds32_v3m->n_hwp);
+	LOG_INFO("%s: total hardware watchpoint %d", target_name(target), nds32_v3m->n_hwp);
+
+	nds32->target->state = TARGET_RUNNING;
+	nds32->target->debug_reason = DBG_REASON_NOTHALTED;
+
+	target_set_examined(target);
+
+	return ERROR_OK;
+}
+
+/** Holds methods for NDS32 V3m targets. */
+struct target_type nds32_v3m_target = {
+	.name = "nds32_v3m",
+
+	.poll = nds32_poll,
+	.arch_state = nds32_arch_state,
+
+	.target_request_data = nds32_v3_target_request_data,
+
+	.halt = nds32_halt,
+	.resume = nds32_resume,
+	.step = nds32_step,
+
+	.assert_reset = nds32_assert_reset,
+	.deassert_reset = nds32_v3m_deassert_reset,
+	.soft_reset_halt = nds32_v3_soft_reset_halt,
+
+	/* register access */
+	.get_gdb_reg_list = nds32_get_gdb_reg_list,
+
+	/* memory access */
+	.read_buffer = nds32_v3_read_buffer,
+	.write_buffer = nds32_v3_write_buffer,
+	.read_memory = nds32_v3_read_memory,
+	.write_memory = nds32_v3_write_memory,
+
+	.checksum_memory = nds32_v3_checksum_memory,
+
+	/* breakpoint/watchpoint */
+	.add_breakpoint = nds32_v3m_add_breakpoint,
+	.remove_breakpoint = nds32_v3m_remove_breakpoint,
+	.add_watchpoint = nds32_v3m_add_watchpoint,
+	.remove_watchpoint = nds32_v3m_remove_watchpoint,
+
+	/* MMU */
+	.mmu = nds32_mmu,
+	.virt2phys = nds32_virtual_to_physical,
+	.read_phys_memory = nds32_read_phys_memory,
+	.write_phys_memory = nds32_write_phys_memory,
+
+	.run_algorithm = nds32_v3_run_algorithm,
+
+	.commands = nds32_command_handlers,
+	.target_create = nds32_v3m_target_create,
+	.init_target = nds32_v3_init_target,
+	.examine = nds32_v3m_examine,
+};

src/target/nds32_v3m.h

@@ -0,0 +1,53 @@
+/***************************************************************************
+ *   Copyright (C) 2013 Andes Technology                                   *
+ *   Hsiangkai Wang <hkwang@andestech.com>                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+#ifndef __NDS32_V3M_H__
+#define __NDS32_V3M_H__
+
+#include "nds32.h"
+
+struct nds32_v3m_common {
+	struct nds32 nds32;
+
+	/** number of hardware breakpoints */
+	int32_t n_hbr;
+
+	/** number of hardware watchpoints */
+	int32_t n_hwp;
+
+	/** number of used hardware watchpoints */
+	int32_t used_n_wp;
+
+	/** next hardware breakpoint index */
+	/** for simple breakpoints, hardware breakpoints are inserted
+	 * from high index to low index */
+	int32_t next_hbr_index;
+
+	/** next hardware watchpoint index */
+	/** increase from low index to high index */
+	int32_t next_hwp_index;
+};
+
+static inline struct nds32_v3m_common *target_to_nds32_v3m(struct target *target)
+{
+	return container_of(target->arch_info, struct nds32_v3m_common, nds32);
+}
+
+
+#endif	/* __NDS32_V3M_H__ */

src/target/target.c

@@ -89,6 +89,9 @@ extern struct target_type dsp5680xx_target;
 extern struct target_type testee_target;
 extern struct target_type avr32_ap7k_target;
 extern struct target_type hla_target;
+extern struct target_type nds32_v2_target;
+extern struct target_type nds32_v3_target;
+extern struct target_type nds32_v3m_target;
 
 static struct target_type *target_types[] = {
 	&arm7tdmi_target,
@@ -113,6 +116,9 @@ static struct target_type *target_types[] = {
 	&testee_target,
 	&avr32_ap7k_target,
 	&hla_target,
+	&nds32_v2_target,
+	&nds32_v3_target,
+	&nds32_v3m_target,
 	NULL,
 };
 

tcl/board/nds32_xc5.cfg

@@ -0,0 +1,5 @@
+set _CPUTAPID 0x1000063d
+set _CHIPNAME nds32
+source [find target/nds32v3.cfg]
+
+jtag init

tcl/target/nds32v2.cfg

@@ -0,0 +1,10 @@
+#
+# Andes Core
+#
+# http://www.andestech.com
+#
+
+jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME nds32_v2 -endian little -chain-position $_TARGETNAME

tcl/target/nds32v3.cfg

@@ -0,0 +1,10 @@
+#
+# Andes Core
+#
+# http://www.andestech.com
+#
+
+jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME nds32_v3 -endian little -chain-position $_TARGETNAME

tcl/target/nds32v3m.cfg

@@ -0,0 +1,10 @@
+#
+# Andes Core
+#
+# http://www.andestech.com
+#
+
+jtag newtap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME nds32_v3m -endian little -chain-position $_TARGETNAME