arm_adi_v5: move in a separate function devtype decode/display
For readability, move in a separate function the decoding and the display of devtype register. The function will be reused with ADIv6. Split from change https://review.openocd.org/6077/ Change-Id: I7a26a2c9759d5db5f9acfae5c169b90b3deb2f18 Signed-off-by: Kevin Burke <kevinb@os.amperecomputing.com> Signed-off-by: Daniel Goehring <dgoehrin@os.amperecomputing.com> Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6448 Tested-by: jenkins Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
This commit is contained in:
Kevin Burke
Antonio Borneo
parent
ddbc13a6f2
commit
cf6909a57c
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@ -1227,120 +1227,11 @@ static const struct {
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{ ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
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{ ANY_ID, 0x343, "TI DAPCTL", "", }, /* from OMAP3 memmap */
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};
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};
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static int dap_rom_display(struct command_invocation *cmd,
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static int dap_devtype_display(struct command_invocation *cmd, uint32_t devtype)
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struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
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{
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{
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int retval;
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uint64_t pid;
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uint32_t cid;
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char tabs[16] = "";
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if (depth > 16) {
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command_print(cmd, "\tTables too deep");
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return ERROR_FAIL;
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}
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if (depth)
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snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
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target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull;
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command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_addr);
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retval = dap_read_part_id(ap, base_addr, &cid, &pid);
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if (retval != ERROR_OK) {
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command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
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return ERROR_OK; /* Don't abort recursion */
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}
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if (!is_valid_arm_cs_cidr(cid)) {
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command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
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return ERROR_OK; /* Don't abort recursion */
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}
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/* component may take multiple 4K pages */
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uint32_t size = ARM_CS_PIDR_SIZE(pid);
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if (size > 0)
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command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size);
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command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
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uint8_t class = (cid & ARM_CS_CIDR_CLASS_MASK) >> ARM_CS_CIDR_CLASS_SHIFT;
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uint16_t part_num = ARM_CS_PIDR_PART(pid);
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uint16_t designer_id = ARM_CS_PIDR_DESIGNER(pid);
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if (pid & ARM_CS_PIDR_JEDEC) {
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/* JEP106 code */
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command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
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designer_id, jep106_manufacturer(designer_id));
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} else {
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/* Legacy ASCII ID, clear invalid bits */
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designer_id &= 0x7f;
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command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
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designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
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}
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/* default values to be overwritten upon finding a match */
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const char *type = "Unrecognized";
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const char *full = "";
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/* search dap_partnums[] array for a match */
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for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
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if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
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continue;
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if (dap_partnums[entry].part_num != part_num)
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continue;
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type = dap_partnums[entry].type;
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full = dap_partnums[entry].full;
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break;
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}
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command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
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command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
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if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
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uint32_t memtype;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C1_MEMTYPE, &memtype);
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if (retval != ERROR_OK)
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return retval;
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if (memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
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command_print(cmd, "\t\tMEMTYPE system memory present on bus");
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else
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command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
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/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
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for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
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uint32_t romentry;
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retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
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if (retval != ERROR_OK)
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return retval;
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command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
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tabs, entry_offset, romentry);
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if (romentry & ARM_CS_ROMENTRY_PRESENT) {
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/* Recurse. "romentry" is signed */
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retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK),
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depth + 1);
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if (retval != ERROR_OK)
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return retval;
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} else if (romentry != 0) {
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command_print(cmd, "\t\tComponent not present");
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} else {
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command_print(cmd, "\t%s\tEnd of ROM table", tabs);
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break;
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}
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}
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} else if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
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const char *major = "Reserved", *subtype = "Reserved";
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const char *major = "Reserved", *subtype = "Reserved";
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const unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
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uint32_t devtype;
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const unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVTYPE, &devtype);
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if (retval != ERROR_OK)
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return retval;
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unsigned int minor = (devtype & ARM_CS_C9_DEVTYPE_SUB_MASK) >> ARM_CS_C9_DEVTYPE_SUB_SHIFT;
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unsigned int devtype_major = (devtype & ARM_CS_C9_DEVTYPE_MAJOR_MASK) >> ARM_CS_C9_DEVTYPE_MAJOR_SHIFT;
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switch (devtype_major) {
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switch (devtype_major) {
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case 0:
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case 0:
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major = "Miscellaneous";
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major = "Miscellaneous";
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@ -1477,6 +1368,124 @@ static int dap_rom_display(struct command_invocation *cmd,
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command_print(cmd, "\t\tType is 0x%02x, %s, %s",
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command_print(cmd, "\t\tType is 0x%02x, %s, %s",
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devtype & ARM_CS_C9_DEVTYPE_MASK,
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devtype & ARM_CS_C9_DEVTYPE_MASK,
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major, subtype);
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major, subtype);
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return ERROR_OK;
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}
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static int dap_rom_display(struct command_invocation *cmd,
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struct adiv5_ap *ap, target_addr_t dbgbase, int depth)
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{
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int retval;
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uint64_t pid;
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uint32_t cid;
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char tabs[16] = "";
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if (depth > 16) {
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command_print(cmd, "\tTables too deep");
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return ERROR_FAIL;
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}
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if (depth)
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snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
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target_addr_t base_addr = dbgbase & 0xFFFFFFFFFFFFF000ull;
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command_print(cmd, "\t\tComponent base address " TARGET_ADDR_FMT, base_addr);
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retval = dap_read_part_id(ap, base_addr, &cid, &pid);
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if (retval != ERROR_OK) {
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command_print(cmd, "\t\tCan't read component, the corresponding core might be turned off");
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return ERROR_OK; /* Don't abort recursion */
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}
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if (!is_valid_arm_cs_cidr(cid)) {
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command_print(cmd, "\t\tInvalid CID 0x%08" PRIx32, cid);
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return ERROR_OK; /* Don't abort recursion */
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}
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/* component may take multiple 4K pages */
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uint32_t size = ARM_CS_PIDR_SIZE(pid);
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if (size > 0)
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command_print(cmd, "\t\tStart address " TARGET_ADDR_FMT, base_addr - 0x1000 * size);
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command_print(cmd, "\t\tPeripheral ID 0x%010" PRIx64, pid);
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uint8_t class = (cid & ARM_CS_CIDR_CLASS_MASK) >> ARM_CS_CIDR_CLASS_SHIFT;
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uint16_t part_num = ARM_CS_PIDR_PART(pid);
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uint16_t designer_id = ARM_CS_PIDR_DESIGNER(pid);
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if (pid & ARM_CS_PIDR_JEDEC) {
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/* JEP106 code */
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command_print(cmd, "\t\tDesigner is 0x%03" PRIx16 ", %s",
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designer_id, jep106_manufacturer(designer_id));
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} else {
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/* Legacy ASCII ID, clear invalid bits */
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designer_id &= 0x7f;
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command_print(cmd, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
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designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
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}
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/* default values to be overwritten upon finding a match */
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const char *type = "Unrecognized";
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const char *full = "";
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/* search dap_partnums[] array for a match */
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for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
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if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
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continue;
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if (dap_partnums[entry].part_num != part_num)
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continue;
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type = dap_partnums[entry].type;
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full = dap_partnums[entry].full;
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break;
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}
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command_print(cmd, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
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command_print(cmd, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
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if (class == ARM_CS_CLASS_0X1_ROM_TABLE) {
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uint32_t memtype;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C1_MEMTYPE, &memtype);
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if (retval != ERROR_OK)
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return retval;
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if (memtype & ARM_CS_C1_MEMTYPE_SYSMEM_MASK)
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command_print(cmd, "\t\tMEMTYPE system memory present on bus");
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else
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command_print(cmd, "\t\tMEMTYPE system memory not present: dedicated debug bus");
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/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
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for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
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uint32_t romentry;
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retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
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if (retval != ERROR_OK)
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return retval;
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command_print(cmd, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
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tabs, entry_offset, romentry);
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if (romentry & ARM_CS_ROMENTRY_PRESENT) {
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/* Recurse. "romentry" is signed */
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retval = dap_rom_display(cmd, ap, base_addr + (int32_t)(romentry & ARM_CS_ROMENTRY_OFFSET_MASK),
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depth + 1);
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if (retval != ERROR_OK)
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return retval;
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} else if (romentry != 0) {
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command_print(cmd, "\t\tComponent not present");
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} else {
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command_print(cmd, "\t%s\tEnd of ROM table", tabs);
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break;
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}
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}
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} else if (class == ARM_CS_CLASS_0X9_CS_COMPONENT) {
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uint32_t devtype;
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retval = mem_ap_read_atomic_u32(ap, base_addr + ARM_CS_C9_DEVTYPE, &devtype);
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if (retval != ERROR_OK)
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return retval;
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retval = dap_devtype_display(cmd, devtype);
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if (retval != ERROR_OK)
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return retval;
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/* REVISIT also show ARM_CS_C9_DEVID */
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/* REVISIT also show ARM_CS_C9_DEVID */
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}
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}
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