riscv: Added several compliance test items
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mwachs5
Megan Wachs
parent
95ee7975ea
commit
ccc605158a
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@ -2111,12 +2111,167 @@ void riscv013_clear_abstract_error(struct target *target)
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dmi_write(target, DMI_ABSTRACTCS, acs);
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}
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#define COMPLIANCE_TEST(b, message) { \
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int pass = 0; \
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if (b) { \
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pass = 1; \
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passed_tests ++; \
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} \
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LOG_INFO("%s test %d (%s)\n", (pass) ? "PASSED":"FAILED", total_tests, message); \
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total_tests ++; \
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}
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int riscv013_test_compliance(struct target *target) {
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LOG_INFO("Testing Compliance against RISC-V Debug Spec v0.13");
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if (!riscv_rtos_enabled(target)) {
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LOG_ERROR("Please run with -rtos riscv to run compliance test.");
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return ERROR_FAIL;
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}
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int total_tests = 0;
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int passed_tests = 0;
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uint32_t dmcontrol_orig = dmi_read(target, DMI_DMCONTROL);
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uint32_t dmcontrol;
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uint32_t testvar;
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTSEL, RISCV_MAX_HARTS-1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmcontrol = dmi_read(target, DMI_DMCONTROL);
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COMPLIANCE_TEST(get_field(dmcontrol, DMI_DMCONTROL_HARTSEL) == (RISCV_MAX_HARTS-1), "DMCONTROL.hartsel should hold MAX_HARTS - 1");
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTSEL, 0);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmcontrol = dmi_read(target, DMI_DMCONTROL);
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COMPLIANCE_TEST(get_field(dmcontrol, DMI_DMCONTROL_HARTSEL) == 0, "DMCONTROL.hartsel should hold Hart ID 0");
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// hartreset
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmcontrol = dmi_read(target, DMI_DMCONTROL);
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testvar = get_field(dmcontrol, DMI_DMCONTROL_HARTRESET);
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HARTRESET, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmcontrol = dmi_read(target, DMI_DMCONTROL);
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HARTRESET)) == 0), "DMCONTROL.hartreset can be 0 or RW.");
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// hasel
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmcontrol = dmi_read(target, DMI_DMCONTROL);
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testvar = get_field(dmcontrol, DMI_DMCONTROL_HASEL);
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dmcontrol = set_field(dmcontrol_orig, DMI_DMCONTROL_HASEL, 1);
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dmi_write(target, DMI_DMCONTROL, dmcontrol);
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dmcontrol = dmi_read(target, DMI_DMCONTROL);
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COMPLIANCE_TEST(((testvar == 0) || (get_field(dmcontrol, DMI_DMCONTROL_HASEL)) == 0), "DMCONTROL.hasel can be 0 or RW.");
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//TODO: test that hamask registers exist if hasel does.
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// TODO: ndmreset
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// TODO: dmactive
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// haltreq
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riscv_halt_all_harts(target);
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// TODO: resumereq
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// HARTINFO: Read-Only. This is per-hart, so need to adjust hartsel.
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for (uint32_t hartsel = 0; hartsel < riscv_count_harts(target); hartsel++){
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riscv_set_current_hartid(target, hartsel);
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uint32_t dmstatus = dmi_read(target, DMI_DMSTATUS);
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if (get_field(dmstatus, DMI_DMSTATUS_ANYNONEXISTENT)) {
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break;
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}
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uint32_t hartinfo = dmi_read(target, DMI_HARTINFO);
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dmi_write (target, DMI_HARTINFO, ~hartinfo);
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COMPLIANCE_TEST((dmi_read(target, DMI_HARTINFO) == hartinfo), "DMHARTINFO should be Read-Only.");
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uint32_t nscratch = get_field(hartinfo, DMI_HARTINFO_NSCRATCH);
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for (int d = 0; d < nscratch; d++) {
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for (testvar = 0x00112233; testvar != 0xDEAD ; testvar = testvar == 0x00112233 ? ~testvar : 0xDEAD ) {
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struct riscv_program program32;
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riscv_program_init(&program32, target);
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riscv_addr_t addr_in = riscv_program_alloc_x(&program32);
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riscv_addr_t addr_out = riscv_program_alloc_x(&program32);
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riscv_program_write_ram(&program32, addr_in, testvar);
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if (riscv_xlen(target) > 32) {
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riscv_program_write_ram(&program32, addr_in + 4, testvar);
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}
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riscv_program_lx(&program32, GDB_REGNO_S0, addr_in);
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riscv_program_csrrw(&program32, GDB_REGNO_S0, GDB_REGNO_S0, GDB_REGNO_DSCRATCH);
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riscv_program_csrrw(&program32, GDB_REGNO_S1, GDB_REGNO_S1, GDB_REGNO_DSCRATCH);
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riscv_program_sx(&program32, GDB_REGNO_S1, addr_out);
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riscv_program_fence(&program32);
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COMPLIANCE_TEST(riscv_program_exec(&program32, target) == ERROR_OK, "Accessing DSCRATCH with program buffer should succeed.");
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COMPLIANCE_TEST(riscv_program_read_ram(&program32, addr_out) == testvar, "All DSCRATCH registers in HARTINFO must be R/W.");
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if (riscv_xlen(target) > 32) {
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COMPLIANCE_TEST(riscv_program_read_ram(&program32, addr_out + 4) == testvar, "All DSCRATCH registers in HARTINFO must be R/W.");
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}
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}
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}
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// TODO: dataaccess
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if (get_field(hartinfo, DMI_HARTINFO_DATAACCESS)) {
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// TODO: Shadowed in memory map.
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// TODO: datasize
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// TODO: dataaddr
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} else {
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// TODO: Shadowed in CSRs.
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// TODO: datasize
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// TODO: dataaddr
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}
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}
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// HALTSUM
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uint32_t expected_haltsum = 0;
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for (unsigned int i = 0; i < riscv_count_harts(target); i +=32){
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expected_haltsum |= (1 << (i / 32));
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}
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COMPLIANCE_TEST(dmi_read(target, DMI_HALTSUM) == expected_haltsum, "HALTSUM should report all halted harts");
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// TODO: HAWINDOWSEL
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// TODO: HAWINDOW
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// ABSTRACTCS
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uint32_t abstractcs = dmi_read(target, DMI_ABSTRACTCS);
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// Check that all reported Data Words are really R/W
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for (int invert = 0; invert < 2; invert++) {
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i ++){
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testvar = (i + 1) * 0x11111111;
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if (invert) {testvar = ~testvar;}
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dmi_write(target, DMI_DATA0 + i, testvar);
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}
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT); i ++){
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testvar = (i + 1) * 0x11111111;
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if (invert) {testvar = ~testvar;}
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COMPLIANCE_TEST(dmi_read(target, DMI_DATA0 + i) == testvar, "All reported DATA words must be R/W");
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}
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}
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// Check that all reported ProgBuf words are really R/W
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for (int invert = 0; invert < 2; invert++) {
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGSIZE); i ++){
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testvar = (i + 1) * 0x11111111;
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if (invert) {testvar = ~testvar;}
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dmi_write(target, DMI_PROGBUF0 + i, testvar);
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}
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for (unsigned int i = 0; i < get_field(abstractcs, DMI_ABSTRACTCS_PROGSIZE); i ++){
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testvar = (i + 1) * 0x11111111;
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if (invert) {testvar = ~testvar;}
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COMPLIANCE_TEST(dmi_read(target, DMI_PROGBUF0 + i) == testvar, "All reported PROGBUF words must be R/W");
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}
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}
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// TODO: Cause and clear all error types
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LOG_INFO("PASSED %d of %d TESTS\n", passed_tests, total_tests);
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if (total_tests == passed_tests) {
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