ARM: streamline register init
Combine register names with other per-register data into a single template structure. This saves space, and makes it easier to change how registers get handled (by shrinking the number of places that care about cache indices). Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
parent
e3ed06579b
commit
cbc13187c3
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@ -36,26 +36,6 @@
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#include "register.h"
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static const char *armv4_5_core_reg_list[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "sp_usr", "lr_usr", "pc",
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"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq",
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"sp_irq", "lr_irq",
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"sp_svc", "lr_svc",
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"sp_abt", "lr_abt",
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"sp_und", "lr_und",
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"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
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"sp_mon", "lr_mon", "spsr_mon",
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};
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static const uint8_t arm_usr_indices[17] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
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};
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@ -230,58 +210,90 @@ char* armv4_5_state_strings[] =
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"ARM", "Thumb", "Jazelle", "ThumbEE",
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};
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static const struct armv4_5_core_reg armv4_5_core_reg_list_arch_info[] =
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{
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{0, ARMV4_5_MODE_ANY, NULL, NULL},
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{1, ARMV4_5_MODE_ANY, NULL, NULL},
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{2, ARMV4_5_MODE_ANY, NULL, NULL},
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{3, ARMV4_5_MODE_ANY, NULL, NULL},
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{4, ARMV4_5_MODE_ANY, NULL, NULL},
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{5, ARMV4_5_MODE_ANY, NULL, NULL},
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{6, ARMV4_5_MODE_ANY, NULL, NULL},
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{7, ARMV4_5_MODE_ANY, NULL, NULL},
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{8, ARMV4_5_MODE_ANY, NULL, NULL},
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{9, ARMV4_5_MODE_ANY, NULL, NULL},
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{10, ARMV4_5_MODE_ANY, NULL, NULL},
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{11, ARMV4_5_MODE_ANY, NULL, NULL},
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{12, ARMV4_5_MODE_ANY, NULL, NULL},
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{13, ARMV4_5_MODE_USR, NULL, NULL},
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{14, ARMV4_5_MODE_USR, NULL, NULL},
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{15, ARMV4_5_MODE_ANY, NULL, NULL},
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/* Templates for ARM core registers.
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*
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* NOTE: offsets in this table are coupled to the arm_mode_data
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* table above, the armv4_5_core_reg_map array below, and also to
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* the ARMV4_5_*PSR* symols.
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*/
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static const struct {
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/* The name is used for e.g. the "regs" command. */
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const char *name;
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{8, ARMV4_5_MODE_FIQ, NULL, NULL},
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{9, ARMV4_5_MODE_FIQ, NULL, NULL},
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{10, ARMV4_5_MODE_FIQ, NULL, NULL},
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{11, ARMV4_5_MODE_FIQ, NULL, NULL},
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{12, ARMV4_5_MODE_FIQ, NULL, NULL},
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{13, ARMV4_5_MODE_FIQ, NULL, NULL},
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{14, ARMV4_5_MODE_FIQ, NULL, NULL},
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/* The {cookie, mode} tuple uniquely identifies one register.
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* In a given mode, cookies 0..15 map to registers R0..R15,
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* with R13..R15 usually called SP, LR, PC.
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*
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* MODE_ANY is used as *input* to the mapping, and indicates
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* various special cases (sigh) and errors.
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*
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* Cookie 16 is (currently) confusing, since it indicates
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* CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
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* (Exception modes have both CPSR and SPSR registers ...)
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*/
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unsigned cookie;
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enum armv4_5_mode mode;
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} arm_core_regs[] = {
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{ .name = "r0", .cookie = 0, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r1", .cookie = 1, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r2", .cookie = 2, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r3", .cookie = 3, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r4", .cookie = 4, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r5", .cookie = 5, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r6", .cookie = 6, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r7", .cookie = 7, .mode = ARMV4_5_MODE_ANY, },
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{13, ARMV4_5_MODE_IRQ, NULL, NULL},
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{14, ARMV4_5_MODE_IRQ, NULL, NULL},
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/* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
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* them as MODE_ANY creates special cases.
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*/
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{ .name = "r8", .cookie = 8, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r9", .cookie = 9, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r10", .cookie = 10, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r11", .cookie = 11, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "r12", .cookie = 12, .mode = ARMV4_5_MODE_ANY, },
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{13, ARMV4_5_MODE_SVC, NULL, NULL},
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{14, ARMV4_5_MODE_SVC, NULL, NULL},
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/* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
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{ .name = "sp_usr", .cookie = 13, .mode = ARMV4_5_MODE_USR, },
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{ .name = "lr_usr", .cookie = 14, .mode = ARMV4_5_MODE_USR, },
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{13, ARMV4_5_MODE_ABT, NULL, NULL},
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{14, ARMV4_5_MODE_ABT, NULL, NULL},
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{ .name = "pc", .cookie = 15, .mode = ARMV4_5_MODE_ANY, },
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{13, ARMV4_5_MODE_UND, NULL, NULL},
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{14, ARMV4_5_MODE_UND, NULL, NULL},
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{ .name = "r8_fiq", .cookie = 8, .mode = ARMV4_5_MODE_FIQ, },
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{ .name = "r9_fiq", .cookie = 9, .mode = ARMV4_5_MODE_FIQ, },
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{ .name = "r10_fiq", .cookie = 10, .mode = ARMV4_5_MODE_FIQ, },
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{ .name = "r11_fiq", .cookie = 11, .mode = ARMV4_5_MODE_FIQ, },
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{ .name = "r12_fiq", .cookie = 12, .mode = ARMV4_5_MODE_FIQ, },
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{16, ARMV4_5_MODE_ANY, NULL, NULL},
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{16, ARMV4_5_MODE_FIQ, NULL, NULL},
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{16, ARMV4_5_MODE_IRQ, NULL, NULL},
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{16, ARMV4_5_MODE_SVC, NULL, NULL},
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{16, ARMV4_5_MODE_ABT, NULL, NULL},
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{16, ARMV4_5_MODE_UND, NULL, NULL},
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{ .name = "lr_fiq", .cookie = 13, .mode = ARMV4_5_MODE_FIQ, },
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{ .name = "sp_fiq", .cookie = 14, .mode = ARMV4_5_MODE_FIQ, },
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{13, ARM_MODE_MON, NULL, NULL},
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{14, ARM_MODE_MON, NULL, NULL},
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{16, ARM_MODE_MON, NULL, NULL},
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{ .name = "lr_irq", .cookie = 13, .mode = ARMV4_5_MODE_IRQ, },
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{ .name = "sp_irq", .cookie = 14, .mode = ARMV4_5_MODE_IRQ, },
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{ .name = "lr_svc", .cookie = 13, .mode = ARMV4_5_MODE_SVC, },
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{ .name = "sp_svc", .cookie = 14, .mode = ARMV4_5_MODE_SVC, },
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{ .name = "lr_abt", .cookie = 13, .mode = ARMV4_5_MODE_ABT, },
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{ .name = "sp_abt", .cookie = 14, .mode = ARMV4_5_MODE_ABT, },
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{ .name = "lr_und", .cookie = 13, .mode = ARMV4_5_MODE_UND, },
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{ .name = "sp_und", .cookie = 14, .mode = ARMV4_5_MODE_UND, },
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{ .name = "cpsr", .cookie = 16, .mode = ARMV4_5_MODE_ANY, },
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{ .name = "spsr_fiq", .cookie = 16, .mode = ARMV4_5_MODE_FIQ, },
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{ .name = "spsr_irq", .cookie = 16, .mode = ARMV4_5_MODE_IRQ, },
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{ .name = "spsr_svc", .cookie = 16, .mode = ARMV4_5_MODE_SVC, },
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{ .name = "spsr_abt", .cookie = 16, .mode = ARMV4_5_MODE_ABT, },
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{ .name = "spsr_und", .cookie = 16, .mode = ARMV4_5_MODE_UND, },
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{ .name = "lr_mon", .cookie = 13, .mode = ARM_MODE_MON, },
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{ .name = "sp_mon", .cookie = 14, .mode = ARM_MODE_MON, },
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{ .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, },
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};
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/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
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/* map core mode (USR, FIQ, ...) and register number to
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* indices into the register cache
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*/
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const int armv4_5_core_reg_map[8][17] =
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{
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{ /* USR */
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@ -442,7 +454,7 @@ int armv4_5_invalidate_core_regs(struct target *target)
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struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *armv4_5_common)
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{
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int num_regs = ARRAY_SIZE(armv4_5_core_reg_list_arch_info);
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int num_regs = ARRAY_SIZE(arm_core_regs);
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struct reg_cache *cache = malloc(sizeof(struct reg_cache));
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struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
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struct armv4_5_core_reg *arch_info = calloc(num_regs,
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@ -464,16 +476,18 @@ struct reg_cache* armv4_5_build_reg_cache(struct target *target, struct arm *arm
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for (i = 0; i < num_regs; i++)
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{
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/* Skip registers this core doesn't expose */
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if (armv4_5_core_reg_list_arch_info[i].mode == ARM_MODE_MON
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if (arm_core_regs[i].mode == ARM_MODE_MON
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&& armv4_5_common->core_type != ARM_MODE_MON)
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continue;
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/* REVISIT handle Cortex-M, which only shadows R13/SP */
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arch_info[i] = armv4_5_core_reg_list_arch_info[i];
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arch_info[i].num = arm_core_regs[i].cookie;
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arch_info[i].mode = arm_core_regs[i].mode;
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arch_info[i].target = target;
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arch_info[i].armv4_5_common = armv4_5_common;
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reg_list[i].name = (char *) armv4_5_core_reg_list[i];
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reg_list[i].name = (char *) arm_core_regs[i].name;
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reg_list[i].size = 32;
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reg_list[i].value = calloc(1, 4);
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reg_list[i].type = &arm_reg_type;
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