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target/mips: rename CamelCase symbols 

No major cross dependencies, mostly changes internal to each
file/function.

Change-Id: Iec58f7fe1d65f621ae0c841b5e25ef222885792b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6341
Tested-by: jenkins
Reviewed-by: Marc Schink <dev@zapb.de>
Reviewed-by: Xiang W <wxjstz@126.com>
This commit is contained in:
Antonio Borneo 2021-04-27 18:50:34 +02:00
parent 12d6f6d804
commit cbaccc5c3e
5 changed files with 35 additions and 35 deletions
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24
src/target/mips32.h
View File

@ -248,7 +248,7 @@ struct mips32_algorithm {
/*MICRO MIPS INSTRUCTIONS, see doc MD00582 */ /*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
#define POOL32A 0X00u #define POOL32A 0X00u
#define POOL32AXf 0x3Cu #define POOL32AXF 0x3Cu
#define POOL32B 0x08u #define POOL32B 0x08u
#define POOL32I 0x10u #define POOL32I 0x10u
#define MMIPS32_OP_ADDI 0x04u #define MMIPS32_OP_ADDI 0x04u
@ -300,24 +300,24 @@ struct mips32_algorithm {
#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off) #define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
#define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1)))) #define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXf) #define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXF)
#define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off) #define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
#define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off) #define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
#define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off) #define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
#define MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val) #define MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val)
#define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off) #define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXf) #define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXF)
#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXf) #define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXF)
#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXf) #define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXF)
#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXf) #define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXF)
#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXf) #define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXF)
#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXf) #define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXF)
#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN) #define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
#define MMIPS32_NOP 0 #define MMIPS32_NOP 0
#define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val) #define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXf) #define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXF)
#define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off) #define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
#define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off) #define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
#define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off) #define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
@ -327,7 +327,7 @@ struct mips32_algorithm {
#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off) #define MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off)
#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL) #define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
#define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val) #define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXf) */ #define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXF) */
#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR) #define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
#define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val) #define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
@ -336,8 +336,8 @@ struct mips32_algorithm {
/* ejtag specific instructions */ /* ejtag specific instructions */
#define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXf) */ #define MMIPS32_DRET 0x0000E37Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x38D, POOL32AXF) */
#define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXf) */ #define MMIPS32_SDBBP 0x0000DB7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1BD, POOL32AXF) */
#define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */ #define MMIPS16_SDBBP 0x46C0u /* POOL16C instr */
/* instruction code with isa selection */ /* instruction code with isa selection */

8
src/target/mips_ejtag.c
View File

@ -296,8 +296,8 @@ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS; ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS;
ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS; ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS;
ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP; ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAN_STEP;
ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP; ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAN_STEP;
} else { } else {
ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS; ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS;
ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0; ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0;
@ -312,8 +312,8 @@ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS; ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS;
ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS; ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS;
ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP; ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAN_STEP;
ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP; ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAN_STEP;
} }
} }

18
src/target/mips_ejtag.h
View File

@ -147,33 +147,33 @@
#define EJTAG_V20_IBA0 0xFF300100 #define EJTAG_V20_IBA0 0xFF300100
#define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */ #define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */
#define EJTAG_V20_IBM_OFFS 0x8 #define EJTAG_V20_IBM_OFFS 0x8
#define EJTAG_V20_IBAn_STEP 0x10 /* Offset for next channel */ #define EJTAG_V20_IBAN_STEP 0x10 /* Offset for next channel */
#define EJTAG_V20_DBS 0xFF300008 #define EJTAG_V20_DBS 0xFF300008
#define EJTAG_V20_DBA0 0xFF300200 #define EJTAG_V20_DBA0 0xFF300200
#define EJTAG_V20_DBC_OFFS 0x4 #define EJTAG_V20_DBC_OFFS 0x4
#define EJTAG_V20_DBM_OFFS 0x8 #define EJTAG_V20_DBM_OFFS 0x8
#define EJTAG_V20_DBV_OFFS 0xc #define EJTAG_V20_DBV_OFFS 0xc
#define EJTAG_V20_DBAn_STEP 0x10 #define EJTAG_V20_DBAN_STEP 0x10
#define EJTAG_V25_IBS 0xFF301000 #define EJTAG_V25_IBS 0xFF301000
#define EJTAG_V25_IBA0 0xFF301100 #define EJTAG_V25_IBA0 0xFF301100
#define EJTAG_V25_IBM_OFFS 0x8 #define EJTAG_V25_IBM_OFFS 0x8
#define EJTAG_V25_IBASID_OFFS 0x10 #define EJTAG_V25_IBASID_OFFS 0x10
#define EJTAG_V25_IBC_OFFS 0x18 #define EJTAG_V25_IBC_OFFS 0x18
#define EJTAG_V25_IBAn_STEP 0x100 #define EJTAG_V25_IBAN_STEP 0x100
#define EJTAG_V25_DBS 0xFF302000 #define EJTAG_V25_DBS 0xFF302000
#define EJTAG_V25_DBA0 0xFF302100 #define EJTAG_V25_DBA0 0xFF302100
#define EJTAG_V25_DBM_OFFS 0x8 #define EJTAG_V25_DBM_OFFS 0x8
#define EJTAG_V25_DBASID_OFFS 0x10 #define EJTAG_V25_DBASID_OFFS 0x10
#define EJTAG_V25_DBC_OFFS 0x18 #define EJTAG_V25_DBC_OFFS 0x18
#define EJTAG_V25_DBV_OFFS 0x20 #define EJTAG_V25_DBV_OFFS 0x20
#define EJTAG_V25_DBAn_STEP 0x100 #define EJTAG_V25_DBAN_STEP 0x100
#define EJTAG_DBCn_NOSB (1 << 13) #define EJTAG_DBCN_NOSB (1 << 13)
#define EJTAG_DBCn_NOLB (1 << 12) #define EJTAG_DBCN_NOLB (1 << 12)
#define EJTAG_DBCn_BLM_MASK 0xff #define EJTAG_DBCN_BLM_MASK 0xff
#define EJTAG_DBCn_BLM_SHIFT 4 #define EJTAG_DBCN_BLM_SHIFT 4
#define EJTAG_DBCn_BE (1 << 0) #define EJTAG_DBCN_BE (1 << 0)
#define EJTAG_VERSION_20 0 #define EJTAG_VERSION_20 0
#define EJTAG_VERSION_25 1 #define EJTAG_VERSION_25 1

10
src/target/mips_m4k.c
View File

@ -880,8 +880,8 @@ static int mips_m4k_set_watchpoint(struct target *target,
* and exclude both load and store accesses from watchpoint * and exclude both load and store accesses from watchpoint
* condition evaluation * condition evaluation
*/ */
int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE | int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE |
(0xff << EJTAG_DBCn_BLM_SHIFT); (0xff << EJTAG_DBCN_BLM_SHIFT);
if (watchpoint->set) { if (watchpoint->set) {
LOG_WARNING("watchpoint already set"); LOG_WARNING("watchpoint already set");
@ -907,13 +907,13 @@ static int mips_m4k_set_watchpoint(struct target *target,
switch (watchpoint->rw) { switch (watchpoint->rw) {
case WPT_READ: case WPT_READ:
enable &= ~EJTAG_DBCn_NOLB; enable &= ~EJTAG_DBCN_NOLB;
break; break;
case WPT_WRITE: case WPT_WRITE:
enable &= ~EJTAG_DBCn_NOSB; enable &= ~EJTAG_DBCN_NOSB;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB); enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
break; break;
default: default:
LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");

10
src/target/mips_mips64.c
View File

@ -410,8 +410,8 @@ static int mips_mips64_set_watchpoint(struct target *target,
* and exclude both load and store accesses from watchpoint * and exclude both load and store accesses from watchpoint
* condition evaluation * condition evaluation
*/ */
int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE int enable = EJTAG_DBCN_NOSB | EJTAG_DBCN_NOLB | EJTAG_DBCN_BE
| (0xff << EJTAG_DBCn_BLM_SHIFT); | (0xff << EJTAG_DBCN_BLM_SHIFT);
if (watchpoint->set) { if (watchpoint->set) {
LOG_WARNING("watchpoint already set"); LOG_WARNING("watchpoint already set");
@ -438,13 +438,13 @@ static int mips_mips64_set_watchpoint(struct target *target,
switch (watchpoint->rw) { switch (watchpoint->rw) {
case WPT_READ: case WPT_READ:
enable &= ~EJTAG_DBCn_NOLB; enable &= ~EJTAG_DBCN_NOLB;
break; break;
case WPT_WRITE: case WPT_WRITE:
enable &= ~EJTAG_DBCn_NOSB; enable &= ~EJTAG_DBCN_NOSB;
break; break;
case WPT_ACCESS: case WPT_ACCESS:
enable &= ~(EJTAG_DBCn_NOLB | EJTAG_DBCn_NOSB); enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB);
break; break;
default: default:
LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");