- reworked file i/o. every fileaccess (target, flash, nand, in future configuration, too) should now go through the fileio subsystem
- added support for reading IHEX files (through fileio) - load/dump_binary renamed to the more generic load/dump_image <file> <address> ['bin'|'ihex'] - added NAND framework (preliminary) - added support for the LPC3180 SLC and MLC NAND controllers (preliminary) - fix initialization for parport - gw16012 fixes/cleanups - added EmbeddedICE version 7 (preliminary, reported on two LPC23xx devices so far) - added 'arm7_9 etm <target#>' configuration command to enable access to the ETM registers git-svn-id: svn://svn.berlios.de/openocd/trunk@132 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
parent
e0c2e30660
commit
cb58279653
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@ -1,5 +1,5 @@
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INCLUDES = -I$(top_srcdir)/src/helper -I$(top_srcdir)/src/jtag -I$(top_srcdir)/src/target $(all_includes)
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METASOURCES = AUTO
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noinst_LIBRARIES = libflash.a
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libflash_a_SOURCES = flash.c lpc2000.c cfi.c at91sam7.c str7x.c str9x.c
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noinst_HEADERS = flash.h lpc2000.h cfi.h at91sam7.h str7x.h str9x.h
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libflash_a_SOURCES = flash.c lpc2000.c cfi.c at91sam7.c str7x.c str9x.c nand.c lpc3180_nand_controller.c
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noinst_HEADERS = flash.h lpc2000.h cfi.h at91sam7.h str7x.h str9x.h nand.h lpc3180_nand_controller.h
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@ -34,6 +34,8 @@
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#include <sys/stat.h>
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#include <errno.h>
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#include <fileio.h>
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/* command handlers */
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int handle_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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int handle_flash_banks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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@ -486,24 +488,31 @@ int handle_flash_protect_command(struct command_context_s *cmd_ctx, char *cmd, c
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int handle_flash_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
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{
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FILE *binary;
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u32 offset;
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struct stat binary_stat;
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u32 binary_size;
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u8 *buffer;
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u32 buf_cnt;
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fileio_t file;
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fileio_image_t image_info;
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enum fileio_sec_type sec_type;
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duration_t duration;
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char *duration_text;
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int retval;
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flash_bank_t *p;
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struct timeval start, end, duration;
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gettimeofday(&start, NULL);
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if (argc < 3)
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{
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command_print(cmd_ctx, "usage: flash write <bank> <file> <offset>");
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command_print(cmd_ctx, "usage: flash write <bank> <file> <offset> [type]");
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return ERROR_OK;
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}
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duration_start_measure(&duration);
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fileio_identify_image_type(&sec_type, (argc == 4) ? args[3] : NULL);
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offset = strtoul(args[2], NULL, 0);
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p = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
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if (!p)
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@ -512,35 +521,20 @@ int handle_flash_write_command(struct command_context_s *cmd_ctx, char *cmd, cha
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return ERROR_OK;
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}
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if (stat(args[1], &binary_stat) == -1)
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image_info.base_address = strtoul(args[2], NULL, 0);
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image_info.has_start_address = 0;
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if (fileio_open(&file, args[1], FILEIO_READ,
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FILEIO_IMAGE, &image_info, sec_type) != ERROR_OK)
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{
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ERROR("couldn't stat() %s: %s", args[1], strerror(errno));
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command_print(cmd_ctx, "flash write error: %s", file.error_str);
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return ERROR_OK;
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}
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if (S_ISDIR(binary_stat.st_mode))
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{
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ERROR("%s is a directory", args[1]);
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command_print(cmd_ctx,"%s is a directory", args[1]);
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return ERROR_OK;
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}
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if (binary_stat.st_size == 0){
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ERROR("Empty file %s", args[1]);
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command_print(cmd_ctx,"Empty file %s", args[1]);
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return ERROR_OK;
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}
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if (!(binary = fopen(args[1], "rb")))
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{
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ERROR("couldn't open %s: %s", args[1], strerror(errno));
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command_print(cmd_ctx, "couldn't open %s", args[1]);
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return ERROR_OK;
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}
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binary_size = binary_stat.st_size;
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binary_size = file.size;
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buffer = malloc(binary_size);
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buf_cnt = fread(buffer, 1, binary_size, binary);
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fileio_read(&file, binary_size, buffer, &buf_cnt);
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if ((retval = p->driver->write(p, buffer, offset, buf_cnt)) != ERROR_OK)
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{
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@ -575,14 +569,14 @@ int handle_flash_write_command(struct command_context_s *cmd_ctx, char *cmd, cha
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}
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else
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{
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gettimeofday(&end, NULL);
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timeval_subtract(&duration, &end, &start);
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command_print(cmd_ctx, "wrote file %s to flash bank %i at offset 0x%8.8x in %is %ius", args[1], strtoul(args[0], NULL, 0), strtoul(args[2], NULL, 0), duration.tv_sec, duration.tv_usec);
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duration_stop_measure(&duration, &duration_text);
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command_print(cmd_ctx, "wrote file %s to flash bank %i at offset 0x%8.8x in %s",
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file.url, strtoul(args[0], NULL, 0), offset, duration_text);
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free(duration_text);
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}
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free(buffer);
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fclose(binary);
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fileio_close(&file);
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return ERROR_OK;
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}
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@ -0,0 +1,916 @@
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/***************************************************************************
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* Copyright (C) 2007 by Dominic Rath *
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* Dominic.Rath@gmx.de *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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#include "lpc3180_nand_controller.h"
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#include "replacements.h"
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#include "log.h"
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#include <stdlib.h>
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#include <string.h>
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#include "nand.h"
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#include "target.h"
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int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
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int lpc3180_register_commands(struct command_context_s *cmd_ctx);
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int lpc3180_init(struct nand_device_s *device);
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int lpc3180_reset(struct nand_device_s *device);
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int lpc3180_command(struct nand_device_s *device, u8 command);
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int lpc3180_address(struct nand_device_s *device, u8 address);
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int lpc3180_write_data(struct nand_device_s *device, u16 data);
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int lpc3180_read_data(struct nand_device_s *device, void *data);
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int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
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int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
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int lpc3180_controller_ready(struct nand_device_s *device, int timeout);
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int lpc3180_nand_ready(struct nand_device_s *device, int timeout);
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int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
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nand_flash_controller_t lpc3180_nand_controller =
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{
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.name = "lpc3180",
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.nand_device_command = lpc3180_nand_device_command,
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.register_commands = lpc3180_register_commands,
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.init = lpc3180_init,
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.reset = lpc3180_reset,
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.command = lpc3180_command,
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.address = lpc3180_address,
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.write_data = lpc3180_write_data,
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.read_data = lpc3180_read_data,
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.write_page = lpc3180_write_page,
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.read_page = lpc3180_read_page,
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.controller_ready = lpc3180_controller_ready,
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.nand_ready = lpc3180_nand_ready,
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};
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/* nand device lpc3180 <target#> <oscillator_frequency>
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*/
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int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device)
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{
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lpc3180_nand_controller_t *lpc3180_info;
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if (argc < 3)
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{
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WARNING("incomplete 'lpc3180' nand flash configuration");
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return ERROR_FLASH_BANK_INVALID;
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}
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lpc3180_info = malloc(sizeof(lpc3180_nand_controller_t));
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device->controller_priv = lpc3180_info;
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lpc3180_info->target = get_target_by_num(strtoul(args[1], NULL, 0));
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if (!lpc3180_info->target)
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{
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ERROR("no target '%s' configured", args[1]);
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return ERROR_NAND_DEVICE_INVALID;
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}
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lpc3180_info->osc_freq = strtoul(args[2], NULL, 0);
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if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
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{
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WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
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}
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lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
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lpc3180_info->sw_write_protection = 0;
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lpc3180_info->sw_wp_lower_bound = 0x0;
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lpc3180_info->sw_wp_upper_bound = 0x0;
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return ERROR_OK;
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}
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int lpc3180_register_commands(struct command_context_s *cmd_ctx)
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{
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command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers");
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register_command(cmd_ctx, lpc3180_cmd, "select", handle_lpc3180_select_command, COMMAND_EXEC, "select <'mlc'|'slc'> controller (default is mlc)");
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return ERROR_OK;
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}
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int lpc3180_pll(int fclkin, u32 pll_ctrl)
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{
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int bypass = (pll_ctrl & 0x8000) >> 15;
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int direct = (pll_ctrl & 0x4000) >> 14;
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int feedback = (pll_ctrl & 0x2000) >> 13;
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int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
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int n = ((pll_ctrl & 0x0600) >> 9) + 1;
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int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
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int lock = (pll_ctrl & 0x1);
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if (!lock)
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WARNING("PLL is not locked");
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if (!bypass && direct) /* direct mode */
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return (m * fclkin) / n;
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if (bypass && !direct) /* bypass mode */
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return fclkin / (2 * p);
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if (bypass & direct) /* direct bypass mode */
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return fclkin;
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if (feedback) /* integer mode */
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return m * (fclkin / n);
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else /* non-integer mode */
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return (m / (2 * p)) * (fclkin / n);
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}
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float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
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{
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target_t *target = lpc3180_info->target;
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u32 sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
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int sysclk;
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int hclk;
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int hclk_pll;
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float cycle;
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/* calculate timings */
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/* determine current SYSCLK (13'MHz or main oscillator) */
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target_read_u32(target, 0x40004050, &sysclk_ctrl);
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if (sysclk_ctrl & 1)
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sysclk = lpc3180_info->osc_freq;
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else
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sysclk = 13000;
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/* determine selected HCLK source */
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target_read_u32(target, 0x40004044, &pwr_ctrl);
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if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
|
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{
|
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hclk = sysclk;
|
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}
|
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else
|
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{
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target_read_u32(target, 0x40004058, &hclkpll_ctrl);
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hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
|
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|
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target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
|
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|
||||
if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
|
||||
{
|
||||
hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
|
||||
}
|
||||
else /* HCLK uses HCLK_PLL */
|
||||
{
|
||||
hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
|
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}
|
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}
|
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|
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DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
|
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|
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cycle = (1.0 / hclk) * 1000000.0;
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return cycle;
|
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}
|
||||
|
||||
int lpc3180_init(struct nand_device_s *device)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
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target_t *target = lpc3180_info->target;
|
||||
int bus_width = (device->bus_width) ? (device->bus_width) : 8;
|
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int address_cycles = (device->address_cycles) ? (device->address_cycles) : 3;
|
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int page_size = (device->page_size) ? (device->page_size) : 512;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
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return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
/* sanitize arguments */
|
||||
if ((bus_width != 8) && (bus_width != 16))
|
||||
{
|
||||
ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
/* The LPC3180 only brings out 8 bit NAND data bus, but the controller
|
||||
* would support 16 bit, too, so we just warn about this for now
|
||||
*/
|
||||
if (bus_width == 16)
|
||||
{
|
||||
WARNING("LPC3180 only supports 8 bit bus width");
|
||||
}
|
||||
|
||||
/* inform calling code about selected bus width */
|
||||
device->bus_width = bus_width;
|
||||
|
||||
if ((address_cycles != 3) && (address_cycles != 4))
|
||||
{
|
||||
ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
if ((page_size != 512) && (page_size != 2048))
|
||||
{
|
||||
ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
|
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return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
/* select MLC controller if none is currently selected */
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
|
||||
lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
|
||||
}
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
u32 mlc_icr_value = 0x0;
|
||||
float cycle;
|
||||
int twp, twh, trp, treh, trhz, trbwb, tcea;
|
||||
|
||||
/* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
|
||||
target_write_u32(target, 0x400040c8, 0x22);
|
||||
|
||||
/* MLC_CEH = 0x0 (Force nCE assert) */
|
||||
target_write_u32(target, 0x200b804c, 0x0);
|
||||
|
||||
/* MLC_LOCK = 0xa25e (unlock protected registers) */
|
||||
target_write_u32(target, 0x200b8044, 0xa25e);
|
||||
|
||||
/* MLC_ICR = configuration */
|
||||
if (lpc3180_info->sw_write_protection)
|
||||
mlc_icr_value |= 0x8;
|
||||
if (page_size == 2048)
|
||||
mlc_icr_value |= 0x4;
|
||||
if (address_cycles == 4)
|
||||
mlc_icr_value |= 0x2;
|
||||
if (bus_width == 16)
|
||||
mlc_icr_value |= 0x1;
|
||||
target_write_u32(target, 0x200b8030, mlc_icr_value);
|
||||
|
||||
/* calculate NAND controller timings */
|
||||
cycle = lpc3180_cycle_time(lpc3180_info);
|
||||
|
||||
twp = ((40 / cycle) + 1);
|
||||
twh = ((20 / cycle) + 1);
|
||||
trp = ((30 / cycle) + 1);
|
||||
treh = ((15 / cycle) + 1);
|
||||
trhz = ((30 / cycle) + 1);
|
||||
trbwb = ((100 / cycle) + 1);
|
||||
tcea = ((45 / cycle) + 1);
|
||||
|
||||
/* MLC_LOCK = 0xa25e (unlock protected registers) */
|
||||
target_write_u32(target, 0x200b8044, 0xa25e);
|
||||
|
||||
/* MLC_TIME_REG */
|
||||
target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
|
||||
((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
|
||||
((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
|
||||
|
||||
lpc3180_reset(device);
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
float cycle;
|
||||
int r_setup, r_hold, r_width, r_rdy;
|
||||
int w_setup, w_hold, w_width, w_rdy;
|
||||
|
||||
/* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
|
||||
target_write_u32(target, 0x400040c8, 0x05);
|
||||
|
||||
/* SLC_CFG = 0x (Force nCE assert, ECC enabled, WIDTH = bus_width) */
|
||||
target_write_u32(target, 0x20020014, 0x28 | (bus_width == 16) ? 1 : 0);
|
||||
|
||||
/* calculate NAND controller timings */
|
||||
cycle = lpc3180_cycle_time(lpc3180_info);
|
||||
|
||||
r_setup = w_setup = 0;
|
||||
r_hold = w_hold = 10 / cycle;
|
||||
r_width = 30 / cycle;
|
||||
w_width = 40 / cycle;
|
||||
r_rdy = w_rdy = 100 / cycle;
|
||||
|
||||
/* SLC_TAC: SLC timing arcs register */
|
||||
target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
|
||||
((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) |
|
||||
((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
|
||||
|
||||
lpc3180_reset(device);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int lpc3180_reset(struct nand_device_s *device)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
ERROR("BUG: no LPC3180 NAND flash controller selected");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
/* MLC_CMD = 0xff (reset controller and NAND device) */
|
||||
target_write_u32(target, 0x200b8000, 0xff);
|
||||
|
||||
if (!lpc3180_controller_ready(device, 100))
|
||||
{
|
||||
ERROR("LPC3180 NAND controller timed out after reset");
|
||||
return ERROR_NAND_OPERATION_TIMEOUT;
|
||||
}
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
|
||||
target_write_u32(target, 0x20020010, 0x6);
|
||||
|
||||
if (!lpc3180_controller_ready(device, 100))
|
||||
{
|
||||
ERROR("LPC3180 NAND controller timed out after reset");
|
||||
return ERROR_NAND_OPERATION_TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int lpc3180_command(struct nand_device_s *device, u8 command)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
ERROR("BUG: no LPC3180 NAND flash controller selected");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
/* MLC_CMD = command */
|
||||
target_write_u32(target, 0x200b8000, command);
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
/* SLC_CMD = command */
|
||||
target_write_u32(target, 0x20020008, command);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int lpc3180_address(struct nand_device_s *device, u8 address)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
ERROR("BUG: no LPC3180 NAND flash controller selected");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
/* MLC_ADDR = address */
|
||||
target_write_u32(target, 0x200b8004, address);
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
/* SLC_ADDR = address */
|
||||
target_write_u32(target, 0x20020004, address);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int lpc3180_write_data(struct nand_device_s *device, u16 data)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
ERROR("BUG: no LPC3180 NAND flash controller selected");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
/* MLC_DATA = data */
|
||||
target_write_u32(target, 0x200b0000, data);
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
/* SLC_DATA = data */
|
||||
target_write_u32(target, 0x20020000, data);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int lpc3180_read_data(struct nand_device_s *device, void *data)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
ERROR("BUG: no LPC3180 NAND flash controller selected");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
/* data = MLC_DATA, use sized access */
|
||||
if (device->bus_width == 8)
|
||||
{
|
||||
u8 *data8 = data;
|
||||
target_read_u8(target, 0x200b0000, data8);
|
||||
}
|
||||
else if (device->bus_width == 16)
|
||||
{
|
||||
u16 *data16 = data;
|
||||
target_read_u16(target, 0x200b0000, data16);
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR("BUG: bus_width neither 8 nor 16 bit");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
u32 data32;
|
||||
|
||||
/* data = SLC_DATA, must use 32-bit access */
|
||||
target_read_u32(target, 0x20020000, &data32);
|
||||
|
||||
if (device->bus_width == 8)
|
||||
{
|
||||
u8 *data8 = data;
|
||||
*data8 = data32 & 0xff;
|
||||
}
|
||||
else if (device->bus_width == 16)
|
||||
{
|
||||
u16 *data16 = data;
|
||||
*data16 = data32 & 0xffff;
|
||||
}
|
||||
else
|
||||
{
|
||||
ERROR("BUG: bus_width neither 8 nor 16 bit");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int lpc3180_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
int retval;
|
||||
u8 status;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
ERROR("BUG: no LPC3180 NAND flash controller selected");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
u8 *page_buffer;
|
||||
u8 *oob_buffer;
|
||||
int quarter, num_quarters;
|
||||
|
||||
if (!data && oob)
|
||||
{
|
||||
ERROR("LPC3180 MLC controller can't write OOB data only");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
if (oob && (oob_size > 6))
|
||||
{
|
||||
ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
if (data_size > device->page_size)
|
||||
{
|
||||
ERROR("data size exceeds page size");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
/* MLC_CMD = sequential input */
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
|
||||
|
||||
page_buffer = malloc(512);
|
||||
oob_buffer = malloc(6);
|
||||
|
||||
if (device->page_size == 512)
|
||||
{
|
||||
/* MLC_ADDR = 0x0 (one column cycle) */
|
||||
target_write_u32(target, 0x200b8004, 0x0);
|
||||
|
||||
/* MLC_ADDR = row */
|
||||
target_write_u32(target, 0x200b8004, page & 0xff);
|
||||
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
|
||||
|
||||
if (device->address_cycles == 4)
|
||||
target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MLC_ADDR = 0x0 (two column cycles) */
|
||||
target_write_u32(target, 0x200b8004, 0x0);
|
||||
target_write_u32(target, 0x200b8004, 0x0);
|
||||
|
||||
/* MLC_ADDR = row */
|
||||
target_write_u32(target, 0x200b8004, page & 0xff);
|
||||
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
|
||||
}
|
||||
|
||||
/* when using the MLC controller, we have to treat a large page device
|
||||
* as being made out of four quarters, each the size of a small page device
|
||||
*/
|
||||
num_quarters = (device->page_size == 2048) ? 4 : 1;
|
||||
|
||||
for (quarter = 0; quarter < num_quarters; quarter++)
|
||||
{
|
||||
int thisrun_data_size = (data_size > 512) ? 512 : data_size;
|
||||
int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
|
||||
|
||||
memset(page_buffer, 0xff, 512);
|
||||
if (data)
|
||||
{
|
||||
memcpy(page_buffer, data, thisrun_data_size);
|
||||
data_size -= thisrun_data_size;
|
||||
data += thisrun_data_size;
|
||||
}
|
||||
|
||||
memset(oob_buffer, 0xff, (device->page_size == 512) ? 6 : 24);
|
||||
if (oob)
|
||||
{
|
||||
memcpy(page_buffer, oob, thisrun_oob_size);
|
||||
oob_size -= thisrun_oob_size;
|
||||
oob += thisrun_oob_size;
|
||||
}
|
||||
|
||||
/* write MLC_ECC_ENC_REG to start encode cycle */
|
||||
target_write_u32(target, 0x200b8008, 0x0);
|
||||
|
||||
target->type->write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
|
||||
target->type->write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
|
||||
|
||||
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
|
||||
target_write_u32(target, 0x200b8010, 0x0);
|
||||
|
||||
if (!lpc3180_controller_ready(device, 1000))
|
||||
{
|
||||
ERROR("timeout while waiting for completion of auto encode cycle");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
}
|
||||
|
||||
/* MLC_CMD = auto program command */
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
|
||||
|
||||
if ((retval = nand_read_status(device, &status)) != ERROR_OK)
|
||||
{
|
||||
ERROR("couldn't read status");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (status & NAND_STATUS_FAIL)
|
||||
{
|
||||
ERROR("write operation didn't pass, status: 0x%2.2x", status);
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
free(page_buffer);
|
||||
free(oob_buffer);
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int lpc3180_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
|
||||
{
|
||||
ERROR("BUG: no LPC3180 NAND flash controller selected");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
u8 *page_buffer;
|
||||
u8 *oob_buffer;
|
||||
u32 page_bytes_done = 0;
|
||||
u32 oob_bytes_done = 0;
|
||||
u32 mlc_isr;
|
||||
|
||||
#if 0
|
||||
if (oob && (oob_size > 6))
|
||||
{
|
||||
ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (data_size > device->page_size)
|
||||
{
|
||||
ERROR("data size exceeds page size");
|
||||
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
|
||||
}
|
||||
|
||||
if (device->page_size == 2048)
|
||||
{
|
||||
page_buffer = malloc(2048);
|
||||
oob_buffer = malloc(64);
|
||||
}
|
||||
else
|
||||
{
|
||||
page_buffer = malloc(512);
|
||||
oob_buffer = malloc(16);
|
||||
}
|
||||
|
||||
if (!data && oob)
|
||||
{
|
||||
/* MLC_CMD = Read OOB
|
||||
* we can use the READOOB command on both small and large page devices,
|
||||
* as the controller translates the 0x50 command to a 0x0 with appropriate
|
||||
* positioning of the serial buffer read pointer
|
||||
*/
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* MLC_CMD = Read0 */
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
|
||||
}
|
||||
|
||||
if (device->page_size == 512)
|
||||
{
|
||||
/* small page device */
|
||||
/* MLC_ADDR = 0x0 (one column cycle) */
|
||||
target_write_u32(target, 0x200b8004, 0x0);
|
||||
|
||||
/* MLC_ADDR = row */
|
||||
target_write_u32(target, 0x200b8004, page & 0xff);
|
||||
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
|
||||
|
||||
if (device->address_cycles == 4)
|
||||
target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* large page device */
|
||||
/* MLC_ADDR = 0x0 (two column cycles) */
|
||||
target_write_u32(target, 0x200b8004, 0x0);
|
||||
target_write_u32(target, 0x200b8004, 0x0);
|
||||
|
||||
/* MLC_ADDR = row */
|
||||
target_write_u32(target, 0x200b8004, page & 0xff);
|
||||
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
|
||||
|
||||
/* MLC_CMD = Read Start */
|
||||
target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
|
||||
}
|
||||
|
||||
while (page_bytes_done < device->page_size)
|
||||
{
|
||||
/* MLC_ECC_AUTO_DEC_REG = dummy */
|
||||
target_write_u32(target, 0x200b8014, 0xaa55aa55);
|
||||
|
||||
if (!lpc3180_controller_ready(device, 1000))
|
||||
{
|
||||
ERROR("timeout while waiting for completion of auto decode cycle");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
target_read_u32(target, 0x200b8048, &mlc_isr);
|
||||
|
||||
if (mlc_isr & 0x8)
|
||||
{
|
||||
if (mlc_isr & 0x40)
|
||||
{
|
||||
ERROR("uncorrectable error detected: 0x%2.2x", mlc_isr);
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
WARNING("%i symbol error detected and corrected", ((mlc_isr & 0x30) >> 4) + 1);
|
||||
}
|
||||
|
||||
if (data)
|
||||
{
|
||||
target->type->read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
|
||||
}
|
||||
|
||||
if (oob)
|
||||
{
|
||||
target->type->read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
|
||||
}
|
||||
|
||||
page_bytes_done += 512;
|
||||
oob_bytes_done += 16;
|
||||
}
|
||||
|
||||
if (data)
|
||||
memcpy(data, page_buffer, data_size);
|
||||
|
||||
if (oob)
|
||||
memcpy(oob, oob_buffer, oob_size);
|
||||
|
||||
free(page_buffer);
|
||||
free(oob_buffer);
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int lpc3180_controller_ready(struct nand_device_s *device, int timeout)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
u8 status = 0x0;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
do
|
||||
{
|
||||
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
/* Read MLC_ISR, wait for controller to become ready */
|
||||
target_read_u8(target, 0x200b8048, &status);
|
||||
|
||||
if (status & 2)
|
||||
return 1;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
/* we pretend that the SLC controller is always ready */
|
||||
return 1;
|
||||
}
|
||||
|
||||
usleep(1000);
|
||||
} while (timeout-- > 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int lpc3180_nand_ready(struct nand_device_s *device, int timeout)
|
||||
{
|
||||
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
|
||||
target_t *target = lpc3180_info->target;
|
||||
|
||||
if (target->state != TARGET_HALTED)
|
||||
{
|
||||
ERROR("target must be halted to use LPC3180 NAND flash controller");
|
||||
return ERROR_NAND_OPERATION_FAILED;
|
||||
}
|
||||
|
||||
do
|
||||
{
|
||||
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
|
||||
{
|
||||
u8 status = 0x0;
|
||||
|
||||
/* Read MLC_ISR, wait for NAND flash device to become ready */
|
||||
target_read_u8(target, 0x200b8048, &status);
|
||||
|
||||
if (status & 1)
|
||||
return 1;
|
||||
}
|
||||
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
|
||||
{
|
||||
u32 status = 0x0;
|
||||
|
||||
/* Read SLC_STAT and check READY bit */
|
||||
target_read_u32(target, 0x20020018, &status);
|
||||
|
||||
if (status & 1)
|
||||
return 1;
|
||||
}
|
||||
|
||||
usleep(1000);
|
||||
} while (timeout-- > 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||
{
|
||||
nand_device_t *device = NULL;
|
||||
lpc3180_nand_controller_t *lpc3180_info = NULL;
|
||||
char *selected[] =
|
||||
{
|
||||
"no", "mlc", "slc"
|
||||
};
|
||||
|
||||
if ((argc < 1) || (argc > 2))
|
||||
{
|
||||
command_print(cmd_ctx, "usage: lpc3180 select <num> <'mlc'|'slc'>");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
device = get_nand_device_by_num(strtoul(args[0], NULL, 0));
|
||||
if (!device)
|
||||
{
|
||||
command_print(cmd_ctx, "nand device '#%s' is out of bounds", args[0]);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
lpc3180_info = device->controller_priv;
|
||||
|
||||
if (argc == 2)
|
||||
{
|
||||
if (strcmp(args[1], "mlc") == 0)
|
||||
{
|
||||
lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
|
||||
}
|
||||
else if (strcmp(args[1], "slc") == 0)
|
||||
{
|
||||
lpc3180_info->selected_controller = LPC3180_SLC_CONTROLLER;
|
||||
}
|
||||
else
|
||||
{
|
||||
command_print(cmd_ctx, "usage: lpc3180 select <'mlc'|'slc'>");
|
||||
}
|
||||
}
|
||||
|
||||
command_print(cmd_ctx, "%s controller selected", selected[lpc3180_info->selected_controller]);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2007 by Dominic Rath *
|
||||
* Dominic.Rath@gmx.de *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
#ifndef LPC3180_NAND_CONTROLLER_H
|
||||
#define LPC3180_NAND_CONTROLLER_H
|
||||
|
||||
#include "target.h"
|
||||
|
||||
enum lpc3180_selected_controller
|
||||
{
|
||||
LPC3180_NO_CONTROLLER,
|
||||
LPC3180_MLC_CONTROLLER,
|
||||
LPC3180_SLC_CONTROLLER,
|
||||
};
|
||||
|
||||
typedef struct lpc3180_nand_controller_s
|
||||
{
|
||||
struct target_s *target;
|
||||
int osc_freq;
|
||||
enum lpc3180_selected_controller selected_controller;
|
||||
int sw_write_protection;
|
||||
u32 sw_wp_lower_bound;
|
||||
u32 sw_wp_upper_bound;
|
||||
} lpc3180_nand_controller_t;
|
||||
|
||||
#endif /*LPC3180_NAND_CONTROLLER_H */
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,207 @@
|
|||
/***************************************************************************
|
||||
* Copyright (C) 2007 by Dominic Rath *
|
||||
* Dominic.Rath@gmx.de *
|
||||
* *
|
||||
* partially based on *
|
||||
* linux/include/linux/mtd/nand.h *
|
||||
* *
|
||||
* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> *
|
||||
* Steven J. Hill <sjhill@realitydiluted.com> *
|
||||
* Thomas Gleixner <tglx@linutronix.de> *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
#ifndef NAND_H
|
||||
#define NAND_H
|
||||
|
||||
#include "flash.h"
|
||||
|
||||
struct nand_device_s;
|
||||
|
||||
typedef struct nand_flash_controller_s
|
||||
{
|
||||
char *name;
|
||||
int (*nand_device_command)(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device);
|
||||
int (*register_commands)(struct command_context_s *cmd_ctx);
|
||||
int (*init)(struct nand_device_s *device);
|
||||
int (*reset)(struct nand_device_s *device);
|
||||
int (*command)(struct nand_device_s *device, u8 command);
|
||||
int (*address)(struct nand_device_s *device, u8 address);
|
||||
int (*write_data)(struct nand_device_s *device, u16 data);
|
||||
int (*read_data)(struct nand_device_s *device, void *data);
|
||||
int (*write_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
||||
int (*read_page)(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
||||
int (*controller_ready)(struct nand_device_s *device, int timeout);
|
||||
int (*nand_ready)(struct nand_device_s *device, int timeout);
|
||||
} nand_flash_controller_t;
|
||||
|
||||
typedef struct nand_block_s
|
||||
{
|
||||
u32 offset;
|
||||
u32 size;
|
||||
int is_erased;
|
||||
int is_bad;
|
||||
} nand_block_t;
|
||||
|
||||
typedef struct nand_device_s
|
||||
{
|
||||
nand_flash_controller_t *controller;
|
||||
void *controller_priv;
|
||||
struct nand_manufacturer_s *manufacturer;
|
||||
struct nand_info_s *device;
|
||||
int bus_width;
|
||||
int address_cycles;
|
||||
int page_size;
|
||||
int erase_size;
|
||||
int use_raw;
|
||||
int num_blocks;
|
||||
nand_block_t *blocks;
|
||||
struct nand_device_s *next;
|
||||
} nand_device_t;
|
||||
|
||||
/* NAND Flash Manufacturer ID Codes
|
||||
*/
|
||||
enum
|
||||
{
|
||||
NAND_MFR_TOSHIBA = 0x98,
|
||||
NAND_MFR_SAMSUNG = 0xec,
|
||||
NAND_MFR_FUJITSU = 0x04,
|
||||
NAND_MFR_NATIONAL = 0x8f,
|
||||
NAND_MFR_RENESAS = 0x07,
|
||||
NAND_MFR_STMICRO = 0x20,
|
||||
NAND_MFR_HYNIX = 0xad,
|
||||
};
|
||||
|
||||
typedef struct nand_manufacturer_s
|
||||
{
|
||||
int id;
|
||||
char *name;
|
||||
} nand_manufacturer_t;
|
||||
|
||||
typedef struct nand_info_s
|
||||
{
|
||||
char *name;
|
||||
int id;
|
||||
int page_size;
|
||||
int chip_size;
|
||||
int erase_size;
|
||||
int options;
|
||||
} nand_info_t;
|
||||
|
||||
/* Option constants for bizarre disfunctionality and real features
|
||||
*/
|
||||
enum {
|
||||
/* Chip can not auto increment pages */
|
||||
NAND_NO_AUTOINCR = 0x00000001,
|
||||
|
||||
/* Buswitdh is 16 bit */
|
||||
NAND_BUSWIDTH_16 = 0x00000002,
|
||||
|
||||
/* Device supports partial programming without padding */
|
||||
NAND_NO_PADDING = 0x00000004,
|
||||
|
||||
/* Chip has cache program function */
|
||||
NAND_CACHEPRG = 0x00000008,
|
||||
|
||||
/* Chip has copy back function */
|
||||
NAND_COPYBACK = 0x00000010,
|
||||
|
||||
/* AND Chip which has 4 banks and a confusing page / block
|
||||
* assignment. See Renesas datasheet for further information */
|
||||
NAND_IS_AND = 0x00000020,
|
||||
|
||||
/* Chip has a array of 4 pages which can be read without
|
||||
* additional ready /busy waits */
|
||||
NAND_4PAGE_ARRAY = 0x00000040,
|
||||
|
||||
/* Chip requires that BBT is periodically rewritten to prevent
|
||||
* bits from adjacent blocks from 'leaking' in altering data.
|
||||
* This happens with the Renesas AG-AND chips, possibly others. */
|
||||
BBT_AUTO_REFRESH = 0x00000080,
|
||||
|
||||
/* Chip does not require ready check on read. True
|
||||
* for all large page devices, as they do not support
|
||||
* autoincrement.*/
|
||||
NAND_NO_READRDY = 0x00000100,
|
||||
|
||||
/* Options valid for Samsung large page devices */
|
||||
NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
|
||||
|
||||
/* Options for new chips with large page size. The pagesize and the
|
||||
* erasesize is determined from the extended id bytes
|
||||
*/
|
||||
LP_OPTIONS = (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR),
|
||||
LP_OPTIONS16 = (LP_OPTIONS | NAND_BUSWIDTH_16),
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
/* Standard NAND flash commands */
|
||||
NAND_CMD_READ0 = 0x0,
|
||||
NAND_CMD_READ1 = 0x1,
|
||||
NAND_CMD_RNDOUT = 0x5,
|
||||
NAND_CMD_PAGEPROG = 0x10,
|
||||
NAND_CMD_READOOB = 0x50,
|
||||
NAND_CMD_ERASE1 = 0x60,
|
||||
NAND_CMD_STATUS = 0x70,
|
||||
NAND_CMD_STATUS_MULTI = 0x71,
|
||||
NAND_CMD_SEQIN = 0x80,
|
||||
NAND_CMD_RNDIN = 0x85,
|
||||
NAND_CMD_READID = 0x90,
|
||||
NAND_CMD_ERASE2 = 0xd0,
|
||||
NAND_CMD_RESET = 0xff,
|
||||
|
||||
/* Extended commands for large page devices */
|
||||
NAND_CMD_READSTART = 0x30,
|
||||
NAND_CMD_RNDOUTSTART = 0xE0,
|
||||
NAND_CMD_CACHEDPROG = 0x15,
|
||||
};
|
||||
|
||||
/* Status bits */
|
||||
enum
|
||||
{
|
||||
NAND_STATUS_FAIL = 0x01,
|
||||
NAND_STATUS_FAIL_N1 = 0x02,
|
||||
NAND_STATUS_TRUE_READY = 0x20,
|
||||
NAND_STATUS_READY = 0x40,
|
||||
NAND_STATUS_WP = 0x80,
|
||||
};
|
||||
|
||||
/* OOB (spare) data formats */
|
||||
enum oob_formats
|
||||
{
|
||||
NAND_OOB_NONE = 0x0, /* no OOB data at all */
|
||||
NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
|
||||
NAND_OOB_ONLY = 0x2, /* only OOB data */
|
||||
NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
|
||||
NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
|
||||
NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
|
||||
NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
|
||||
};
|
||||
|
||||
/* Function prototypes */
|
||||
extern nand_device_t *get_nand_device_by_num(int num);
|
||||
extern int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
||||
extern int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
|
||||
|
||||
#define ERROR_NAND_DEVICE_INVALID (-1100)
|
||||
#define ERROR_NAND_OPERATION_FAILED (-1101)
|
||||
#define ERROR_NAND_OPERATION_TIMEOUT (-1102)
|
||||
#define ERROR_NAND_OPERATION_NOT_SUPPORTED (-1103)
|
||||
#define ERROR_NAND_DEVICE_NOT_PROBED (-1104)
|
||||
#define ERROR_NAND_ERROR_CORRECTION_FAILED (-1105)
|
||||
|
||||
#endif /* NAND_H */
|
||||
|
|
@ -1,6 +1,7 @@
|
|||
INCLUDES = $(all_includes)
|
||||
METASOURCES = AUTO
|
||||
noinst_LIBRARIES = libhelper.a
|
||||
libhelper_a_SOURCES = binarybuffer.c configuration.c log.c interpreter.c command.c time_support.c replacements.c
|
||||
libhelper_a_SOURCES = binarybuffer.c configuration.c log.c interpreter.c command.c time_support.c \
|
||||
replacements.c fileio.c
|
||||
noinst_HEADERS = binarybuffer.h configuration.h types.h log.h command.h \
|
||||
interpreter.h time_support.h replacements.h
|
||||
interpreter.h time_support.h replacements.h fileio.h
|
||||
|
|
|
|||
|
|
@ -22,6 +22,7 @@
|
|||
#endif
|
||||
|
||||
#include "time_support.h"
|
||||
#include "log.h"
|
||||
|
||||
#include <sys/time.h>
|
||||
#include <time.h>
|
||||
|
|
@ -82,3 +83,26 @@ int timeval_add_time(struct timeval *result, int sec, int usec)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int duration_start_measure(duration_t *duration)
|
||||
{
|
||||
gettimeofday(&duration->start, NULL);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int duration_stop_measure(duration_t *duration, char **text)
|
||||
{
|
||||
struct timeval end;
|
||||
|
||||
gettimeofday(&end, NULL);
|
||||
|
||||
timeval_subtract(&duration->duration, &end, &duration->start);
|
||||
|
||||
if (text)
|
||||
{
|
||||
*text = malloc(16);
|
||||
snprintf(*text, 16, "%is %ius", duration->duration.tv_sec, duration->duration.tv_usec);
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -27,4 +27,13 @@ extern int timeval_subtract(struct timeval *result, struct timeval *x, struct ti
|
|||
extern int timeval_add(struct timeval *result, struct timeval *x, struct timeval *y);
|
||||
extern int timeval_add_time(struct timeval *result, int sec, int usec);
|
||||
|
||||
typedef struct duration_s
|
||||
{
|
||||
struct timeval start;
|
||||
struct timeval duration;
|
||||
} duration_t;
|
||||
|
||||
extern int duration_start_measure(duration_t *duration);
|
||||
extern int duration_stop_measure(duration_t *duration, char **text);
|
||||
|
||||
#endif /* TIME_SUPPORT_H */
|
||||
|
|
|
|||
|
|
@ -34,6 +34,10 @@ typedef unsigned short u16;
|
|||
typedef unsigned int u32;
|
||||
#endif
|
||||
|
||||
#ifndef u64
|
||||
typedef unsigned long long u64;
|
||||
#endif
|
||||
|
||||
#ifdef WORDS_BIGENDIAN /* big endian host */
|
||||
|
||||
#define le_to_h_u32(x) (u32)(x[0] | x[1] << 8 | x[2] << 16 | x[3] << 24)
|
||||
|
|
@ -61,8 +65,8 @@ typedef unsigned int u32;
|
|||
#else /* little endian host */
|
||||
#define le_to_h_u32(x) (*(u32*)(x))
|
||||
#define le_to_h_u16(x) (*(u16*)(x))
|
||||
#define be_to_h_u32(x) (u32)(x[3] | x[2] << 8 | x[1] << 16 | x[0] << 24)
|
||||
#define be_to_h_u16(x) (u16)(x[1] | x[0] << 8)
|
||||
#define be_to_h_u32(x) (u32)((x)[3] | (x)[2] << 8 | (x)[1] << 16 | (x)[0] << 24)
|
||||
#define be_to_h_u16(x) (u16)((x)[1] | (x)[0] << 8)
|
||||
|
||||
#define h_u32_to_le(buf, val) do { *(u32*)(buf) = (val); } while (0)
|
||||
#define h_u16_to_le(buf, val) do { *(u16*)(buf) = (val); } while (0)
|
||||
|
|
|
|||
|
|
@ -288,6 +288,9 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
|
|||
enum tap_state saved_end_state = end_state;
|
||||
u8 scan_out, scan_in;
|
||||
|
||||
/* only if we're not already in the correct Shift state */
|
||||
if (!((!ir_scan && (cur_state == TAP_SD)) || (ir_scan && (cur_state == TAP_SI))))
|
||||
{
|
||||
if (ir_scan)
|
||||
gw16012_end_state(TAP_SI);
|
||||
else
|
||||
|
|
@ -295,6 +298,7 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
|
|||
|
||||
gw16012_state_move();
|
||||
gw16012_end_state(saved_end_state);
|
||||
}
|
||||
|
||||
while (type == SCAN_OUT && ((bits_left - 1) > 7))
|
||||
{
|
||||
|
|
@ -309,6 +313,9 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
|
|||
while (bits_left-- > 0)
|
||||
{
|
||||
u8 tms = 0;
|
||||
|
||||
scan_out = buf_get_u32(buffer, bit_count, 1);
|
||||
|
||||
if (bits_left == 0) /* last bit */
|
||||
{
|
||||
if ((ir_scan && (end_state == TAP_SI))
|
||||
|
|
@ -322,13 +329,14 @@ void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
|
|||
}
|
||||
}
|
||||
|
||||
scan_out = buf_get_u32(buffer, bit_count, 1);
|
||||
gw16012_data(scan_out | tms);
|
||||
|
||||
if (type != SCAN_OUT)
|
||||
{
|
||||
gw16012_input(&scan_in);
|
||||
buf_set_u32(buffer, bit_count, 1, ((scan_in & 0x08) >> 3));
|
||||
}
|
||||
|
||||
bit_count++;
|
||||
}
|
||||
|
||||
|
|
@ -530,6 +538,13 @@ int gw16012_init(void)
|
|||
return ERROR_JTAG_INIT_FAILED;
|
||||
}
|
||||
DEBUG("...privileges granted");
|
||||
|
||||
/* make sure parallel port is in right mode (clear tristate and interrupt */
|
||||
#ifdef __FreeBSD__
|
||||
outb(gw16012_port + 2, 0x0);
|
||||
#else
|
||||
outb(0x0, gw16012_port + 2);
|
||||
#endif
|
||||
#endif /* PARPORT_USE_PPDEV */
|
||||
|
||||
gw16012_input(&status_port);
|
||||
|
|
|
|||
|
|
@ -1143,6 +1143,7 @@ void jtag_sleep(u32 us)
|
|||
*/
|
||||
int jtag_examine_chain()
|
||||
{
|
||||
jtag_device_t *device = jtag_devices;
|
||||
scan_field_t field;
|
||||
u8 idcode_buffer[JTAG_MAX_CHAIN_SIZE * 4];
|
||||
int i;
|
||||
|
|
@ -1204,6 +1205,11 @@ int jtag_examine_chain()
|
|||
break;
|
||||
}
|
||||
|
||||
if (device)
|
||||
{
|
||||
device->idcode = idcode;
|
||||
device = device->next;
|
||||
}
|
||||
device_count++;
|
||||
|
||||
manufacturer = (idcode & 0xffe) >> 1;
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
#include "command.h"
|
||||
|
||||
#if 1
|
||||
#if 0
|
||||
#define _DEBUG_JTAG_IO_
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -94,6 +94,7 @@ cable_t cables[] =
|
|||
{
|
||||
/* name tdo trst tms tck tdi srst o_inv i_inv init */
|
||||
{ "wiggler", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80 },
|
||||
{ "wiggler_ntrst_inverted", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x11, 0x80, 0x80 },
|
||||
{ "old_amt_wiggler", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x11, 0x80, 0x80 },
|
||||
{ "chameleon", 0x80, 0x00, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00 },
|
||||
{ "dlc5", 0x10, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x10 },
|
||||
|
|
@ -390,7 +391,7 @@ int parport_init(void)
|
|||
#ifdef __FreeBSD__
|
||||
outb(parport_port + 2, 0x0);
|
||||
#else
|
||||
outb(0x0, dataport);
|
||||
outb(0x0, parport_port + 2);
|
||||
#endif
|
||||
|
||||
#endif /* PARPORT_USE_PPDEV */
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
|
||||
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-01-31 12:00 CET)"
|
||||
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-03-15 14:30 CET)"
|
||||
|
||||
#ifdef HAVE_CONFIG_H
|
||||
#include "config.h"
|
||||
|
|
@ -75,6 +75,7 @@ int main(int argc, char *argv[])
|
|||
xsvf_register_commands(cmd_ctx);
|
||||
target_register_commands(cmd_ctx);
|
||||
flash_register_commands(cmd_ctx);
|
||||
nand_register_commands(cmd_ctx);
|
||||
pld_register_commands(cmd_ctx);
|
||||
|
||||
if (log_init(cmd_ctx) != ERROR_OK)
|
||||
|
|
@ -109,6 +110,10 @@ int main(int argc, char *argv[])
|
|||
return EXIT_FAILURE;
|
||||
DEBUG("flash init complete");
|
||||
|
||||
if (nand_init(cmd_ctx) != ERROR_OK)
|
||||
return EXIT_FAILURE;
|
||||
DEBUG("NAND init complete");
|
||||
|
||||
if (pld_init(cmd_ctx) != ERROR_OK)
|
||||
return EXIT_FAILURE;
|
||||
DEBUG("pld init complete");
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@ int handle_arm7_9_force_hw_bkpts_command(struct command_context_s *cmd_ctx, char
|
|||
int handle_arm7_9_dbgrq_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_arm7_9_fast_memory_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
|
||||
int arm7_9_reinit_embeddedice(target_t *target)
|
||||
{
|
||||
|
|
@ -2050,6 +2051,8 @@ int arm7_9_register_commands(struct command_context_s *cmd_ctx)
|
|||
|
||||
arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9", NULL, COMMAND_ANY, "arm7/9 specific commands");
|
||||
|
||||
register_command(cmd_ctx, arm7_9_cmd, "etm", handle_arm7_9_etm_command, COMMAND_CONFIG, NULL);
|
||||
|
||||
register_command(cmd_ctx, arm7_9_cmd, "write_xpsr", handle_arm7_9_write_xpsr_command, COMMAND_EXEC, "write program status register <value> <not cpsr|spsr>");
|
||||
register_command(cmd_ctx, arm7_9_cmd, "write_xpsr_im8", handle_arm7_9_write_xpsr_im8_command, COMMAND_EXEC, "write program status register <8bit immediate> <rotate> <not cpsr|spsr>");
|
||||
|
||||
|
|
@ -2376,6 +2379,37 @@ int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char
|
|||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||
{
|
||||
target_t *target;
|
||||
armv4_5_common_t *armv4_5;
|
||||
arm7_9_common_t *arm7_9;
|
||||
|
||||
if (argc != 1)
|
||||
{
|
||||
ERROR("incomplete 'arm7_9 etm <target>' command");
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
target = get_target_by_num(strtoul(args[0], NULL, 0));
|
||||
|
||||
if (!target)
|
||||
{
|
||||
ERROR("target number '%s' not defined", args[0]);
|
||||
exit(-1);
|
||||
}
|
||||
|
||||
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
|
||||
{
|
||||
command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
arm7_9->has_etm = 1;
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
int arm7_9_init_arch_info(target_t *target, arm7_9_common_t *arm7_9)
|
||||
{
|
||||
armv4_5_common_t *armv4_5 = &arm7_9->armv4_5_common;
|
||||
|
|
|
|||
|
|
@ -736,8 +736,6 @@ void arm7tdmi_build_reg_cache(target_t *target)
|
|||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
||||
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
||||
arm7tdmi_common_t *arch_info = arm7_9->arch_info;
|
||||
|
||||
|
||||
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
|
||||
armv4_5->core_cache = (*cache_p);
|
||||
|
|
@ -771,7 +769,6 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int c
|
|||
{
|
||||
armv4_5_common_t *armv4_5;
|
||||
arm7_9_common_t *arm7_9;
|
||||
int has_etm = 0;
|
||||
|
||||
arm7_9 = &arm7tdmi->arm7_9_common;
|
||||
armv4_5 = &arm7_9->armv4_5_common;
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
#include "target.h"
|
||||
#include "armv4_5.h"
|
||||
#include "embeddedice.h"
|
||||
#include "etm.h"
|
||||
#include "log.h"
|
||||
#include "jtag.h"
|
||||
#include "arm_jtag.h"
|
||||
|
|
@ -824,9 +825,6 @@ void arm9tdmi_build_reg_cache(target_t *target)
|
|||
armv4_5_common_t *armv4_5 = target->arch_info;
|
||||
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
|
||||
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
|
||||
arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
|
||||
|
||||
embeddedice_reg_t *vec_catch_arch_info;
|
||||
|
||||
(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
|
||||
armv4_5->core_cache = (*cache_p);
|
||||
|
|
@ -835,17 +833,11 @@ void arm9tdmi_build_reg_cache(target_t *target)
|
|||
(*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
|
||||
arm7_9->eice_cache = (*cache_p)->next;
|
||||
|
||||
#if 0
|
||||
(*cache_p)->next->reg_list[EICE_VEC_CATCH].name = "vector catch";
|
||||
(*cache_p)->next->reg_list[EICE_VEC_CATCH].dirty = 0;
|
||||
(*cache_p)->next->reg_list[EICE_VEC_CATCH].valid = 0;
|
||||
(*cache_p)->next->reg_list[EICE_VEC_CATCH].bitfield_desc = NULL;
|
||||
(*cache_p)->next->reg_list[EICE_VEC_CATCH].num_bitfields = 0;
|
||||
(*cache_p)->next->reg_list[EICE_VEC_CATCH].size = 8;
|
||||
(*cache_p)->next->reg_list[EICE_VEC_CATCH].value = calloc(1, 4);
|
||||
vec_catch_arch_info = (*cache_p)->next->reg_list[EICE_VEC_CATCH].arch_info;
|
||||
vec_catch_arch_info->addr = 0x2;
|
||||
#endif
|
||||
if (arm7_9->has_etm)
|
||||
{
|
||||
(*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
|
||||
arm7_9->etm_cache = (*cache_p)->next->next;
|
||||
}
|
||||
}
|
||||
|
||||
int arm9tdmi_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
|
||||
|
|
|
|||
|
|
@ -171,6 +171,12 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
|
|||
reg_list[EICE_DBG_STAT].size = 10;
|
||||
arm7_9->has_monitor_mode = 1;
|
||||
break;
|
||||
case 7:
|
||||
WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
|
||||
reg_list[EICE_DBG_CTRL].size = 6;
|
||||
reg_list[EICE_DBG_STAT].size = 5;
|
||||
arm7_9->has_monitor_mode = 1;
|
||||
break;
|
||||
default:
|
||||
ERROR("unknown EmbeddedICE version (comms ctrl: 0x%4.4x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -42,6 +42,8 @@
|
|||
|
||||
#include <time_support.h>
|
||||
|
||||
#include <fileio.h>
|
||||
|
||||
int cli_target_callback_event_handler(struct target_s *target, enum target_event event, void *priv);
|
||||
|
||||
int handle_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
|
|
@ -62,8 +64,8 @@ int handle_resume_command(struct command_context_s *cmd_ctx, char *cmd, char **a
|
|||
int handle_step_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_md_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_mw_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_load_binary_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_dump_binary_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_load_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_dump_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_bp_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_rbp_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
int handle_wp_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
|
||||
|
|
@ -732,6 +734,8 @@ void target_read_u32(struct target_s *target, u32 address, u32 *value)
|
|||
target->type->read_memory(target, address, 4, 1, value_buf);
|
||||
|
||||
*value = target_buffer_get_u32(target, value_buf);
|
||||
|
||||
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, *value);
|
||||
}
|
||||
|
||||
void target_read_u16(struct target_s *target, u32 address, u16 *value)
|
||||
|
|
@ -741,17 +745,23 @@ void target_read_u16(struct target_s *target, u32 address, u16 *value)
|
|||
target->type->read_memory(target, address, 2, 1, value_buf);
|
||||
|
||||
*value = target_buffer_get_u16(target, value_buf);
|
||||
|
||||
DEBUG("address: 0x%8.8x, value: 0x%4.4x", address, *value);
|
||||
}
|
||||
|
||||
void target_read_u8(struct target_s *target, u32 address, u8 *value)
|
||||
{
|
||||
target->type->read_memory(target, address, 1, 1, value);
|
||||
|
||||
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, *value);
|
||||
}
|
||||
|
||||
void target_write_u32(struct target_s *target, u32 address, u32 value)
|
||||
{
|
||||
u8 value_buf[4];
|
||||
|
||||
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
|
||||
|
||||
target_buffer_set_u32(target, value_buf, value);
|
||||
target->type->write_memory(target, address, 4, 1, value_buf);
|
||||
}
|
||||
|
|
@ -760,12 +770,16 @@ void target_write_u16(struct target_s *target, u32 address, u16 value)
|
|||
{
|
||||
u8 value_buf[2];
|
||||
|
||||
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
|
||||
|
||||
target_buffer_set_u16(target, value_buf, value);
|
||||
target->type->write_memory(target, address, 2, 1, value_buf);
|
||||
}
|
||||
|
||||
void target_write_u8(struct target_s *target, u32 address, u8 value)
|
||||
{
|
||||
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value);
|
||||
|
||||
target->type->read_memory(target, address, 1, 1, &value);
|
||||
}
|
||||
|
||||
|
|
@ -773,7 +787,7 @@ int target_register_user_commands(struct command_context_s *cmd_ctx)
|
|||
{
|
||||
register_command(cmd_ctx, NULL, "reg", handle_reg_command, COMMAND_EXEC, NULL);
|
||||
register_command(cmd_ctx, NULL, "poll", handle_poll_command, COMMAND_EXEC, "poll target state");
|
||||
register_command(cmd_ctx, NULL, "wait_halt", handle_wait_halt_command, COMMAND_EXEC, "wait for target halt");
|
||||
register_command(cmd_ctx, NULL, "wait_halt", handle_wait_halt_command, COMMAND_EXEC, "wait for target halt [time (s)]");
|
||||
register_command(cmd_ctx, NULL, "halt", handle_halt_command, COMMAND_EXEC, "halt target");
|
||||
register_command(cmd_ctx, NULL, "resume", handle_resume_command, COMMAND_EXEC, "resume target [addr]");
|
||||
register_command(cmd_ctx, NULL, "step", handle_step_command, COMMAND_EXEC, "step one instruction");
|
||||
|
|
@ -793,8 +807,10 @@ int target_register_user_commands(struct command_context_s *cmd_ctx)
|
|||
register_command(cmd_ctx, NULL, "wp", handle_wp_command, COMMAND_EXEC, "set watchpoint <address> <length> <r/w/a> [value] [mask]");
|
||||
register_command(cmd_ctx, NULL, "rwp", handle_rwp_command, COMMAND_EXEC, "remove watchpoint <adress>");
|
||||
|
||||
register_command(cmd_ctx, NULL, "load_binary", handle_load_binary_command, COMMAND_EXEC, "load binary <file> <address>");
|
||||
register_command(cmd_ctx, NULL, "dump_binary", handle_dump_binary_command, COMMAND_EXEC, "dump binary <file> <address> <size>");
|
||||
register_command(cmd_ctx, NULL, "load_image", handle_load_image_command, COMMAND_EXEC, "load_image <file> <address> ['bin'|'ihex']");
|
||||
register_command(cmd_ctx, NULL, "dump_image", handle_dump_image_command, COMMAND_EXEC, "dump_image <file> <address> <size>");
|
||||
register_command(cmd_ctx, NULL, "load_binary", handle_load_image_command, COMMAND_EXEC, "[DEPRECATED] load_binary <file> <address>");
|
||||
register_command(cmd_ctx, NULL, "dump_binary", handle_dump_image_command, COMMAND_EXEC, "[DEPRECATED] dump_binary <file> <address> <size>");
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
|
@ -1223,7 +1239,17 @@ int handle_wait_halt_command(struct command_context_s *cmd_ctx, char *cmd, char
|
|||
struct timeval timeout, now;
|
||||
|
||||
gettimeofday(&timeout, NULL);
|
||||
if (!argc)
|
||||
timeval_add_time(&timeout, 5, 0);
|
||||
else {
|
||||
char *end;
|
||||
|
||||
timeval_add_time(&timeout, strtoul(args[0], &end, 0), 0);
|
||||
if (*end) {
|
||||
command_print(cmd_ctx, "usage: wait_halt [seconds]");
|
||||
return ERROR_OK;
|
||||
}
|
||||
}
|
||||
|
||||
command_print(cmd_ctx, "waiting for target halted...");
|
||||
|
||||
|
|
@ -1560,118 +1586,126 @@ int handle_mw_command(struct command_context_s *cmd_ctx, char *cmd, char **args,
|
|||
|
||||
}
|
||||
|
||||
int handle_load_binary_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||
int handle_load_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||
{
|
||||
FILE *binary;
|
||||
u32 address;
|
||||
struct stat binary_stat;
|
||||
u32 binary_size;
|
||||
|
||||
u8 *buffer;
|
||||
u32 buf_cnt;
|
||||
u32 binary_size;
|
||||
|
||||
struct timeval start, end, duration;
|
||||
fileio_t file;
|
||||
enum fileio_pri_type pri_type = FILEIO_IMAGE;
|
||||
fileio_image_t image_info;
|
||||
enum fileio_sec_type sec_type;
|
||||
|
||||
duration_t duration;
|
||||
char *duration_text;
|
||||
|
||||
target_t *target = get_current_target(cmd_ctx);
|
||||
|
||||
if (argc != 2)
|
||||
if (argc < 2)
|
||||
{
|
||||
command_print(cmd_ctx, "usage: load_binary <filename> <address>");
|
||||
command_print(cmd_ctx, "usage: load_image <filename> <address> [type]");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
address = strtoul(args[1], NULL, 0);
|
||||
memset(&file, 0, sizeof(fileio_t));
|
||||
fileio_identify_image_type(&sec_type, (argc == 3) ? args[2] : NULL);
|
||||
|
||||
if (stat(args[0], &binary_stat) == -1)
|
||||
{
|
||||
ERROR("couldn't stat() %s: %s", args[0], strerror(errno));
|
||||
command_print(cmd_ctx, "error accessing file %s", args[0]);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
if (!(binary = fopen(args[0], "rb")))
|
||||
{
|
||||
ERROR("couldn't open %s: %s", args[0], strerror(errno));
|
||||
command_print(cmd_ctx, "error accessing file %s", args[0]);
|
||||
return ERROR_OK;
|
||||
}
|
||||
image_info.base_address = strtoul(args[1], NULL, 0);
|
||||
image_info.has_start_address = 0;
|
||||
|
||||
buffer = malloc(128 * 1024);
|
||||
|
||||
gettimeofday(&start, NULL);
|
||||
duration_start_measure(&duration);
|
||||
|
||||
binary_size = binary_stat.st_size;
|
||||
while (binary_size > 0)
|
||||
if (fileio_open(&file, args[0], FILEIO_READ,
|
||||
pri_type, &image_info, sec_type) != ERROR_OK)
|
||||
{
|
||||
command_print(cmd_ctx, "load_image error: %s", file.error_str);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
binary_size = file.size;
|
||||
address = image_info.base_address;
|
||||
while ((binary_size > 0) &&
|
||||
(fileio_read(&file, 128 * 1024, buffer, &buf_cnt) == ERROR_OK))
|
||||
{
|
||||
buf_cnt = fread(buffer, 1, 128*1024, binary);
|
||||
target_write_buffer(target, address, buf_cnt, buffer);
|
||||
address += buf_cnt;
|
||||
binary_size -= buf_cnt;
|
||||
}
|
||||
|
||||
gettimeofday(&end, NULL);
|
||||
|
||||
free(buffer);
|
||||
|
||||
timeval_subtract(&duration, &end, &start);
|
||||
command_print(cmd_ctx, "downloaded %lli byte in %is %ius", (long long) binary_stat.st_size, duration.tv_sec, duration.tv_usec);
|
||||
duration_stop_measure(&duration, &duration_text);
|
||||
command_print(cmd_ctx, "downloaded %lli byte in %s", file.size, duration_text);
|
||||
free(duration_text);
|
||||
|
||||
fclose(binary);
|
||||
fileio_close(&file);
|
||||
|
||||
return ERROR_OK;
|
||||
|
||||
}
|
||||
|
||||
int handle_dump_binary_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||
int handle_dump_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
|
||||
{
|
||||
FILE *binary;
|
||||
fileio_t file;
|
||||
fileio_image_t image_info;
|
||||
|
||||
u32 address;
|
||||
u32 size;
|
||||
u8 buffer[560];
|
||||
|
||||
struct timeval start, end, duration;
|
||||
duration_t duration;
|
||||
char *duration_text;
|
||||
|
||||
target_t *target = get_current_target(cmd_ctx);
|
||||
|
||||
if (argc != 3)
|
||||
{
|
||||
command_print(cmd_ctx, "usage: dump_binary <filename> <address> <size>");
|
||||
command_print(cmd_ctx, "usage: dump_image <filename> <address> <size>");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
address = strtoul(args[1], NULL, 0);
|
||||
size = strtoul(args[2], NULL, 0);
|
||||
|
||||
if (!(binary = fopen(args[0], "wb")))
|
||||
{
|
||||
ERROR("couldn't open %s for writing: %s", args[0], strerror(errno));
|
||||
command_print(cmd_ctx, "error accessing file %s", args[0]);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
if ((address & 3) || (size & 3))
|
||||
{
|
||||
command_print(cmd_ctx, "only 32-bit aligned address and size are supported");
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
gettimeofday(&start, NULL);
|
||||
image_info.base_address = address;
|
||||
image_info.has_start_address = 0;
|
||||
|
||||
if (fileio_open(&file, args[0], FILEIO_WRITE,
|
||||
FILEIO_IMAGE, &image_info, FILEIO_PLAIN) != ERROR_OK)
|
||||
{
|
||||
command_print(cmd_ctx, "dump_image error: %s", file.error_str);
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
duration_start_measure(&duration);
|
||||
|
||||
while (size > 0)
|
||||
{
|
||||
u32 size_written;
|
||||
u32 this_run_size = (size > 560) ? 560 : size;
|
||||
|
||||
target->type->read_memory(target, address, 4, this_run_size / 4, buffer);
|
||||
fwrite(buffer, 1, this_run_size, binary);
|
||||
fileio_write(&file, this_run_size, buffer, &size_written);
|
||||
|
||||
size -= this_run_size;
|
||||
address += this_run_size;
|
||||
}
|
||||
|
||||
fclose(binary);
|
||||
fileio_close(&file);
|
||||
|
||||
gettimeofday(&end, NULL);
|
||||
|
||||
timeval_subtract(&duration, &end, &start);
|
||||
command_print(cmd_ctx, "dumped %i byte in %is %ius", strtoul(args[2], NULL, 0), duration.tv_sec, duration.tv_usec);
|
||||
duration_stop_measure(&duration, &duration_text);
|
||||
command_print(cmd_ctx, "dumped %lli byte in %s", file.size, duration_text);
|
||||
free(duration_text);
|
||||
|
||||
return ERROR_OK;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue