arm_adi_v5: Rewrite dap_rom_display
Simplify by printing one component per call, instead of one complete ROM Table per call. Print common information the same way for all components, including ROM tables, because ROM tables (at least the top level) contain useful information in their identification registers, such as the manufacturer of the SoC. Print component designer name using the JEP106 helper when available. Change-Id: Ic51bccd98acfae6886243500153fbdd567be2fae Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3182 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: James Mastros <james@mastros.biz>
This commit is contained in:
Andreas Fritiofson
parent
849f69b2e9
commit
ca86cd6128
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@ -75,6 +75,7 @@
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#include "jtag/interface.h"
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#include "arm.h"
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#include "arm_adi_v5.h"
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#include <helper/jep106.h>
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#include <helper/time_support.h>
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#include <helper/list.h>
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@ -739,10 +740,9 @@ static const char *class_description[16] = {
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"Generic IP component", "PrimeCell or System component"
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};
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static bool is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
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static bool is_dap_cid_ok(uint32_t cid)
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{
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return cid3 == 0xb1 && cid2 == 0x05
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&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
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return (cid & 0xffff0fff) == 0xb105000d;
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}
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/*
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@ -876,6 +876,61 @@ int dap_lookup_cs_component(struct adiv5_ap *ap,
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return ERROR_OK;
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}
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static int dap_read_part_id(struct adiv5_ap *ap, uint32_t component_base, uint32_t *cid, uint64_t *pid)
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{
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assert((component_base & 0xFFF) == 0);
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assert(ap != NULL && cid != NULL && pid != NULL);
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uint32_t cid0, cid1, cid2, cid3;
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uint32_t pid0, pid1, pid2, pid3, pid4;
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int retval;
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/* IDs are in last 4K section */
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retval = mem_ap_read_u32(ap, component_base + 0xFE0, &pid0);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + 0xFE4, &pid1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + 0xFE8, &pid2);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + 0xFEC, &pid3);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + 0xFD0, &pid4);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + 0xFF0, &cid0);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + 0xFF4, &cid1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + 0xFF8, &cid2);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, component_base + 0xFFC, &cid3);
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if (retval != ERROR_OK)
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return retval;
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retval = dap_run(ap->dap);
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if (retval != ERROR_OK)
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return retval;
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*cid = (cid3 & 0xff) << 24
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| (cid2 & 0xff) << 16
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| (cid1 & 0xff) << 8
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| (cid0 & 0xff);
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*pid = (uint64_t)(pid4 & 0xff) << 32
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| (pid3 & 0xff) << 24
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| (pid2 & 0xff) << 16
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| (pid1 & 0xff) << 8
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| (pid0 & 0xff);
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return ERROR_OK;
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}
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/* The designer identity code is encoded as:
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* bits 11:8 : JEP106 Bank (number of continuation codes), only valid when bit 7 is 1.
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* bit 7 : Set when bits 6:0 represent a JEP106 ID and cleared when bits 6:0 represent
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@ -976,10 +1031,9 @@ static const struct {
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static int dap_rom_display(struct command_context *cmd_ctx,
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struct adiv5_ap *ap, uint32_t dbgbase, int depth)
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{
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struct adiv5_dap *dap = ap->dap;
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int retval;
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uint32_t cid0, cid1, cid2, cid3, memtype, romentry;
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uint16_t entry_offset;
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uint64_t pid;
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uint32_t cid;
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char tabs[7] = "";
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if (depth > 16) {
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@ -990,330 +1044,241 @@ static int dap_rom_display(struct command_context *cmd_ctx,
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if (depth)
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snprintf(tabs, sizeof(tabs), "[L%02d] ", depth);
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/* bit 16 of apid indicates a memory access port */
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if (dbgbase & 0x02)
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command_print(cmd_ctx, "\t%sValid ROM table present", tabs);
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else
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command_print(cmd_ctx, "\t%sROM table in legacy format", tabs);
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uint32_t base_addr = dbgbase & 0xFFFFF000;
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command_print(cmd_ctx, "\t\tComponent base address 0x%08" PRIx32, base_addr);
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/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
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retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
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if (retval != ERROR_OK)
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return retval;
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retval = mem_ap_read_u32(ap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
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if (retval != ERROR_OK)
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return retval;
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retval = dap_run(dap);
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if (retval != ERROR_OK)
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return retval;
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retval = dap_read_part_id(ap, base_addr, &cid, &pid);
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if (retval != ERROR_OK) {
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command_print(cmd_ctx, "\t\tCan't read component, the corresponding core might be turned off");
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return ERROR_OK; /* Don't abort recursion */
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}
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if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
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command_print(cmd_ctx, "\t%sCID3 0x%02x"
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", CID2 0x%02x"
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", CID1 0x%02x"
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", CID0 0x%02x",
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tabs,
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(unsigned)cid3, (unsigned)cid2,
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(unsigned)cid1, (unsigned)cid0);
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if (memtype & 0x01)
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command_print(cmd_ctx, "\t%sMEMTYPE system memory present on bus", tabs);
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else
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command_print(cmd_ctx, "\t%sMEMTYPE system memory not present: dedicated debug bus", tabs);
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if (!is_dap_cid_ok(cid)) {
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command_print(cmd_ctx, "\t\tInvalid CID 0x%08" PRIx32, cid);
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return ERROR_OK; /* Don't abort recursion */
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}
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/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
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for (entry_offset = 0; ; entry_offset += 4) {
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retval = mem_ap_read_atomic_u32(ap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
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/* component may take multiple 4K pages */
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uint32_t size = (pid >> 36) & 0xf;
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if (size > 0)
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command_print(cmd_ctx, "\t\tStart address 0x%08" PRIx32, (uint32_t)(base_addr - 0x1000 * size));
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command_print(cmd_ctx, "\t\tPeripheral ID 0x%010" PRIx64, pid);
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uint8_t class = (cid >> 12) & 0xf;
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uint16_t part_num = pid & 0xfff;
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uint16_t designer_id = ((pid >> 32) & 0xf) << 8 | ((pid >> 12) & 0xff);
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if (designer_id & 0x80) {
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/* JEP106 code */
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command_print(cmd_ctx, "\t\tDesigner is 0x%03" PRIx16 ", %s",
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designer_id, jep106_manufacturer(designer_id >> 8, designer_id & 0x7f));
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} else {
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/* Legacy ASCII ID, clear invalid bits */
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designer_id &= 0x7f;
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command_print(cmd_ctx, "\t\tDesigner ASCII code 0x%02" PRIx16 ", %s",
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designer_id, designer_id == 0x41 ? "ARM" : "<unknown>");
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}
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/* default values to be overwritten upon finding a match */
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const char *type = "Unrecognized";
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const char *full = "";
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/* search dap_partnums[] array for a match */
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for (unsigned entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
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if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
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continue;
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if (dap_partnums[entry].part_num != part_num)
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continue;
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type = dap_partnums[entry].type;
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full = dap_partnums[entry].full;
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break;
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}
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command_print(cmd_ctx, "\t\tPart is 0x%" PRIx16", %s %s", part_num, type, full);
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command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s", class, class_description[class]);
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if (class == 1) { /* ROM Table */
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uint32_t memtype;
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retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &memtype);
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if (retval != ERROR_OK)
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return retval;
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command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
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tabs, entry_offset, romentry);
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if (romentry & 0x01) {
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uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
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uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
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uint32_t component_base;
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uint16_t part_num, designer_id;
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const char *type, *full;
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component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000);
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if (memtype & 0x01)
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command_print(cmd_ctx, "\t\tMEMTYPE system memory present on bus");
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else
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command_print(cmd_ctx, "\t\tMEMTYPE system memory not present: dedicated debug bus");
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/* IDs are in last 4K section */
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE0, &c_pid0);
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if (retval != ERROR_OK) {
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command_print(cmd_ctx, "\t%s\tCan't read component with base address 0x%" PRIx32
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", the corresponding core might be turned off", tabs, component_base);
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continue;
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}
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c_pid0 &= 0xff;
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE4, &c_pid1);
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/* Read ROM table entries from base address until we get 0x00000000 or reach the reserved area */
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for (uint16_t entry_offset = 0; entry_offset < 0xF00; entry_offset += 4) {
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uint32_t romentry;
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retval = mem_ap_read_atomic_u32(ap, base_addr | entry_offset, &romentry);
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if (retval != ERROR_OK)
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return retval;
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c_pid1 &= 0xff;
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFE8, &c_pid2);
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if (retval != ERROR_OK)
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return retval;
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c_pid2 &= 0xff;
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFEC, &c_pid3);
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if (retval != ERROR_OK)
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return retval;
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c_pid3 &= 0xff;
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFD0, &c_pid4);
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if (retval != ERROR_OK)
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return retval;
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c_pid4 &= 0xff;
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF0, &c_cid0);
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if (retval != ERROR_OK)
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return retval;
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c_cid0 &= 0xff;
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF4, &c_cid1);
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if (retval != ERROR_OK)
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return retval;
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c_cid1 &= 0xff;
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFF8, &c_cid2);
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if (retval != ERROR_OK)
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return retval;
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c_cid2 &= 0xff;
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retval = mem_ap_read_atomic_u32(ap, component_base + 0xFFC, &c_cid3);
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if (retval != ERROR_OK)
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return retval;
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c_cid3 &= 0xff;
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command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", "
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"start address 0x%" PRIx32, component_base,
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/* component may take multiple 4K pages */
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(uint32_t)(component_base - 0x1000*(c_pid4 >> 4)));
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command_print(cmd_ctx, "\t\tComponent class is 0x%" PRIx8 ", %s",
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(uint8_t)((c_cid1 >> 4) & 0xf),
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/* See ARM IHI 0029B Table 3-3 */
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class_description[(c_cid1 >> 4) & 0xf]);
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/* CoreSight component? */
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if (((c_cid1 >> 4) & 0x0f) == 9) {
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uint32_t devtype;
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unsigned minor;
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const char *major = "Reserved", *subtype = "Reserved";
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retval = mem_ap_read_atomic_u32(ap,
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(component_base & 0xfffff000) | 0xfcc,
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&devtype);
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command_print(cmd_ctx, "\t%sROMTABLE[0x%x] = 0x%" PRIx32 "",
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tabs, entry_offset, romentry);
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if (romentry & 0x01) {
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/* Recurse */
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retval = dap_rom_display(cmd_ctx, ap, base_addr + (romentry & 0xFFFFF000), depth + 1);
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if (retval != ERROR_OK)
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return retval;
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minor = (devtype >> 4) & 0x0f;
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switch (devtype & 0x0f) {
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case 0:
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major = "Miscellaneous";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 4:
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subtype = "Validation component";
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break;
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}
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break;
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case 1:
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major = "Trace Sink";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Port";
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break;
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case 2:
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subtype = "Buffer";
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break;
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case 3:
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subtype = "Router";
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break;
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}
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break;
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case 2:
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major = "Trace Link";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Funnel, router";
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break;
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case 2:
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subtype = "Filter";
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break;
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case 3:
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subtype = "FIFO, buffer";
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break;
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}
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break;
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case 3:
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major = "Trace Source";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Processor";
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break;
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case 2:
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subtype = "DSP";
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break;
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case 3:
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subtype = "Engine/Coprocessor";
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break;
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case 4:
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subtype = "Bus";
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break;
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case 6:
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subtype = "Software";
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break;
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}
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break;
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case 4:
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major = "Debug Control";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Trigger Matrix";
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break;
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case 2:
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subtype = "Debug Auth";
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break;
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case 3:
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subtype = "Power Requestor";
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break;
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}
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break;
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case 5:
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major = "Debug Logic";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Processor";
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break;
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case 2:
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subtype = "DSP";
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break;
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case 3:
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subtype = "Engine/Coprocessor";
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break;
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case 4:
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subtype = "Bus";
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break;
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case 5:
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subtype = "Memory";
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break;
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}
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break;
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case 6:
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major = "Perfomance Monitor";
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switch (minor) {
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case 0:
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subtype = "other";
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break;
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case 1:
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subtype = "Processor";
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break;
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case 2:
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subtype = "DSP";
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break;
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case 3:
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subtype = "Engine/Coprocessor";
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break;
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case 4:
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subtype = "Bus";
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break;
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case 5:
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subtype = "Memory";
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break;
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}
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break;
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}
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command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
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(uint8_t)(devtype & 0xff),
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major, subtype);
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/* REVISIT also show 0xfc8 DevId */
|
||||
}
|
||||
|
||||
if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
|
||||
command_print(cmd_ctx,
|
||||
"\t\tCID3 0%02x"
|
||||
", CID2 0%02x"
|
||||
", CID1 0%02x"
|
||||
", CID0 0%02x",
|
||||
(int)c_cid3,
|
||||
(int)c_cid2,
|
||||
(int)c_cid1,
|
||||
(int)c_cid0);
|
||||
command_print(cmd_ctx,
|
||||
"\t\tPeripheral ID[4..0] = hex "
|
||||
"%02x %02x %02x %02x %02x",
|
||||
(int)c_pid4, (int)c_pid3, (int)c_pid2,
|
||||
(int)c_pid1, (int)c_pid0);
|
||||
|
||||
part_num = (c_pid0 & 0xff);
|
||||
part_num |= (c_pid1 & 0x0f) << 8;
|
||||
designer_id = (c_pid1 & 0xf0) >> 4;
|
||||
designer_id |= (c_pid2 & 0x0f) << 4;
|
||||
designer_id |= (c_pid4 & 0x0f) << 8;
|
||||
if ((designer_id & 0x80) == 0) {
|
||||
/* Legacy ASCII ID, clear invalid bits */
|
||||
designer_id &= 0x7f;
|
||||
}
|
||||
|
||||
/* default values to be overwritten upon finding a match */
|
||||
type = NULL;
|
||||
full = "";
|
||||
|
||||
/* search dap_partnums[] array for a match */
|
||||
unsigned entry;
|
||||
for (entry = 0; entry < ARRAY_SIZE(dap_partnums); entry++) {
|
||||
|
||||
if ((dap_partnums[entry].designer_id != designer_id) && (dap_partnums[entry].designer_id != ANY_ID))
|
||||
continue;
|
||||
|
||||
if (dap_partnums[entry].part_num != part_num)
|
||||
continue;
|
||||
|
||||
type = dap_partnums[entry].type;
|
||||
full = dap_partnums[entry].full;
|
||||
break;
|
||||
}
|
||||
|
||||
if (type) {
|
||||
command_print(cmd_ctx, "\t\tPart is %s %s",
|
||||
type, full);
|
||||
} else {
|
||||
command_print(cmd_ctx, "\t\tUnrecognized (Part 0x%" PRIx16 ", designer 0x%" PRIx16 ")",
|
||||
part_num, designer_id);
|
||||
}
|
||||
|
||||
/* ROM Table? */
|
||||
if (((c_cid1 >> 4) & 0x0f) == 1) {
|
||||
retval = dap_rom_display(cmd_ctx, ap, component_base, depth + 1);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
}
|
||||
} else {
|
||||
if (romentry)
|
||||
} else if (romentry != 0) {
|
||||
command_print(cmd_ctx, "\t\tComponent not present");
|
||||
else
|
||||
} else {
|
||||
command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (class == 9) { /* CoreSight component */
|
||||
const char *major = "Reserved", *subtype = "Reserved";
|
||||
|
||||
uint32_t devtype;
|
||||
retval = mem_ap_read_atomic_u32(ap, base_addr | 0xFCC, &devtype);
|
||||
if (retval != ERROR_OK)
|
||||
return retval;
|
||||
unsigned minor = (devtype >> 4) & 0x0f;
|
||||
switch (devtype & 0x0f) {
|
||||
case 0:
|
||||
major = "Miscellaneous";
|
||||
switch (minor) {
|
||||
case 0:
|
||||
subtype = "other";
|
||||
break;
|
||||
case 4:
|
||||
subtype = "Validation component";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
major = "Trace Sink";
|
||||
switch (minor) {
|
||||
case 0:
|
||||
subtype = "other";
|
||||
break;
|
||||
case 1:
|
||||
subtype = "Port";
|
||||
break;
|
||||
case 2:
|
||||
subtype = "Buffer";
|
||||
break;
|
||||
case 3:
|
||||
subtype = "Router";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 2:
|
||||
major = "Trace Link";
|
||||
switch (minor) {
|
||||
case 0:
|
||||
subtype = "other";
|
||||
break;
|
||||
case 1:
|
||||
subtype = "Funnel, router";
|
||||
break;
|
||||
case 2:
|
||||
subtype = "Filter";
|
||||
break;
|
||||
case 3:
|
||||
subtype = "FIFO, buffer";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 3:
|
||||
major = "Trace Source";
|
||||
switch (minor) {
|
||||
case 0:
|
||||
subtype = "other";
|
||||
break;
|
||||
case 1:
|
||||
subtype = "Processor";
|
||||
break;
|
||||
case 2:
|
||||
subtype = "DSP";
|
||||
break;
|
||||
case 3:
|
||||
subtype = "Engine/Coprocessor";
|
||||
break;
|
||||
case 4:
|
||||
subtype = "Bus";
|
||||
break;
|
||||
case 6:
|
||||
subtype = "Software";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 4:
|
||||
major = "Debug Control";
|
||||
switch (minor) {
|
||||
case 0:
|
||||
subtype = "other";
|
||||
break;
|
||||
case 1:
|
||||
subtype = "Trigger Matrix";
|
||||
break;
|
||||
case 2:
|
||||
subtype = "Debug Auth";
|
||||
break;
|
||||
case 3:
|
||||
subtype = "Power Requestor";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 5:
|
||||
major = "Debug Logic";
|
||||
switch (minor) {
|
||||
case 0:
|
||||
subtype = "other";
|
||||
break;
|
||||
case 1:
|
||||
subtype = "Processor";
|
||||
break;
|
||||
case 2:
|
||||
subtype = "DSP";
|
||||
break;
|
||||
case 3:
|
||||
subtype = "Engine/Coprocessor";
|
||||
break;
|
||||
case 4:
|
||||
subtype = "Bus";
|
||||
break;
|
||||
case 5:
|
||||
subtype = "Memory";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 6:
|
||||
major = "Perfomance Monitor";
|
||||
switch (minor) {
|
||||
case 0:
|
||||
subtype = "other";
|
||||
break;
|
||||
case 1:
|
||||
subtype = "Processor";
|
||||
break;
|
||||
case 2:
|
||||
subtype = "DSP";
|
||||
break;
|
||||
case 3:
|
||||
subtype = "Engine/Coprocessor";
|
||||
break;
|
||||
case 4:
|
||||
subtype = "Bus";
|
||||
break;
|
||||
case 5:
|
||||
subtype = "Memory";
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
command_print(cmd_ctx, "\t\tType is 0x%02" PRIx8 ", %s, %s",
|
||||
(uint8_t)(devtype & 0xff),
|
||||
major, subtype);
|
||||
/* REVISIT also show 0xfc8 DevId */
|
||||
}
|
||||
command_print(cmd_ctx, "\t%s\tEnd of ROM table", tabs);
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
|
|
@ -1322,7 +1287,6 @@ static int dap_info_command(struct command_context *cmd_ctx,
|
|||
{
|
||||
int retval;
|
||||
uint32_t dbgbase, apid;
|
||||
int romtable_present = 0;
|
||||
uint8_t mem_ap;
|
||||
|
||||
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
|
||||
|
|
@ -1361,11 +1325,16 @@ static int dap_info_command(struct command_context *cmd_ctx,
|
|||
if (mem_ap) {
|
||||
command_print(cmd_ctx, "MEM-AP BASE 0x%8.8" PRIx32, dbgbase);
|
||||
|
||||
romtable_present = dbgbase != 0xFFFFFFFF;
|
||||
if (romtable_present)
|
||||
dap_rom_display(cmd_ctx, ap, dbgbase, 0);
|
||||
else
|
||||
if (dbgbase == 0xFFFFFFFF || (dbgbase & 0x3) == 0x2) {
|
||||
command_print(cmd_ctx, "\tNo ROM table present");
|
||||
} else {
|
||||
if (dbgbase & 0x01)
|
||||
command_print(cmd_ctx, "\tValid ROM table present");
|
||||
else
|
||||
command_print(cmd_ctx, "\tROM table in legacy format");
|
||||
|
||||
dap_rom_display(cmd_ctx, ap, dbgbase & 0xFFFFF000, 0);
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR_OK;
|
||||
|
|
|
|||
Loading…
Reference in New Issue