flash/stm32l4x: STM32L5 support programming when TZEN=1 and RDP=0xAA
STM32L5 flash memory is aliased to 0x0C000000, this address mapping is used for secure applications. (0x08000000 for non-secure) this change allows the programming of secure and non-secure flash when trustzone is enabled and RDP level is 0 Change-Id: I89d1f1b5d493cf01a142ca4dbfef5a3731cab96e Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/5936 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Tarek BOCHKATI
Oleksij Rempel
parent
80d323c6e8
commit
c9d40366ad
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@ -127,6 +127,8 @@
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#define F_USE_ALL_WRPXX BIT(1)
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/* this flag indicates if the device embeds a TrustZone security feature */
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#define F_HAS_TZ BIT(2)
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/* this flag indicates if the device has the same flash registers as STM32L5 */
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#define F_HAS_L5_FLASH_REGS BIT(3)
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/* end of STM32L4 flags ******************************************************/
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@ -166,10 +168,23 @@ static const uint32_t stm32l4_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
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static const uint32_t stm32l5_ns_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
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[STM32_FLASH_ACR_INDEX] = 0x000,
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[STM32_FLASH_KEYR_INDEX] = 0x008,
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[STM32_FLASH_KEYR_INDEX] = 0x008, /* NSKEYR */
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[STM32_FLASH_OPTKEYR_INDEX] = 0x010,
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[STM32_FLASH_SR_INDEX] = 0x020,
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[STM32_FLASH_CR_INDEX] = 0x028,
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[STM32_FLASH_SR_INDEX] = 0x020, /* NSSR */
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[STM32_FLASH_CR_INDEX] = 0x028, /* NSCR */
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[STM32_FLASH_OPTR_INDEX] = 0x040,
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[STM32_FLASH_WRP1AR_INDEX] = 0x058,
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[STM32_FLASH_WRP1BR_INDEX] = 0x05C,
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[STM32_FLASH_WRP2AR_INDEX] = 0x068,
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[STM32_FLASH_WRP2BR_INDEX] = 0x06C,
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};
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static const uint32_t stm32l5_s_flash_regs[STM32_FLASH_REG_INDEX_NUM] = {
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[STM32_FLASH_ACR_INDEX] = 0x000,
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[STM32_FLASH_KEYR_INDEX] = 0x00C, /* SECKEYR */
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[STM32_FLASH_OPTKEYR_INDEX] = 0x010,
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[STM32_FLASH_SR_INDEX] = 0x024, /* SECSR */
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[STM32_FLASH_CR_INDEX] = 0x02C, /* SECCR */
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[STM32_FLASH_OPTR_INDEX] = 0x040,
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[STM32_FLASH_WRP1AR_INDEX] = 0x058,
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[STM32_FLASH_WRP1BR_INDEX] = 0x05C,
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@ -205,6 +220,7 @@ struct stm32l4_flash_bank {
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uint32_t user_bank_size;
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uint32_t wrpxxr_mask;
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const struct stm32l4_part_info *part_info;
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uint32_t flash_regs_base;
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const uint32_t *flash_regs;
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bool otp_enabled;
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enum stm32l4_rdp rdp;
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@ -444,7 +460,7 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
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.num_revs = ARRAY_SIZE(stm32_472_revs),
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.device_str = "STM32L55/L56xx",
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.max_flash_size_kb = 512,
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.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ,
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.flags = F_HAS_DUAL_BANK | F_USE_ALL_WRPXX | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
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.flash_regs_base = 0x40022000,
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.default_flash_regs = stm32l5_ns_flash_regs,
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.fsize_addr = 0x0BFA05E0,
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@ -653,7 +669,7 @@ static void stm32l4_sync_rdp_tzen(struct flash_bank *bank)
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static inline uint32_t stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
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{
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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return stm32l4_info->part_info->flash_regs_base + reg_offset;
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return stm32l4_info->flash_regs_base + reg_offset;
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}
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static inline uint32_t stm32l4_get_flash_reg_by_index(struct flash_bank *bank,
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@ -725,6 +741,49 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
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return retval;
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}
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/** set all FLASH_SECBB registers to the same value */
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static int stm32l4_set_secbb(struct flash_bank *bank, uint32_t value)
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{
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/* This function should be used only with device with TrustZone, do just a security check */
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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assert(stm32l4_info->part_info->flags & F_HAS_TZ);
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/* based on RM0438 Rev6 for STM32L5x devices:
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* to modify a page block-based security attribution, it is recommended to
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* 1- check that no flash operation is ongoing on the related page
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* 2- add ISB instruction after modifying the page security attribute in SECBBxRy
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* this step is not need in case of JTAG direct access
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*/
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int retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
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if (retval != ERROR_OK)
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return retval;
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/* write SECBBxRy registers */
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LOG_DEBUG("setting secure block-based areas registers (SECBBxRy) to 0x%08x", value);
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const uint8_t secbb_regs[] = {
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FLASH_SECBB1(1), FLASH_SECBB1(2), FLASH_SECBB1(3), FLASH_SECBB1(4), /* bank 1 SECBB register offsets */
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FLASH_SECBB2(1), FLASH_SECBB2(2), FLASH_SECBB2(3), FLASH_SECBB2(4) /* bank 2 SECBB register offsets */
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};
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unsigned int num_secbb_regs = ARRAY_SIZE(secbb_regs);
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/* in single bank mode, it's useless to modify FLASH_SECBB2Rx registers
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* then consider only the first half of secbb_regs
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*/
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if (!stm32l4_info->dual_bank_mode)
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num_secbb_regs /= 2;
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for (unsigned int i = 0; i < num_secbb_regs; i++) {
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retval = stm32l4_write_flash_reg(bank, secbb_regs[i], value);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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static int stm32l4_unlock_reg(struct flash_bank *bank)
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{
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uint32_t ctrl;
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@ -831,6 +890,7 @@ err_lock:
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static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
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uint32_t value, uint32_t mask)
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{
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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uint32_t optiondata;
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int retval, retval2;
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@ -838,6 +898,12 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
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if (retval != ERROR_OK)
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return retval;
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/* for STM32L5 and similar devices, use always non-secure
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* registers for option bytes programming */
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const uint32_t *saved_flash_regs = stm32l4_info->flash_regs;
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if (stm32l4_info->part_info->flags & F_HAS_L5_FLASH_REGS)
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stm32l4_info->flash_regs = stm32l5_ns_flash_regs;
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retval = stm32l4_unlock_reg(bank);
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if (retval != ERROR_OK)
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goto err_lock;
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@ -860,6 +926,7 @@ static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK | FLASH_OPTLOCK);
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stm32l4_info->flash_regs = saved_flash_regs;
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if (retval != ERROR_OK)
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return retval;
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@ -1007,6 +1074,16 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
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return ERROR_TARGET_NOT_HALTED;
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}
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* set all FLASH pages as secure */
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retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
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if (retval != ERROR_OK) {
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/* restore all FLASH pages as non-secure */
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stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
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return retval;
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}
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}
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retval = stm32l4_unlock_reg(bank);
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if (retval != ERROR_OK)
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goto err_lock;
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@ -1044,6 +1121,13 @@ static int stm32l4_erase(struct flash_bank *bank, unsigned int first,
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* restore all FLASH pages as non-secure */
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int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
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if (retval3 != ERROR_OK)
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return retval3;
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}
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if (retval != ERROR_OK)
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return retval;
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@ -1281,6 +1365,7 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
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static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
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int retval = ERROR_OK, retval2;
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if (stm32l4_is_otp(bank) && !stm32l4_otp_is_enabled(bank)) {
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@ -1335,6 +1420,16 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
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if (retval != ERROR_OK)
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return retval;
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* set all FLASH pages as secure */
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retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
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if (retval != ERROR_OK) {
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/* restore all FLASH pages as non-secure */
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stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
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return retval;
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}
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}
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retval = stm32l4_unlock_reg(bank);
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if (retval != ERROR_OK)
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goto err_lock;
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@ -1344,6 +1439,13 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* restore all FLASH pages as non-secure */
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int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
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if (retval3 != ERROR_OK)
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return retval3;
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}
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if (retval != ERROR_OK) {
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LOG_ERROR("block write failed");
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return retval;
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@ -1426,6 +1528,7 @@ static int stm32l4_probe(struct flash_bank *bank)
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LOG_INFO("device idcode = 0x%08" PRIx32 " (%s - Rev %s : 0x%04x)",
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stm32l4_info->idcode, part_info->device_str, rev_str, rev_id);
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stm32l4_info->flash_regs_base = stm32l4_info->part_info->flash_regs_base;
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stm32l4_info->flash_regs = stm32l4_info->part_info->default_flash_regs;
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/* read flash option register */
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@ -1461,7 +1564,7 @@ static int stm32l4_probe(struct flash_bank *bank)
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stm32l4_info->probed = true;
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return ERROR_OK;
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} else if (bank->base != STM32_FLASH_BANK_BASE) {
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} else if (bank->base != STM32_FLASH_BANK_BASE && bank->base != STM32_FLASH_S_BANK_BASE) {
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LOG_ERROR("invalid bank base address");
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return ERROR_FAIL;
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}
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@ -1589,6 +1692,15 @@ static int stm32l4_probe(struct flash_bank *bank)
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num_pages = flash_size_kb / page_size_kb;
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stm32l4_info->bank1_sectors = num_pages / 2;
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}
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/**
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* by default use the non-secure registers,
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* switch secure registers if TZ is enabled and RDP is LEVEL_0
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*/
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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stm32l4_info->flash_regs_base |= 0x10000000;
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stm32l4_info->flash_regs = stm32l5_s_flash_regs;
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}
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break;
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case 0x495: /* STM32WB5x */
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case 0x496: /* STM32WB3x */
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@ -1714,6 +1826,16 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
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return ERROR_TARGET_NOT_HALTED;
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}
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* set all FLASH pages as secure */
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retval = stm32l4_set_secbb(bank, FLASH_SECBB_SECURE);
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if (retval != ERROR_OK) {
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/* restore all FLASH pages as non-secure */
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stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE); /* ignore the return value */
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return retval;
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}
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}
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retval = stm32l4_unlock_reg(bank);
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if (retval != ERROR_OK)
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goto err_lock;
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@ -1736,6 +1858,13 @@ static int stm32l4_mass_erase(struct flash_bank *bank)
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err_lock:
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retval2 = stm32l4_write_flash_reg_by_index(bank, STM32_FLASH_CR_INDEX, FLASH_LOCK);
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if (stm32l4_info->tzen && (stm32l4_info->rdp == RDP_LEVEL_0)) {
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/* restore all FLASH pages as non-secure */
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int retval3 = stm32l4_set_secbb(bank, FLASH_SECBB_NON_SECURE);
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if (retval3 != ERROR_OK)
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return retval3;
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}
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if (retval != ERROR_OK)
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return retval;
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@ -60,11 +60,19 @@
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#define FLASH_RDP_MASK 0xFF
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#define FLASH_TZEN (1 << 31)
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/* FLASH secure block based bank 1/2 register offsets */
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#define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
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#define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))
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#define FLASH_SECBB_SECURE 0xFFFFFFFF
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#define FLASH_SECBB_NON_SECURE 0
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/* other registers */
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#define DBGMCU_IDCODE_G0 0x40015800
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#define DBGMCU_IDCODE_L4_G4 0xE0042000
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#define DBGMCU_IDCODE_L5 0xE0044000
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#define STM32_FLASH_BANK_BASE 0x08000000
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#define STM32_FLASH_S_BANK_BASE 0x0C000000
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#endif
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@ -52,9 +52,10 @@ target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
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# use non-secure RAM by default
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# declare non-secure flash
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flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
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# create sec/ns flash and otp memories (sizes will be probed)
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flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
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flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
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# Common knowledges tells JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
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@ -77,30 +78,47 @@ if {![using_hla]} {
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cortex_m reset_config sysresetreq
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}
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proc is_secure {} {
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# read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
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set DSCSR [mrw 0xE000EE08]
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return [expr {($DSCSR & (1 << 16)) != 0}]
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}
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proc clock_config_110_mhz {} {
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set offset [expr {[is_secure] ? 0x10000000 : 0}]
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# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
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# RCC_APB1ENR1 = PWREN
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mww 0x40021058 0x10000000
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mww [expr {0x40021058 + $offset}] 0x10000000
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# delay for register clock enable (read back reg)
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mrw 0x40021058
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mrw [expr {0x40021058 + $offset}]
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# PWR_CR1 : VOS Range 0
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mww 0x40007000 0
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mww [expr {0x40007000 + $offset}] 0
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# while (PWR_SR2 & VOSF)
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while {([mrw 0x40007014] & 0x0400)} {}
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while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
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# FLASH_ACR : 5 WS for 110 MHz HCLK
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mww 0x40022000 0x00000005
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# RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
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# fVCO = 4 x 55 /1 = 220
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# SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
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mww 0x4002100C 0x01003711
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mww [expr {0x4002100C + $offset}] 0x01003711
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# RCC_CR |= PLLON
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mmw 0x40021000 0x01000000 0
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mmw [expr {0x40021000 + $offset}] 0x01000000 0
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# while !(RCC_CR & PLLRDY)
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||||
while {!([mrw 0x40021000] & 0x02000000)} {}
|
||||
while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
|
||||
# RCC_CFGR |= SW_PLL
|
||||
mmw 0x40021008 0x00000003 0
|
||||
mmw [expr {0x40021008 + $offset}] 0x00000003 0
|
||||
# while ((RCC_CFGR & SWS) != PLL)
|
||||
while {([mrw 0x40021008] & 0x0C) != 0x0C} {}
|
||||
while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
|
||||
}
|
||||
|
||||
proc ahb_ap_non_secure_access {} {
|
||||
# SPROT=1=Non Secure access, Priv=1
|
||||
[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
|
||||
}
|
||||
|
||||
proc ahb_ap_secure_access {} {
|
||||
# SPROT=0=Secure access, Priv=1
|
||||
[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
|
|
@ -123,6 +141,53 @@ $_TARGETNAME configure -event examine-end {
|
|||
mmw 0xE0044008 0x00001800 0
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event halted {
|
||||
set secure [is_secure]
|
||||
|
||||
if {$secure} {
|
||||
set secure_str "Secure"
|
||||
ahb_ap_secure_access
|
||||
} else {
|
||||
set secure_str "Non-Secure"
|
||||
ahb_ap_non_secure_access
|
||||
}
|
||||
|
||||
# print the secure state only when it changes
|
||||
set _TARGETNAME [target current]
|
||||
global $_TARGETNAME.secure
|
||||
|
||||
if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
|
||||
echo "CPU in $secure_str state"
|
||||
# update saved security state
|
||||
set $_TARGETNAME.secure $secure
|
||||
}
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event gdb-flash-erase-start {
|
||||
set use_secure_workarea 0
|
||||
# check if FLASH_OPTR.TZEN is enabled
|
||||
set FLASH_OPTR [mrw 0x40022040]
|
||||
if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
|
||||
echo "TZEN option bit disabled"
|
||||
ahb_ap_non_secure_access
|
||||
} {
|
||||
ahb_ap_secure_access
|
||||
echo "TZEN option bit enabled"
|
||||
set use_secure_workarea 1
|
||||
}
|
||||
|
||||
set workarea_addr [$_TARGETNAME cget -work-area-phys]
|
||||
echo "workarea_addr $workarea_addr"
|
||||
|
||||
if {$use_secure_workarea} {
|
||||
set workarea_addr [expr {$workarea_addr | 0x10000000}]
|
||||
} {
|
||||
set workarea_addr [expr {$workarea_addr & ~0x10000000}]
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-phys $workarea_addr
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event trace-config {
|
||||
# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
|
||||
# change this value accordingly to configure trace pins
|
||||
|
|
|
|||
Loading…
Reference in New Issue