From c917af5e1635db4727dddc1627becd1352e62f15 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 13 Dec 2024 10:31:03 +0800 Subject: [PATCH] src/target/riscv: conditionally log priv register read failures - Only log error if target is not running or in debug running state. - Refine logging for consistency across functions. Change-Id: Ic1a8b0e379dca06f01786feb9aa9ef5892e1d789 Signed-off-by: Huaqi Fang <578567190@qq.com> --- src/target/riscv/riscv.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 925b9bfbf..5a2c1c305 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -2813,7 +2813,8 @@ static int riscv_effective_privilege_mode(struct target *target, int *v_mode, in { riscv_reg_t priv; if (riscv_reg_get(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) { - LOG_TARGET_ERROR(target, "Failed to read priv register."); + if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) + LOG_TARGET_ERROR(target, "Failed to read priv register."); return ERROR_FAIL; } *v_mode = get_field(priv, VIRT_PRIV_V); @@ -2844,7 +2845,8 @@ static int riscv_mmu(struct target *target, int *enabled) /* Don't use MMU in explicit or effective M (machine) mode */ riscv_reg_t priv; if (riscv_reg_get(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) { - LOG_TARGET_ERROR(target, "Failed to read priv register."); + if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) + LOG_TARGET_ERROR(target, "Failed to read priv register."); return ERROR_FAIL; } @@ -3146,7 +3148,8 @@ static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_ riscv_reg_t priv; if (riscv_reg_get(target, &priv, GDB_REGNO_PRIV) != ERROR_OK) { - LOG_TARGET_ERROR(target, "Failed to read priv register."); + if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING) + LOG_TARGET_ERROR(target, "Failed to read priv register."); return ERROR_FAIL; }