interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

I do not know why this is necessary, but it fixes strange effects 

(step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen 

git-svn-id: svn://svn.berlios.de/openocd/trunk@1008 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2008-09-26 18:00:10 +00:00
parent e5408ce0b6
commit c90c48b00b
1 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/target/cortex_m3.c
View File

@ -376,7 +376,7 @@ int cortex_m3_debug_entry(target_t *target)
int cortex_m3_poll(target_t *target)
{
int retval;
u32 prev_target_state = target->state;
enum target_state prev_target_state = target->state;
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
@ -762,6 +762,13 @@ int cortex_m3_assert_reset(target_t *target)
/* this causes the luminary device to reset using the watchdog */
ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ );
LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
{
/* I do not know why this is necessary, but it fixes strange effects
(step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
u32 tmp;
ahbap_read_system_atomic_u32(swjdp, NVIC_AIRCR, &tmp );
}
}
target->state = TARGET_RESET;