target/riscv: improve register caching (prep_*, cleanup_*)
Introduce riscv_write_register to prep_for_register/vector_access and cleanup_after_register/vector_access. Change-Id: I77a0a06ac6f12eceec309f0aff94aa77bd56ff55 Signed-off-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
This commit is contained in:
Evgeniy Naydanov
parent
8f3a617dc7
commit
c822dc8194
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@ -1065,35 +1065,54 @@ static int is_vector_reg(enum gdb_regno gdb_regno)
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gdb_regno == GDB_REGNO_VLENB;
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}
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static int prep_for_register_access(struct target *target, riscv_reg_t *mstatus,
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enum gdb_regno regno)
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static int prep_for_register_access(struct target *target,
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riscv_reg_t *orig_mstatus, enum gdb_regno regno)
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{
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if (is_fpu_reg(regno) || is_vector_reg(regno)) {
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if (register_read_direct(target, mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
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assert(orig_mstatus);
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if (!is_fpu_reg(regno) && !is_vector_reg(regno))
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/* No special preparation needed */
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return ERROR_OK;
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LOG_TARGET_DEBUG(target, "Preparing mstatus to access %s",
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gdb_regno_name(regno));
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/* FIXME: On a running target, there is no way to make sure mstatus won't
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* change between reading and writing it, so
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* if target->state != TARGET_HALTED an error should be returned here.
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* However, this would not allow access to FPU registers on the running
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* target.
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* See https://github.com/riscv/riscv-openocd/pull/842#discussion_r1178500114
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*/
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if (riscv_get_register(target, orig_mstatus, GDB_REGNO_MSTATUS) != ERROR_OK)
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return ERROR_FAIL;
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if (is_fpu_reg(regno) && (*mstatus & MSTATUS_FS) == 0) {
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if (register_write_direct(target, GDB_REGNO_MSTATUS,
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set_field(*mstatus, MSTATUS_FS, 1)) != ERROR_OK)
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riscv_reg_t new_mstatus = *orig_mstatus;
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riscv_reg_t field_mask = is_fpu_reg(regno) ? MSTATUS_FS : MSTATUS_VS;
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if ((new_mstatus & field_mask) != 0)
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return ERROR_OK;
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new_mstatus = set_field(new_mstatus, field_mask, 1);
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if (riscv_write_register(target, GDB_REGNO_MSTATUS, new_mstatus) != ERROR_OK)
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return ERROR_FAIL;
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} else if (is_vector_reg(regno) && (*mstatus & MSTATUS_VS) == 0) {
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if (register_write_direct(target, GDB_REGNO_MSTATUS,
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set_field(*mstatus, MSTATUS_VS, 1)) != ERROR_OK)
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return ERROR_FAIL;
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}
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} else {
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*mstatus = 0;
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}
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LOG_TARGET_DEBUG(target, "Prepared to access %s (mstatus=0x%" PRIx64 ")",
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gdb_regno_name(regno), new_mstatus);
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return ERROR_OK;
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}
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static int cleanup_after_register_access(struct target *target,
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riscv_reg_t mstatus, enum gdb_regno regno)
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{
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if ((is_fpu_reg(regno) && (mstatus & MSTATUS_FS) == 0) ||
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(is_vector_reg(regno) && (mstatus & MSTATUS_VS) == 0))
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if (register_write_direct(target, GDB_REGNO_MSTATUS, mstatus) != ERROR_OK)
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return ERROR_FAIL;
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if (!is_fpu_reg(regno) && !is_vector_reg(regno))
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/* Mstatus was not changed for this register access. No need to restore it. */
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return ERROR_OK;
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LOG_TARGET_DEBUG(target, "Restoring mstatus to 0x%" PRIx64, mstatus);
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return riscv_write_register(target, GDB_REGNO_MSTATUS, mstatus);
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}
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typedef enum {
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@ -1913,69 +1932,78 @@ static COMMAND_HELPER(riscv013_print_info, struct target *target)
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return 0;
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}
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static int prep_for_vector_access(struct target *target, riscv_reg_t *saved_vtype,
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riscv_reg_t *saved_vl, unsigned int *debug_vl, unsigned int *debug_vsew)
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static int try_set_vsew(struct target *target, unsigned int *debug_vsew)
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{
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RISCV_INFO(r);
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/* TODO: this continuous save/restore is terrible for performance. */
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/* Write vtype and vl. */
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/* Save vtype and vl. */
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if (register_read_direct(target, saved_vtype, GDB_REGNO_VTYPE) != ERROR_OK)
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return ERROR_FAIL;
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if (register_read_direct(target, saved_vl, GDB_REGNO_VL) != ERROR_OK)
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return ERROR_FAIL;
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while (true) {
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unsigned int encoded_vsew;
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if (riscv_xlen(target) == 64 && r->vsew64_supported != YNM_NO) {
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encoded_vsew = 3;
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*debug_vsew = 64;
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} else {
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encoded_vsew = 2;
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*debug_vsew = 32;
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}
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unsigned int encoded_vsew =
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(riscv_xlen(target) == 64 && r->vsew64_supported != YNM_NO) ? 3 : 2;
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/* Set standard element width to match XLEN, for vmv instruction to move
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* the least significant bits into a GPR. */
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if (register_write_direct(target, GDB_REGNO_VTYPE, encoded_vsew << 3) != ERROR_OK)
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* the least significant bits into a GPR.
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*/
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if (riscv_write_register(target, GDB_REGNO_VTYPE, encoded_vsew << 3) != ERROR_OK)
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return ERROR_FAIL;
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if (*debug_vsew == 64 && r->vsew64_supported == YNM_MAYBE) {
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if (encoded_vsew == 3 && r->vsew64_supported == YNM_MAYBE) {
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/* Check that it's supported. */
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uint64_t vtype;
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if (register_read_direct(target, &vtype, GDB_REGNO_VTYPE) != ERROR_OK)
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riscv_reg_t vtype;
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if (riscv_get_register(target, &vtype, GDB_REGNO_VTYPE) != ERROR_OK)
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return ERROR_FAIL;
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if (vtype >> (riscv_xlen(target) - 1)) {
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r->vsew64_supported = YNM_NO;
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/* Try again. */
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continue;
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} else {
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return try_set_vsew(target, debug_vsew);
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}
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r->vsew64_supported = YNM_YES;
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}
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}
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break;
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}
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*debug_vsew = encoded_vsew == 3 ? 64 : 32;
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return ERROR_OK;
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}
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static int prep_for_vector_access(struct target *target,
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riscv_reg_t *orig_mstatus, riscv_reg_t *orig_vtype, riscv_reg_t *orig_vl,
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unsigned int *debug_vl, unsigned int *debug_vsew)
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{
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assert(orig_mstatus);
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assert(orig_vtype);
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assert(orig_vl);
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assert(debug_vl);
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assert(debug_vsew);
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RISCV_INFO(r);
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if (target->state != TARGET_HALTED) {
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LOG_TARGET_ERROR(target,
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"Unable to access vector register: target not halted");
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return ERROR_FAIL;
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}
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if (prep_for_register_access(target, orig_mstatus, GDB_REGNO_VL) != ERROR_OK)
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return ERROR_FAIL;
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/* Save vtype and vl. */
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if (riscv_get_register(target, orig_vtype, GDB_REGNO_VTYPE) != ERROR_OK)
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return ERROR_FAIL;
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if (riscv_get_register(target, orig_vl, GDB_REGNO_VL) != ERROR_OK)
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return ERROR_FAIL;
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if (try_set_vsew(target, debug_vsew) != ERROR_OK)
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return ERROR_FAIL;
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/* Set the number of elements to be updated with results from a vector
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* instruction, for the vslide1down instruction.
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* Set it so the entire V register is updated. */
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*debug_vl = DIV_ROUND_UP(r->vlenb * 8, *debug_vsew);
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if (register_write_direct(target, GDB_REGNO_VL, *debug_vl) != ERROR_OK)
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return ERROR_FAIL;
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return ERROR_OK;
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return riscv_write_register(target, GDB_REGNO_VL, *debug_vl);
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}
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static int cleanup_after_vector_access(struct target *target, riscv_reg_t vtype,
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riscv_reg_t vl)
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static int cleanup_after_vector_access(struct target *target,
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riscv_reg_t mstatus, riscv_reg_t vtype, riscv_reg_t vl)
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{
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/* Restore vtype and vl. */
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if (register_write_direct(target, GDB_REGNO_VTYPE, vtype) != ERROR_OK)
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if (riscv_write_register(target, GDB_REGNO_VTYPE, vtype) != ERROR_OK)
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return ERROR_FAIL;
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if (register_write_direct(target, GDB_REGNO_VL, vl) != ERROR_OK)
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if (riscv_write_register(target, GDB_REGNO_VL, vl) != ERROR_OK)
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return ERROR_FAIL;
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return ERROR_OK;
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return cleanup_after_register_access(target, mstatus, GDB_REGNO_VL);
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}
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static int riscv013_get_register_buf(struct target *target,
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@ -1989,13 +2017,10 @@ static int riscv013_get_register_buf(struct target *target,
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if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
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return ERROR_FAIL;
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riscv_reg_t mstatus;
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if (prep_for_register_access(target, &mstatus, regno) != ERROR_OK)
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return ERROR_FAIL;
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riscv_reg_t vtype, vl;
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riscv_reg_t mstatus, vtype, vl;
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unsigned int debug_vl, debug_vsew;
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if (prep_for_vector_access(target, &vtype, &vl, &debug_vl, &debug_vsew) != ERROR_OK)
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if (prep_for_vector_access(target, &mstatus, &vtype, &vl,
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&debug_vl, &debug_vsew) != ERROR_OK)
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return ERROR_FAIL;
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unsigned vnum = regno - GDB_REGNO_V0;
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@ -2022,16 +2047,14 @@ static int riscv013_get_register_buf(struct target *target,
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return ERROR_FAIL;
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buf_set_u64(value, debug_vsew * i, debug_vsew, v);
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} else {
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LOG_TARGET_ERROR(target, "Failed to execute vmv/vslide1down while reading %s",
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LOG_TARGET_ERROR(target,
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"Failed to execute vmv/vslide1down while reading %s",
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gdb_regno_name(regno));
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break;
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}
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}
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if (cleanup_after_vector_access(target, vtype, vl) != ERROR_OK)
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return ERROR_FAIL;
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if (cleanup_after_register_access(target, mstatus, regno) != ERROR_OK)
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if (cleanup_after_vector_access(target, mstatus, vtype, vl) != ERROR_OK)
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return ERROR_FAIL;
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return result;
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@ -2048,13 +2071,10 @@ static int riscv013_set_register_buf(struct target *target,
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if (riscv_save_register(target, GDB_REGNO_S0) != ERROR_OK)
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return ERROR_FAIL;
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riscv_reg_t mstatus;
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if (prep_for_register_access(target, &mstatus, regno) != ERROR_OK)
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return ERROR_FAIL;
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riscv_reg_t vtype, vl;
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riscv_reg_t mstatus, vtype, vl;
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unsigned int debug_vl, debug_vsew;
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if (prep_for_vector_access(target, &vtype, &vl, &debug_vl, &debug_vsew) != ERROR_OK)
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if (prep_for_vector_access(target, &mstatus, &vtype, &vl,
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&debug_vl, &debug_vsew) != ERROR_OK)
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return ERROR_FAIL;
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unsigned vnum = regno - GDB_REGNO_V0;
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@ -2072,10 +2092,7 @@ static int riscv013_set_register_buf(struct target *target,
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break;
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}
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if (cleanup_after_vector_access(target, vtype, vl) != ERROR_OK)
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return ERROR_FAIL;
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if (cleanup_after_register_access(target, mstatus, regno) != ERROR_OK)
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if (cleanup_after_vector_access(target, mstatus, vtype, vl) != ERROR_OK)
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return ERROR_FAIL;
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return result;
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