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Added asser_reset and deassert_reset for cortex_a8 

git-svn-id: svn://svn.berlios.de/openocd/trunk@2791 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
mlu 2009-10-02 16:36:03 +00:00
parent 1033633321
commit c74ede4248
1 changed files with 56 additions and 22 deletions
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78
src/target/cortex_a8.c
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@ -67,6 +67,8 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target,
uint32_t *value, int regnum); uint32_t *value, int regnum);
int cortex_a8_dap_write_coreregister_u32(target_t *target, int cortex_a8_dap_write_coreregister_u32(target_t *target,
uint32_t value, int regnum); uint32_t value, int regnum);
int cortex_a8_assert_reset(target_t *target);
int cortex_a8_deassert_reset(target_t *target);
target_type_t cortexa8_target = target_type_t cortexa8_target =
{ {
@ -138,8 +140,13 @@ int cortex_a8_init_debug_access(target_t *target)
/* Clear Sticky Power Down status Bit in PRSR to enable access to /* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */ the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy); retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
/* Enabling of instruction execution in debug mode is done in debug_entry code */ /* Enabling of instruction execution in debug mode is done in debug_entry code */
/* Resync breakpoint registers */
/* Since this is likley called from init or reset, update targtet state information*/
cortex_a8_poll(target);
return retval; return retval;
} }
@ -303,7 +310,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
armv4_5_common_t *armv4_5 = target->arch_info; armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info; swjdp_common_t *swjdp = &armv7a->swjdp_info;
if (Rd > 16) if (Rd > 16)
return retval; return retval;
@ -1188,6 +1195,33 @@ int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
* Cortex-A8 Reset fuctions * Cortex-A8 Reset fuctions
*/ */
int cortex_a8_assert_reset(target_t *target)
{
LOG_DEBUG(" ");
/* registers are now invalid */
armv4_5_invalidate_core_regs(target);
target->state = TARGET_RESET;
return ERROR_OK;
}
int cortex_a8_deassert_reset(target_t *target)
{
LOG_DEBUG(" ");
if (target->reset_halt)
{
int retval;
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
}
return ERROR_OK;
}
/* /*
* Cortex-A8 Memory access * Cortex-A8 Memory access
@ -1265,23 +1299,23 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address,
exit(-1); exit(-1);
} }
/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
/* invalidate I-Cache */ /* invalidate I-Cache */
if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
{ {
/* Invalidate ICache single entry with MVA, repeat this for all cache /* Invalidate ICache single entry with MVA, repeat this for all cache
lines in the address range, Cortex-A8 has fixed 64 byte line length */ lines in the address range, Cortex-A8 has fixed 64 byte line length */
/* Invalidate Cache single entry with MVA to PoU */ /* Invalidate Cache single entry with MVA to PoU */
for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */ armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
} }
/* invalidate D-Cache */ /* invalidate D-Cache */
if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{ {
/* Invalidate Cache single entry with MVA to PoC */ /* Invalidate Cache single entry with MVA to PoC */
for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */ armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
} }
return retval; return retval;
} }
@ -1374,7 +1408,7 @@ int cortex_a8_examine(struct target_s *target)
uint32_t didr, ctypr, ttypr, cpuid; uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("TODO"); LOG_DEBUG("TODO");
/* Here we shall insert a proper ROM Table scan */ /* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE; armv7a->debug_base = OMAP3530_DEBUG_BASE;
@ -1451,7 +1485,7 @@ int cortex_a8_examine(struct target_s *target)
/* Configure core debug access */ /* Configure core debug access */
cortex_a8_init_debug_access(target); cortex_a8_init_debug_access(target);
target->type->examined = 1; target->type->examined = 1;
return retval; return retval;