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target/lakemont: Use 'bool' data type 

Change-Id: I9baaf617c2bfabd07ac3ca195e486893d7950398
Signed-off-by: Marc Schink <openocd-dev@marcschink.de>
Reviewed-on: http://openocd.zylin.com/4969
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Marc Schink 2019-02-26 14:10:09 +01:00 committed by Tomas Vanek
parent ffd8e2b630
commit c69da2eb0c
1 changed files with 12 additions and 12 deletions
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24
src/target/lakemont.c
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@ -322,8 +322,8 @@ static int restore_context(struct target *t)
} }
for (i = 0; i < (x86_32->cache->num_regs); i++) { for (i = 0; i < (x86_32->cache->num_regs); i++) {
x86_32->cache->reg_list[i].dirty = 0; x86_32->cache->reg_list[i].dirty = false;
x86_32->cache->reg_list[i].valid = 0; x86_32->cache->reg_list[i].valid = false;
} }
return err; return err;
} }
@ -357,8 +357,8 @@ static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
if (check_not_halted(t)) if (check_not_halted(t))
return ERROR_TARGET_NOT_HALTED; return ERROR_TARGET_NOT_HALTED;
buf_set_u32(reg->value, 0, 32, value); buf_set_u32(reg->value, 0, 32, value);
reg->dirty = 1; reg->dirty = true;
reg->valid = 1; reg->valid = true;
return ERROR_OK; return ERROR_OK;
} }
@ -405,8 +405,8 @@ struct reg_cache *lakemont_build_reg_cache(struct target *t)
reg_list[i].name = regs[i].name; reg_list[i].name = regs[i].name;
reg_list[i].size = 32; reg_list[i].size = 32;
reg_list[i].value = calloc(1, 4); reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0; reg_list[i].dirty = false;
reg_list[i].valid = 0; reg_list[i].valid = false;
reg_list[i].type = &lakemont_reg_type; reg_list[i].type = &lakemont_reg_type;
reg_list[i].arch_info = &arch_info[i]; reg_list[i].arch_info = &arch_info[i];
@ -667,8 +667,8 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach
*regval = buf_get_u32(scan.out, 0, 32); *regval = buf_get_u32(scan.out, 0, 32);
if (cache) { if (cache) {
buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval); buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval);
x86_32->cache->reg_list[reg].valid = 1; x86_32->cache->reg_list[reg].valid = true;
x86_32->cache->reg_list[reg].dirty = 0; x86_32->cache->reg_list[reg].dirty = false;
} }
LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32, LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32,
x86_32->cache->reg_list[reg].name, x86_32->cache->reg_list[reg].name,
@ -709,8 +709,8 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach
/* we are writing from the cache so ensure we reset flags */ /* we are writing from the cache so ensure we reset flags */
if (cache) { if (cache) {
x86_32->cache->reg_list[reg].dirty = 0; x86_32->cache->reg_list[reg].dirty = false;
x86_32->cache->reg_list[reg].valid = 0; x86_32->cache->reg_list[reg].valid = false;
} }
return ERROR_OK; return ERROR_OK;
} }
@ -947,8 +947,8 @@ int lakemont_poll(struct target *t)
* breakpoint instruction. This needs to be corrected. * breakpoint instruction. This needs to be corrected.
*/ */
buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1); buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
x86_32->cache->reg_list[EIP].dirty = 1; x86_32->cache->reg_list[EIP].dirty = true;
x86_32->cache->reg_list[EIP].valid = 1; x86_32->cache->reg_list[EIP].valid = true;
LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1); LOG_USER("hit software breakpoint at 0x%08" PRIx32, eip-1);
} else { } else {
/* it's not a hardware breakpoint (checked already in DR6 state) /* it's not a hardware breakpoint (checked already in DR6 state)