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Make reset work again for multicore 

Both regular multicore and RTOS hack methods.

Change-Id: I9a0998de0f33ef8a4d163f36ddf01c7675893b3d
This commit is contained in:
Tim Newsome 2018-03-23 12:53:24 -07:00
parent d7282d0bfe
commit c534a37fc3
2 changed files with 79 additions and 80 deletions
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5
src/target/riscv/batch.c
View File

@ -160,11 +160,10 @@ void dump_field(const struct scan_field *field)
log_printf_lf(LOG_LVL_DEBUG, log_printf_lf(LOG_LVL_DEBUG,
__FILE__, __LINE__, __PRETTY_FUNCTION__, __FILE__, __LINE__, __PRETTY_FUNCTION__,
"%db %s %08x @%02x -> %s %08x @%02x [0x%p -> 0x%p]", "%db %s %08x @%02x -> %s %08x @%02x",
field->num_bits, field->num_bits,
op_string[out_op], out_data, out_address, op_string[out_op], out_data, out_address,
status_string[in_op], in_data, in_address, status_string[in_op], in_data, in_address);
field->out_value, field->in_value);
} else { } else {
log_printf_lf(LOG_LVL_DEBUG, log_printf_lf(LOG_LVL_DEBUG,
__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?", __FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?",

154
src/target/riscv/riscv-013.c
View File

@ -1346,7 +1346,8 @@ static int examine(struct target *target)
if (!riscv_havereset_not_supported && if (!riscv_havereset_not_supported &&
get_field(s, DMI_DMSTATUS_ANYHAVERESET)) get_field(s, DMI_DMSTATUS_ANYHAVERESET))
dmi_write(target, DMI_DMCONTROL, dmi_write(target, DMI_DMCONTROL,
DMI_DMCONTROL_DMACTIVE | DMI_DMCONTROL_ACKHAVERESET); set_field(DMI_DMCONTROL_DMACTIVE | DMI_DMCONTROL_ACKHAVERESET,
hartsel_mask(target), i));
if (!riscv_is_halted(target)) { if (!riscv_is_halted(target)) {
if (riscv013_halt_current_hart(target) != ERROR_OK) { if (riscv013_halt_current_hart(target) != ERROR_OK) {
@ -1518,7 +1519,7 @@ static int assert_reset(struct target *target)
/* TODO: Try to use hasel in dmcontrol */ /* TODO: Try to use hasel in dmcontrol */
/* Set haltreq/resumereq for each hart. */ /* Set haltreq for each hart. */
uint32_t control = control_base; uint32_t control = control_base;
for (int i = 0; i < riscv_count_harts(target); ++i) { for (int i = 0; i < riscv_count_harts(target); ++i) {
if (!riscv_hart_enabled(target, i)) if (!riscv_hart_enabled(target, i))
@ -1539,20 +1540,8 @@ static int assert_reset(struct target *target)
r->current_hartid); r->current_hartid);
control = set_field(control, DMI_DMCONTROL_HALTREQ, control = set_field(control, DMI_DMCONTROL_HALTREQ,
target->reset_halt ? 1 : 0); target->reset_halt ? 1 : 0);
control = set_field(control, DMI_DMCONTROL_HARTRESET, 1); control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
dmi_write(target, DMI_DMCONTROL, control); dmi_write(target, DMI_DMCONTROL, control);
/* Read back to check if hartreset is supported. */
uint32_t rb;
if (dmi_read(target, &rb, DMI_DMCONTROL) != ERROR_OK)
return ERROR_FAIL;
if (!get_field(rb, DMI_DMCONTROL_HARTRESET)) {
/* Use ndmreset instead. That will reset the entire device, but
* that's probably what OpenOCD wants anyway. */
control = set_field(control, DMI_DMCONTROL_HARTRESET, 0);
control = set_field(control, DMI_DMCONTROL_NDMRESET, 1);
dmi_write(target, DMI_DMCONTROL, control);
}
} }
target->state = TARGET_RESET; target->state = TARGET_RESET;
@ -1569,69 +1558,83 @@ static int deassert_reset(struct target *target)
/* Clear the reset, but make sure haltreq is still set */ /* Clear the reset, but make sure haltreq is still set */
uint32_t control = 0; uint32_t control = 0;
control = set_field(control, DMI_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0); control = set_field(control, DMI_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0);
control = set_field(control, hartsel_mask(target), r->current_hartid);
control = set_field(control, DMI_DMCONTROL_DMACTIVE, 1); control = set_field(control, DMI_DMCONTROL_DMACTIVE, 1);
dmi_write(target, DMI_DMCONTROL, control); dmi_write(target, DMI_DMCONTROL,
set_field(control, hartsel_mask(target), r->current_hartid));
uint32_t dmstatus; uint32_t dmstatus;
int dmi_busy_delay = info->dmi_busy_delay; int dmi_busy_delay = info->dmi_busy_delay;
time_t start = time(NULL); time_t start = time(NULL);
if (!riscv_havereset_not_supported) { for (int i = 0; i < riscv_count_harts(target); ++i) {
LOG_DEBUG("Waiting for hart %d to be reset.", r->current_hartid); int index = i;
do { if (target->rtos) {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK) if (!riscv_hart_enabled(target, index))
return ERROR_FAIL; continue;
dmi_write(target, DMI_DMCONTROL,
if (time(NULL) - start > riscv_reset_timeout_sec) { set_field(control, hartsel_mask(target), index));
LOG_ERROR("Hart %d didn't reset in %ds; dmstatus=0x%x; " } else {
"Increase the timeout with riscv set_reset_timeout_sec.", index = r->current_hartid;
r->current_hartid, riscv_reset_timeout_sec, dmstatus);
return ERROR_FAIL;
}
} while (get_field(dmstatus, DMI_DMSTATUS_ALLHAVERESET) == 0);
/* Ack reset. */
dmi_write(target, DMI_DMCONTROL, control | DMI_DMCONTROL_ACKHAVERESET);
}
if (target->reset_halt) {
LOG_DEBUG("Waiting for hart %d to be halted.", r->current_hartid);
while (get_field(dmstatus, DMI_DMSTATUS_ALLHALTED) == 0) {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
if (time(NULL) - start > riscv_reset_timeout_sec) {
LOG_ERROR("Hart %d didn't halt coming out of reset in %ds; "
"dmstatus=0x%x; "
"Increase the timeout with riscv set_reset_timeout_sec.",
r->current_hartid, riscv_reset_timeout_sec, dmstatus);
return ERROR_FAIL;
}
} }
target->state = TARGET_HALTED;
control = set_field(control, DMI_DMCONTROL_HALTREQ, 0); if (!riscv_havereset_not_supported) {
dmi_write(target, DMI_DMCONTROL, control); LOG_DEBUG("Waiting for hart %d to be reset.", index);
do {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
} else { if (time(NULL) - start > riscv_reset_timeout_sec) {
LOG_DEBUG("Waiting for hart %d to be running.", r->current_hartid); LOG_ERROR("Hart %d didn't reset in %ds; dmstatus=0x%x; "
while (get_field(dmstatus, DMI_DMSTATUS_ALLRUNNING) == 0) { "Increase the timeout with riscv set_reset_timeout_sec.",
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK) r->current_hartid, riscv_reset_timeout_sec, dmstatus);
return ERROR_FAIL; return ERROR_FAIL;
if (get_field(dmstatus, DMI_DMSTATUS_ANYHALTED) || }
get_field(dmstatus, DMI_DMSTATUS_ANYUNAVAIL)) { } while (get_field(dmstatus, DMI_DMSTATUS_ALLHAVERESET) == 0);
LOG_ERROR("Unexpected hart %d status during reset. dmstatus=0x%x", /* Ack reset. */
r->current_hartid, dmstatus); dmi_write(target, DMI_DMCONTROL,
return ERROR_FAIL; set_field(control, hartsel_mask(target), index) |
} DMI_DMCONTROL_ACKHAVERESET);
if (time(NULL) - start > riscv_reset_timeout_sec) {
LOG_ERROR("Hart %d didn't run coming out of reset in %ds; "
"dmstatus=0x%x; "
"Increase the timeout with riscv set_reset_timeout_sec.",
r->current_hartid, riscv_reset_timeout_sec, dmstatus);
return ERROR_FAIL;
}
} }
target->state = TARGET_RUNNING;
if (target->reset_halt) {
LOG_DEBUG("Waiting for hart %d to be halted.", index);
do {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
if (time(NULL) - start > riscv_reset_timeout_sec) {
LOG_ERROR("Hart %d didn't halt coming out of reset in %ds; "
"dmstatus=0x%x; "
"Increase the timeout with riscv set_reset_timeout_sec.",
index, riscv_reset_timeout_sec, dmstatus);
return ERROR_FAIL;
}
} while (get_field(dmstatus, DMI_DMSTATUS_ALLHALTED) == 0);
target->state = TARGET_HALTED;
} else {
LOG_DEBUG("Waiting for hart %d to be running.", index);
while (get_field(dmstatus, DMI_DMSTATUS_ALLRUNNING) == 0) {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
if (get_field(dmstatus, DMI_DMSTATUS_ANYHALTED) ||
get_field(dmstatus, DMI_DMSTATUS_ANYUNAVAIL)) {
LOG_ERROR("Unexpected hart %d status during reset. dmstatus=0x%x",
index, dmstatus);
return ERROR_FAIL;
}
if (time(NULL) - start > riscv_reset_timeout_sec) {
LOG_ERROR("Hart %d didn't run coming out of reset in %ds; "
"dmstatus=0x%x; "
"Increase the timeout with riscv set_reset_timeout_sec.",
index, riscv_reset_timeout_sec, dmstatus);
return ERROR_FAIL;
}
}
target->state = TARGET_RUNNING;
}
if (!target->rtos)
break;
} }
info->dmi_busy_delay = dmi_busy_delay; info->dmi_busy_delay = dmi_busy_delay;
return ERROR_OK; return ERROR_OK;
@ -2707,11 +2710,9 @@ static int riscv013_step_or_resume_current_hart(struct target *target, bool step
return ERROR_FAIL; return ERROR_FAIL;
/* Issue the resume command, and then wait for the current hart to resume. */ /* Issue the resume command, and then wait for the current hart to resume. */
uint32_t dmcontrol; uint32_t dmcontrol = DMI_DMCONTROL_DMACTIVE;
if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK) dmcontrol = set_field(dmcontrol, hartsel_mask(target), r->current_hartid);
return ERROR_FAIL; dmi_write(target, DMI_DMCONTROL, dmcontrol | DMI_DMCONTROL_RESUMEREQ);
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 1);
dmi_write(target, DMI_DMCONTROL, dmcontrol);
uint32_t dmstatus; uint32_t dmstatus;
for (size_t i = 0; i < 256; ++i) { for (size_t i = 0; i < 256; ++i) {
@ -2723,17 +2724,16 @@ static int riscv013_step_or_resume_current_hart(struct target *target, bool step
if (step && get_field(dmstatus, DMI_DMSTATUS_ALLHALTED) == 0) if (step && get_field(dmstatus, DMI_DMSTATUS_ALLHALTED) == 0)
continue; continue;
dmcontrol = set_field(dmcontrol, DMI_DMCONTROL_RESUMEREQ, 0);
dmi_write(target, DMI_DMCONTROL, dmcontrol); dmi_write(target, DMI_DMCONTROL, dmcontrol);
return ERROR_OK; return ERROR_OK;
} }
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK) LOG_ERROR("unable to resume hart %d", r->current_hartid);
return ERROR_FAIL;
if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK) if (dmi_read(target, &dmcontrol, DMI_DMCONTROL) != ERROR_OK)
return ERROR_FAIL; return ERROR_FAIL;
LOG_ERROR("unable to resume hart %d", r->current_hartid);
LOG_ERROR(" dmcontrol=0x%08x", dmcontrol); LOG_ERROR(" dmcontrol=0x%08x", dmcontrol);
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
LOG_ERROR(" dmstatus =0x%08x", dmstatus); LOG_ERROR(" dmstatus =0x%08x", dmstatus);
if (step) { if (step) {