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src/target/riscv: make sure hart is halted when reset halt is requested 

This patch is used to fix Error: timed out while waiting for target halted
when executing monitor reset halt for some nuclei fpga bitstreams

1. we need to issue halt req when halt is required
2. we need to wait if halt req is sent, and wait for the halt req
   really finished

Change-Id: I1be58732eb2a96d91173f1cfee1d6ac6cb9fe17a
Signed-off-by: Huaqi Fang <578567190@qq.com>
This commit is contained in:
Huaqi Fang 2025-01-21 17:42:17 +08:00
parent 553428e08e
commit c382f7c9e7
1 changed files with 9 additions and 0 deletions
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9
src/target/riscv/riscv-013.c
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@ -3008,12 +3008,21 @@ static int deassert_reset(struct target *target)
control = 0;
control = set_field(control, DM_DMCONTROL_DMACTIVE, 1);
control = set_field(control, DM_DMCONTROL_ACKHAVERESET, 1);
control = set_field(control, DM_DMCONTROL_HALTREQ, target->reset_halt ? 1 : 0);
control = set_dmcontrol_hartsel(control, info->index);
result = dm_write(target, DM_DMCONTROL, control);
if (result != ERROR_OK)
return result;
/* If reset halt is set, should wait until all harts are not running */
if (target->reset_halt) {
for (size_t i = 0; i < 256; ++i) {
if (dmstatus_read(target, &dmstatus, true) != ERROR_OK)
return ERROR_FAIL;
/* When no harts are running, there's no point in continuing this loop. */
if (!get_field(dmstatus, DM_DMSTATUS_ANYRUNNING))
break;
}
target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_DBGRQ;
} else {