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target: arm: disassembler: decode v6T2 ARM DSB instruction 

Change-Id: Id91b1a87d34982c72f2a8ab46564c961d1fef9dc
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3894
Tested-by: jenkins
This commit is contained in:
Paul Fertser 2016-12-02 20:03:07 +03:00
parent de974eaed3
commit c26bbf7a1b
2 changed files with 42 additions and 0 deletions
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41
src/target/arm_disassembler.c
View File

@ -129,6 +129,47 @@ static int evaluate_pld(uint32_t opcode,
return ERROR_OK; return ERROR_OK;
} }
/* DSB */
if ((opcode & 0x07f000f0) == 0x05700040) {
instruction->type = ARM_DSB;
char *opt;
switch (opcode & 0x0000000f) {
case 0xf:
opt = "SY";
break;
case 0xe:
opt = "ST";
break;
case 0xb:
opt = "ISH";
break;
case 0xa:
opt = "ISHST";
break;
case 0x7:
opt = "NSH";
break;
case 0x6:
opt = "NSHST";
break;
case 0x3:
opt = "OSH";
break;
case 0x2:
opt = "OSHST";
break;
default:
opt = "UNK";
}
snprintf(instruction->text,
128,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tDSB %s",
address, opcode, opt);
return ERROR_OK;
}
return evaluate_unknown(opcode, address, instruction); return evaluate_unknown(opcode, address, instruction);
} }

1
src/target/arm_disassembler.h
View File

@ -106,6 +106,7 @@ enum arm_instruction_type {
ARM_MCRR, ARM_MCRR,
ARM_MRRC, ARM_MRRC,
ARM_PLD, ARM_PLD,
ARM_DSB,
ARM_QADD, ARM_QADD,
ARM_QDADD, ARM_QDADD,
ARM_QSUB, ARM_QSUB,