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flash/nor/nrf5: unify size of HWID 

HWID is a part of 32 bit CONFIGID register. hwid member of struct nrf5_info
was typed uint32_t to enable direct CONFIGID read and masked afterwards.

Change to uint16_t to unify with hwid in struct nrf5_device_spec
and RM description.

Change-Id: Ib720d3ce23c301aee41d074ea78a6f00a23aed68
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5589
Tested-by: jenkins
This commit is contained in:
Tomas Vanek 2020-04-13 20:19:41 +02:00
parent a5bf98f846
commit c1f4d9e6e8
1 changed files with 6 additions and 5 deletions
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11
src/flash/nor/nrf5.c
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@ -158,7 +158,7 @@ struct nrf5_info {
bool ficr_info_valid;
struct nrf52_ficr_info ficr_info;
const struct nrf5_device_spec *spec;
uint32_t hwid;
uint16_t hwid;
enum nrf5_features features;
unsigned int flash_size_kb;
unsigned int ram_size_kb;
@ -648,7 +648,7 @@ static int nrf5_info(struct flash_bank *bank, char *buf, int buf_size)
variant, &variant[2]);
} else {
res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%08" PRIx32 ")",
res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")",
chip->hwid);
}
if (res <= 0)
@ -765,14 +765,15 @@ static int nrf5_probe(struct flash_bank *bank)
struct nrf5_info *chip = nbank->chip;
struct target *target = chip->target;
res = target_read_u32(target, NRF5_FICR_CONFIGID, &chip->hwid);
uint32_t configid;
res = target_read_u32(target, NRF5_FICR_CONFIGID, &configid);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read CONFIGID register");
return res;
}
chip->hwid &= 0xFFFF; /* HWID is stored in the lower two
* bytes of the CONFIGID register */
/* HWID is stored in the lower two bytes of the CONFIGID register */
chip->hwid = configid & 0xFFFF;
/* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
chip->features = NRF5_FEATURE_SERIES_51;