interesting
/
riscv-openocd
mirror of https://github.com/riscv/riscv-openocd.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

deleted superfluous sam7s256 which was identical to sam7x256 

git-svn-id: svn://svn.berlios.de/openocd/trunk@924 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe 2008-08-17 19:32:44 +00:00
parent 8ca8313c43
commit c1683a55bc
3 changed files with 2 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/target/Makefile.am
View File

@ -20,8 +20,8 @@ noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7t
etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h
nobase_dist_pkglib_DATA = xscale/debug_handler.bin target/at91eb40a.cfg \
event/at91r40008_reset.script event/sam7s256_reset.script event/sam7x256_reset.script \
target/at91r40008.cfg target/lpc2148.cfg target/lpc2148_rclk.cfg target/lpc2148_2mhz.cfg target/lpc2294.cfg target/sam7s256.cfg \
event/at91r40008_reset.script event/sam7x256_reset.script \
target/at91r40008.cfg target/lpc2148.cfg target/lpc2148_rclk.cfg target/lpc2148_2mhz.cfg target/lpc2294.cfg \
target/sam7x256.cfg target/str710.cfg target/str912.cfg target/nslu2.cfg target/pxa255_sst.cfg \
target/pxa255.cfg target/zy1000.cfg event/zy1000_reset.script event/at91sam9260_reset.script target/at91sam9260.cfg \
target/wi-9c.cfg event/wi-9c_reset.script event/pxa255_reset.script target/stm32.cfg target/xba_revA3.cfg event/xba_revA3.script \

23
src/target/event/sam7s256_reset.script
View File

@ -1,23 +0,0 @@
#
# Init - taken form the script openocd_at91sam7_ecr.script
#
# I take this script from the following page:
#
# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html
#
# disable watchdog
mww 0xfffffd44 0x00008000
# enable user reset
mww 0xfffffd08 0xa5000001
# CKGR_MOR : enable the main oscillator
mww 0xfffffc20 0x00000601
sleep 10
# CKGR_PLLR: 96.1097 MHz
mww 0xfffffc2c 0x00481c0e
sleep 10
# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
mww 0xfffffc30 0x00000007
sleep 10
# MC_FMR: flash mode (FWS=1,FMCN=60)
mww 0xffffff60 0x003c0100
sleep 100

21
src/target/target/sam7s256.cfg
View File

@ -1,21 +0,0 @@
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config srst_only srst_pulls_trst
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag_device 4 0x1 0xf 0xe
#target <type> <startup mode>
#target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
target arm7tdmi little 0 arm7tdmi
target_script 0 reset event/sam7s256_reset.script
working_area 0 0x00200000 0x4000 nobackup
#flash bank <driver> <base> <size> <chip_width> <bus_width>
flash bank at91sam7 0 0 0 0 0
# For more information about the configuration files, take a look at:
# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger