+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | RES001 |
+ AT91FR40162 |
+ ZY1000 |
+ Reset halt on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > mdw 0x01000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ > reset halt
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0x600000d3 pc: 0x00008a70
+ >
+
+ |
+ PASS |
+
+
+ | RES002 |
+ AT91FR40162 |
+ ZY1000 |
+ Reset init on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset init |
+ Reset should return without error and the output should contain
executing reset script 'name_of_the_script' |
+
+
+ > reset init
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0x600000d3 pc: 0x00008ea4
+ >
+
+ |
+ PASS
+ NOTE! Even if there is no message, the reset script is being executed (proved by side effects) |
+
+
+ | RES003 |
+ AT91FR40162 |
+ ZY1000 |
+ Reset after a power cycle of the target |
+ Reset the target then power cycle the target |
+ Connect via the telnet interface and type
reset halt after the power was detected |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ Sensed nSRST asserted
+ Sensed power dropout.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0xd5dff7e6
+ Sensed power restore.
+ Sensed nSRST deasserted
+ > reset halt
+ JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0x0000072c
+ >
+
+ |
+ PASS |
+
+
+ | RES004 |
+ AT91FR40162 |
+ ZY1000 |
+ Reset halt on a blank target where reset halt is supported |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted
pc = 0 |
+
+ > reset halt
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0x00008b38
+ >
+ |
+ PASS |
+
+
+ | RES005 |
+ AT91FR40162 |
+ ZY1000 |
+ Reset halt on a blank target using return clock |
+ Erase all the content of the flash, set the configuration script to use RCLK |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ N/A, At91EB40A does NOT have support for RCLK
+
+ |
+ N/A |
+
+
+
+
+
+ | ID |
+ Target |
+ ZY1000 |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | SPD001 |
+ AT91FR40162 |
+ ZY1000 |
+ 16MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > reset halt
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0x00008ae8
+ > jtag_khz 16000
+ jtag_speed 4 => JTAG clk=16.000000
+ 16000 kHz
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+ PASS |
+
+
+ | SPD002 |
+ AT91FR40162 |
+ ZY1000 |
+ 8MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > reset halt
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0x00008c14
+ > jtag_khz 8000
+ jtag_speed 8 => JTAG clk=8.000000
+ 8000 kHz
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+ | SPD003 |
+ AT91FR40162 |
+ ZY1000 |
+ 4MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > reset halt
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0x00008bc4
+ > jtag_khz 4000
+ jtag_speed 16 => JTAG clk=4.000000
+ 4000 kHz
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+ | SPD004 |
+ AT91FR40162 |
+ ZY1000 |
+ 2MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > reset halt
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0x00009678
+ > jtag_khz 2000
+ jtag_speed 32 => JTAG clk=2.000000
+ 2000 kHz
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+ | SPD005 |
+ AT91FR40162 |
+ ZY1000 |
+ RCLK on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 0
+ RCLK - adaptive
+ RCLK timeout
+
+ N/A for this target
+ |
+ N/A for this target |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | DBG001 |
+ AT91FR40162 |
+ ZY1000 |
+ Load is working |
+ Reset init is working, RAM is accesible, GDB server is started |
+ On the console of the OS:
+ $ arm-none-eabi-gdb redboot_ram.elf
+ (gdb) target remote ip:port
+ (gdb) load
+ |
+ Load should return without error, typical output looks like:
+
+ Loading section .text, size 0x14c lma 0x0
+ Start address 0x40, load size 332
+ Transfer rate: 180 bytes/sec, 332 bytes/write.
+
+ |
+
+ (gdb) load
+ Loading section .rom_vectors, size 0x40 lma 0xc000
+ Loading section .text, size 0x103e8 lma 0xc040
+ Loading section .rodata, size 0x1a84 lma 0x1c428
+ Loading section .data, size 0x3ec lma 0x1deac
+ Start address 0xc040, load size 74392
+ Transfer rate: 572 KB/sec, 9299 bytes/write.
+ (gdb)
+ |
+ PASS |
+
+
+
+ | DBG002 |
+ AT91FR40162 |
+ ZY1000 |
+ Software breakpoint |
+ Load the redboot_ram.elf application, use instructions from GDB001 |
+ In the GDB console:
+
+ (gdb) monitor arm7_9 dbgrq enable
+ software breakpoints enabled
+ (gdb) break cyg_start
+ Breakpoint 1 at 0xec: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+
+ |
+ The software breakpoint should be reached, a typical output looks like:
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor arm7_9 dbgrq enable
+ use of EmbeddedICE dbgrq instead of breakpoint for target halt enabled
+ (gdb) break cyg_start
+
+ Breakpoint 1 at 0x155b8: file /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c, line 264.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, cyg_start ()
+ at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264
+ 264 CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG003 |
+ AT91FR40162 |
+ ZY1000 |
+ Single step in a RAM application |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
(gdb) step |
+ The next instruction should be reached, typical output:
+
+ (gdb) step
+ 70 DWORD b = 2;
+
+
+ |
+
+
+ (gdb) step
+ 266 CYGACC_CALL_IF_MONITOR_RETURN_SET(return_to_redboot);
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG004 |
+ AT91FR40162 |
+ ZY1000 |
+ Software break points are working after a reset |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
+ (gdb) monitor reset init
+ (gdb) load
+ (gdb) continue
+ |
+ The breakpoint should be reached, typical output:
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+ (gdb) moni reset init
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0x600000d3 pc: 0x00008ae8
+ (gdb) load
+ Loading section .rom_vectors, size 0x40 lma 0xc000
+ Loading section .text, size 0x103e8 lma 0xc040
+ Loading section .rodata, size 0x1a84 lma 0x1c428
+ Loading section .data, size 0x3ec lma 0x1deac
+ Start address 0xc040, load size 74392
+ Transfer rate: 576 KB/sec, 9299 bytes/write.
+ (gdb) c
+ Continuing.
+
+ Breakpoint 1, cyg_start ()
+ at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264
+ 264 CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);
+ (gdb)
+ |
+ PASS |
+
+
+ | DBG005 |
+ AT91FR40162 |
+ ZY1000 |
+ Hardware breakpoint |
+ Flash the redboot_rom.elf application. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset init
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) load
+ Loading section .rom_vectors, size 0x40 lma 0x1000000
+ Loading section .text, size 0x10638 lma 0x1000040
+ Loading section .rodata, size 0x1a84 lma 0x1010678
+ Loading section .data, size 0x428 lma 0x10120fc
+ Start address 0x1000040, load size 75044
+ Transfer rate: 33 KB/sec, 9380 bytes/write.
+ (gdb) break cyg_start
+ Breakpoint 1 at 0x100979c: file /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c, line 264.
+ (gdb) c
+ Continuing.
+ Note: automatically using hardware breakpoints for read-only addresses.
+
+ Breakpoint 1, cyg_start () at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264
+ 264 CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG006 |
+ AT91FR40162 |
+ ZY1000 |
+ Hardware breakpoint is set after a reset |
+ Follow the instructions to flash and insert a hardware breakpoint from DBG005 |
+ In GDB, type
+
+ (gdb) monitor reset
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue
+
+ where the value inserted in PC is the start address of the application
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) moni reset init
+ JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0x200000d3 pc: 0x01000200
+ (gdb) moni reg pc 0x1000000
+ pc (/32): 0x01000000
+ (gdb) c
+ Continuing.
+
+ Breakpoint 1, cyg_start () at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264
+ 264 CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG007 |
+ AT91FR40162 |
+ ZY1000 |
+ Single step in ROM |
+ Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step
+
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+
+ |
+
+ Breakpoint 1, cyg_start () at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264
+ 264 CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);
+ (gdb) step
+ 266 CYGACC_CALL_IF_MONITOR_RETURN_SET(return_to_redboot);
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | FLA001 |
+ AT91FR40162 |
+ ZY1000 |
+ Flash probe |
+ Reset init is working |
+ On the telnet interface:
+ > flash probe 0
+ |
+ The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
+ flash 'ecosflash' found at 0x01000000
+ |
+
+
+ > flash probe 0
+ flash 'ecosflash' found at 0x01000000
+
+ |
+ PASS |
+
+
+ | FLA002 |
+ AT91FR40162 |
+ ZY1000 |
+ flash fillw |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash fillw 0x100000 0xdeadbeef 16
+
+ |
+ The commands should execute without error. The output looks like:
+
+ wrote 64 bytes to 0x0100000 in 11.610000s (0.091516 kb/s)
+
+ To verify the contents of the flash:
+
+ > mdw 0x100000 32
+ 0x0100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x0100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash fillw 0x01000000 0xdeadbeef 16
+ wrote 64 bytes to 0x01000000 in 0.010000s (6.250 kb/s)
+ > mdw 0x1000000 32
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+ |
+ PASS |
+
+
+ | FLA003 |
+ AT91FR40162 |
+ ZY1000 |
+ Flash erase |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash erase_address 0x100000 0x2000
+
+ |
+ The commands should execute without error.
+
+ erased address 0x0100000 length 8192 in 4.970000s
+
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.
+
+ > mdw 0x100000 32
+ 0x0100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x0100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash erase_address 0x1000000 0x10000
+ erased address 0x01000000 (length 65536) in 0.840000s (76.190 kb/s)
+ > mdw 0x1000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ |
+ PASS |
+
+
+ | FLA004 |
+ AT91FR40162 |
+ ZY1000 |
+ Loading to flash from GDB |
+ Reset init is working, flash is probed, connectivity to GDB server is working |
+ Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
+
+ (gdb) target remote ip:port
+ (gdb) monitor reset halt
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor verify_image path_to_elf_file
+
+ |
+ The output should look like:
+
+ verified 404 bytes in 5.060000s
+
+ The failure message is something like:
+ Verify operation failed address 0x00200000. Was 0x00 instead of 0x18
+ |
+
+
+ (gdb) load
+ Loading section .rom_vectors, size 0x40 lma 0x1000000
+ Loading section .text, size 0x10638 lma 0x1000040
+ Loading section .rodata, size 0x1a84 lma 0x1010678
+ Loading section .data, size 0x428 lma 0x10120fc
+ Start address 0x1000040, load size 75044
+ Transfer rate: 34 KB/sec, 9380 bytes/write.
+ (gdb) moni verify_image /tftp/10.0.0.190/redboot_rom.elf
+ keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1820). Workaround: increase "set remotetimeout" in GDB
+ verified 75044 bytes in 1.960000s (37.390 kb/s)
+
+ |
+ PASS |
+
+
+
+
+
\ No newline at end of file
diff --git a/testing/results/v0.4.0-rc1/LPC2148.html b/testing/results/v0.4.0-rc1/LPC2148.html
new file mode 100755
index 000000000..425b52484
--- /dev/null
+++ b/testing/results/v0.4.0-rc1/LPC2148.html
@@ -0,0 +1,933 @@
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | RES001 |
+ LPC2148 |
+ ZY1000 |
+ Reset halt on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ >
+
+ |
+ PASS |
+
+
+ | RES002 |
+ LPC2148 |
+ ZY1000 |
+ Reset init on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset init |
+ Reset should return without error and the output should contain
executing reset script 'name_of_the_script' |
+
+
+ > reset init
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2da
+ core state: ARM
+ >
+
+ |
+ PASS
+ NOTE! Even if there is no message, the reset script is being executed (proved by side effects) |
+
+
+ | RES003 |
+ LPC2148 |
+ ZY1000 |
+ Reset after a power cycle of the target |
+ Reset the target then power cycle the target |
+ Connect via the telnet interface and type
reset halt after the power was detected |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ nsed nSRST asserted.
+ nsed power dropout.
+ nsed power restore.
+ SRST took 186ms to deassert
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ core state: ARM
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ >
+
+ |
+ PASS |
+
+
+ | RES004 |
+ LPC2148 |
+ ZY1000 |
+ Reset halt on a blank target where reset halt is supported |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted
pc = 0 |
+
+
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ >
+
+ |
+ PASS |
+
+
+ | RES005 |
+ LPC2148 |
+ ZY1000 |
+ Reset halt on a blank target using return clock |
+ Erase all the content of the flash, set the configuration script to use RCLK |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > jtag_khz 0
+ RCLK - adaptive
+ > reset init
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ core state: ARM
+ >
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ ZY1000 |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | SPD001 |
+ LPC2148 |
+ ZY1000 |
+ 16MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 16000
+ jtag_speed 4 => JTAG clk=16.000000
+ 16000 kHz
+ > reset halt
+ JTAG scan chain interrogation failed: all zeroes
+ Check JTAG interface, timings, target power, etc.
+ error: -100
+ Command handler execution failed
+ in procedure 'reset' called at file "command.c", line 638
+ called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ ThumbEE -- incomplete support
+ target state: halted
+ target halted in ThumbEE state due to debug-request, current mode: System
+ cpsr: 0x1fffffff pc: 0xfffffffa
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: System
+ cpsr: 0xc00003ff pc: 0xfffffff0
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ ThumbEE -- incomplete support
+ target state: halted
+ target halted in ThumbEE state due to debug-request, current mode: System
+ cpsr: 0xffffffff pc: 0xfffffffa
+ >
+
+ |
+ FAIL |
+
+
+ | SPD002 |
+ LPC2148 |
+ ZY1000 |
+ 8MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 8000
+ jtag_speed 8 => JTAG clk=8.000000
+ 8000 kHz
+ > reset halt
+ JTAG scan chain interrogation failed: all zeroes
+ Check JTAG interface, timings, target power, etc.
+ error: -100
+ Command handler execution failed
+ in procedure 'reset' called at file "command.c", line 638
+ called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ invalid mode value encountered 0
+ cpsr contains invalid mode value - communication failure
+ >
+
+ |
+ FAIL |
+
+
+ | SPD003 |
+ LPC2148 |
+ ZY1000 |
+ 4MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 4000
+ jtag_speed 16 => JTAG clk=4.000000
+ 4000 kHz
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)
+ JTAG tap: lpc2148.cpu UNEXPECTED: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)
+ JTAG tap: lpc2148.cpu expected 1 of 1: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ Unexpected idcode after end of chain: 64 0x0000007f
+ Unexpected idcode after end of chain: 160 0x0000007f
+ Unexpected idcode after end of chain: 192 0x0000007f
+ Unexpected idcode after end of chain: 320 0x0000007f
+ Unexpected idcode after end of chain: 352 0x0000007f
+ Unexpected idcode after end of chain: 384 0x0000007f
+ Unexpected idcode after end of chain: 480 0x0000007f
+ Unexpected idcode after end of chain: 512 0x0000007f
+ Unexpected idcode after end of chain: 544 0x0000007f
+ double-check your JTAG setup (interface, speed, missing TAPs, ...)
+ error: -100
+ Command handler execution failed
+ in procedure 'reset' called at file "command.c", line 638
+ called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352
+ >
+
+ |
+ FAIL |
+
+
+ | SPD004 |
+ LPC2148 |
+ ZY1000 |
+ 2MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 2000
+ jtag_speed 32 => JTAG clk=2.000000
+ 2000 kHz
+ > reset halt
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2da
+ > mdw 0 32
+ 0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093
+ 0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+ | SPD005 |
+ LPC2148 |
+ ZY1000 |
+ RCLK on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 0
+ RCLK - adaptive
+ > mdw 0 32
+ 0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093
+ 0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | DBG001 |
+ LPC2148 |
+ ZY1000 |
+ Load is working |
+ Reset init is working, RAM is accesible, GDB server is started |
+ On the console of the OS:
+ arm-elf-gdb test_ram.elf
+ (gdb) target remote ip:port
+ (gdb) load
+ |
+ Load should return without error, typical output looks like:
+
+ Loading section .text, size 0x14c lma 0x0
+ Start address 0x40, load size 332
+ Transfer rate: 180 bytes/sec, 332 bytes/write.
+
+ |
+
+ (gdb) load
+ Loading section .text, size 0x16c lma 0x40000000
+ Start address 0x40000040, load size 364
+ Transfer rate: 32 KB/sec, 364 bytes/write.
+ (gdb)
+ |
+ PASS |
+
+
+
+ | DBG002 |
+ LPC2148 |
+ ZY1000 |
+ Software breakpoint |
+ Load the test_ram.elf application, use instructions from GDB001 |
+ In the GDB console:
+
+ (gdb) monitor gdb_breakpoint_override soft
+ software breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0xec: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+
+ |
+ The software breakpoint should be reached, a typical output looks like:
+
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor gdb_breakpoint_override soft
+ force soft breakpoints
+ Current language: auto
+ The current source language is "auto; currently asm".
+ (gdb) break main
+ Breakpoint 1 at 0x4000010c: file src/main.c, line 71.
+ (gdb) c
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ Current language: auto
+ The current source language is "auto; currently c".
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG003 |
+ LPC2148 |
+ ZY1000 |
+ Single step in a RAM application |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
(gdb) step |
+ The next instruction should be reached, typical output:
+
+ (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f0
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f4
+ 72 DWORD b = 2;
+
+ |
+
+
+ (gdb) step
+ 72 DWORD b = 2;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG004 |
+ LPC2148 |
+ ZY1000 |
+ Software break points are working after a reset |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
+ (gdb) monitor reset init
+ (gdb) load
+ (gdb) continue
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+
+ |
+
+ (gdb) moni reset init
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in Thumb state due to debug-request, current mode: Supervisor
+ cpsr: 0xa00000f3 pc: 0x7fffd2d6
+ core state: ARM
+ (gdb) load
+ Loading section .text, size 0x16c lma 0x40000000
+ Start address 0x40000040, load size 364
+ Transfer rate: 27 KB/sec, 364 bytes/write.
+ (gdb) c
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ (gdb)
+ |
+ PASS |
+
+
+ | DBG005 |
+ LPC2148 |
+ ZY1000 |
+ Hardware breakpoint |
+ Flash the test_rom.elf application. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset init
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0x10c: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+ Note: automatically using hardware breakpoints for read-only addresses.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ Current language: auto
+ The current source language is "auto; currently c".
+ (gdb)
+
+ |
+ PASS NOTE: This test is failing from time to time, not able to describe a cause |
+
+
+ | DBG006 |
+ LPC2148 |
+ ZY1000 |
+ Hardware breakpoint is set after a reset |
+ Follow the instructions to flash and insert a hardware breakpoint from DBG005 |
+ In GDB, type
+
+ (gdb) monitor reset
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue
+
+ where the value inserted in PC is the start address of the application
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor reset init
+ JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00000160
+ core state: ARM
+ (gdb) monitor reg pc 0x40
+ pc (/32): 0x00000040
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG007 |
+ LPC2148 |
+ ZY1000 |
+ Single step in ROM |
+ Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step
+
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+
+ |
+
+ (gdb) load
+ Loading section .text, size 0x16c lma 0x0
+ Start address 0x40, load size 364
+ Transfer rate: 637 bytes/sec, 364 bytes/write.
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ Current language: auto
+ The current source language is "auto; currently asm".
+ (gdb) break main
+ Breakpoint 1 at 0x10c: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+ Note: automatically using hardware breakpoints for read-only addresses.
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+ Current language: auto
+ The current source language is "auto; currently c".
+ (gdb) step
+ 72 DWORD b = 2;
+ (gdb)
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | FLA001 |
+ LPC2148 |
+ ZY1000 |
+ Flash probe |
+ Reset init is working |
+ On the telnet interface:
+ > flash probe 0
+ |
+ The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
+ flash 'ecosflash' found at 0x01000000
+ |
+
+
+ > flash probe 0
+ flash 'lpc2000' found at 0x00000000
+
+ |
+ PASS |
+
+
+ | FLA002 |
+ LPC2148 |
+ ZY1000 |
+ flash fillw |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash fillw 0x1000000 0xdeadbeef 16
+
+ |
+ The commands should execute without error. The output looks like:
+
+ wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
+
+ To verify the contents of the flash:
+
+ > mdw 0x1000000 32
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash fillw 0x0 0xdeadbeef 16
+ Verification will fail since checksum in image (0xdeadbeef) to be written to flash is different from calculated vector checksum (0xe93fc777).
+ To remove this warning modify build tools on developer PC to inject correct LPC vector checksum.
+ wrote 64 bytes to 0x00000000 in 0.040000s (1.563 kb/s)
+ > mdw 0 32
+ 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef e93fc777 deadbeef deadbeef
+ 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+ |
+ FAIL |
+
+
+ | FLA003 |
+ LPC2148 |
+ ZY1000 |
+ Flash erase |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash erase_address 0x1000000 0x2000
+
+ |
+ The commands should execute without error.
+
+ erased address 0x01000000 length 8192 in 4.970000s
+
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.
+
+ > mdw 0x1000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash erase_address 0 0x2000
+ erased address 0x00000000 (length 8192) in 0.510000s (15.686 kb/s)
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+ |
+ PASS |
+
+
+
+ | FLA004 |
+ LPC2148 |
+ ZY1000 |
+ Loading to flash from GDB |
+ Reset init is working, flash is probed, connectivity to GDB server is working |
+ Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
+
+ (gdb) target remote ip:port
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor verify_image path_to_elf_file
+
+ |
+ The output should look like:
+
+ verified 404 bytes in 5.060000s
+
+ The failure message is something like:
+ Verify operation failed address 0x00200000. Was 0x00 instead of 0x18
+ |
+
+
+ (gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf
+ checksum mismatch - attempting binary compare
+ Verify operation failed address 0x00000014. Was 0x58 instead of 0x60
+
+ Command handler execution failed
+ in procedure 'verify_image' called at file "command.c", line 647
+ called at file "command.c", line 361
+ (gdb)
+
+ |
+ FAIL |
+
+
+
+
+
\ No newline at end of file
diff --git a/testing/results/v0.4.0-rc1/SAM7.html b/testing/results/v0.4.0-rc1/SAM7.html
new file mode 100755
index 000000000..a400a476f
--- /dev/null
+++ b/testing/results/v0.4.0-rc1/SAM7.html
@@ -0,0 +1,853 @@
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | RES001 |
+ SAM7S64 |
+ ZY1000 |
+ Reset halt on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ > reset halt
+ SRST took 2ms to deassert
+ JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x600000d3 pc: 0x000003c4
+ >
+
+ |
+ PASS |
+
+
+ | RES002 |
+ SAM7S64 |
+ ZY1000 |
+ Reset init on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset init |
+ Reset should return without error and the output should contain
executing reset script 'name_of_the_script' |
+
+
+ > reset init
+ SRST took 2ms to deassert
+ JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x600000d3 pc: 0x000003c0
+ >
+
+ |
+ PASS
+ NOTE! Even if there is no message, the reset script is being executed (proved by side effects) |
+
+
+ | RES003 |
+ SAM7S64 |
+ ZY1000 |
+ Reset after a power cycle of the target |
+ Reset the target then power cycle the target |
+ Connect via the telnet interface and type
reset halt after the power was detected |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ Sensed nSRST asserted
+ Sensed power dropout.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0xd5dff7e6
+ Sensed power restore.
+ Sensed nSRST deasserted
+ > reset halt
+ JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0xf00000d3 pc: 0x0000072c
+ >
+
+ |
+ PASS |
+
+
+ | RES004 |
+ SAM7S64 |
+ ZY1000 |
+ Reset halt on a blank target where reset halt is supported |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted
pc = 0 |
+
+
+ > reset halt
+ SRST took 2ms to deassert
+ JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x300000d3 pc: 0x000003c0
+
+ |
+ PASS |
+
+
+ | RES005 |
+ SAM7S64 |
+ ZY1000 |
+ Reset halt on a blank target using return clock |
+ Erase all the content of the flash, set the configuration script to use RCLK |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > jtag_khz 0
+ jtag_khz: 0
+ > reset init
+ SRST took 2ms to deassert
+ JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x300000d3 pc: 0x000003c0
+ executing event/sam7s256_reset.script
+ >
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ ZY1000 |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | SPD001 |
+ SAM7S64 |
+ ZY1000 |
+ 16MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 16000
+ jtag_speed 4 => JTAG clk=16.000000
+ jtag_khz: 16000
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+ | SPD002 |
+ SAM7S64 |
+ ZY1000 |
+ 8MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 8000
+ jtag_speed 8 => JTAG clk=8.000000
+ jtag_khz: 8000
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+ PASS |
+
+
+ | SPD003 |
+ SAM7S64 |
+ ZY1000 |
+ 4MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 4000
+ jtag_speed 16 => JTAG clk=4.000000
+ jtag_khz: 4000
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+ | SPD004 |
+ SAM7S64 |
+ ZY1000 |
+ 2MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 2000
+ jtag_speed 32 => JTAG clk=2.000000
+ jtag_khz: 2000
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+ | SPD005 |
+ SAM7S64 |
+ ZY1000 |
+ RCLK on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+ > jtag_khz 0
+ jtag_khz: 0
+ > mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | DBG001 |
+ SAM7S64 |
+ ZY1000 |
+ Load is working |
+ Reset init is working, RAM is accesible, GDB server is started |
+ On the console of the OS:
+ arm-elf-gdb test_ram.elf
+ (gdb) target remote ip:port
+ (gdb) load
+ |
+ Load should return without error, typical output looks like:
+
+ Loading section .text, size 0x14c lma 0x0
+ Start address 0x40, load size 332
+ Transfer rate: 180 bytes/sec, 332 bytes/write.
+
+ |
+
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x200000
+ Start address 0x200040, load size 404
+ Transfer rate: 443 bytes/sec, 404 bytes/write.
+ (gdb)
+ |
+ PASS |
+
+
+
+ | DBG002 |
+ SAM7S64 |
+ ZY1000 |
+ Software breakpoint |
+ Load the test_ram.elf application, use instructions from GDB001 |
+ In the GDB console:
+
+ (gdb) monitor arm7_9 dbgrq enable
+ software breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0xec: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+
+ |
+ The software breakpoint should be reached, a typical output looks like:
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor arm7_9 dbgrq enable
+ use of EmbeddedICE dbgrq instead of breakpoint for target halt enabled
+ (gdb) break main
+ Breakpoint 1 at 0x200134: file src/main.c, line 69.
+ (gdb) c
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ Current language: auto
+ The current source language is "auto; currently c".
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG003 |
+ SAM7S64 |
+ ZY1000 |
+ Single step in a RAM application |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
(gdb) step |
+ The next instruction should be reached, typical output:
+
+ (gdb) step
+ 70 DWORD b = 2;
+
+
+ |
+
+
+ (gdb) step
+ 70 DWORD b = 2;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG004 |
+ SAM7S64 |
+ ZY1000 |
+ Software break points are working after a reset |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
+ (gdb) monitor reset init
+ (gdb) load
+ (gdb) continue
+ |
+ The breakpoint should be reached, typical output:
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+ (gdb) monitor reset init
+ JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug-request, current mode: Supervisor
+ cpsr: 0x600000d3 pc: 0x0000031c
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x200000
+ Start address 0x200040, load size 404
+ Transfer rate: 26 KB/sec, 404 bytes/write.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb)
+ |
+ PASS |
+
+
+ | DBG005 |
+ SAM7S64 |
+ ZY1000 |
+ Hardware breakpoint |
+ Flash the test_rom.elf application. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset init
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+ Note: automatically using hardware breakpoints for read-only addresses.
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100134
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG006 |
+ SAM7S64 |
+ ZY1000 |
+ Hardware breakpoint is set after a reset |
+ Follow the instructions to flash and insert a hardware breakpoint from DBG005 |
+ In GDB, type
+
+ (gdb) monitor reset
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue
+
+ where the value inserted in PC is the start address of the application
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+ (gdb) monitor reset init
+ SRST took 3ms to deassert
+ JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)
+ srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+ target state: halted
+ target halted in ARM state due to debug request, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100168
+ executing event/sam7s256_reset.script
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue
+ Continuing.
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100040
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100134
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG007 |
+ SAM7S64 |
+ ZY1000 |
+ Single step in ROM |
+ Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step
+
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+
+ |
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x00100138
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+ (gdb)
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | FLA001 |
+ SAM7S64 |
+ ZY1000 |
+ Flash probe |
+ Reset init is working |
+ On the telnet interface:
+ > flash probe 0
+ |
+ The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
+ flash 'ecosflash' found at 0x01000000
+ |
+
+
+ > flash probe 0
+ flash 'at91sam7' found at 0x00100000
+
+ |
+ PASS |
+
+
+ | FLA002 |
+ SAM7S64 |
+ ZY1000 |
+ flash fillw |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash fillw 0x100000 0xdeadbeef 16
+
+ |
+ The commands should execute without error. The output looks like:
+
+ wrote 64 bytes to 0x0100000 in 11.610000s (0.091516 kb/s)
+
+ To verify the contents of the flash:
+
+ > mdw 0x100000 32
+ 0x0100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x0100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash fillw 0x100000 0xdeadbeef 16
+ wrote 64 bytes to 0x00100000 in 0.040000s (26.562500 kb/s)
+ > mdw 0x100000 32
+ 0x00100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+ |
+ PASS |
+
+
+ | FLA003 |
+ SAM7S64 |
+ ZY1000 |
+ Flash erase |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash erase_address 0x100000 0x2000
+
+ |
+ The commands should execute without error.
+
+ erased address 0x0100000 length 8192 in 4.970000s
+
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.
+
+ > mdw 0x100000 32
+ 0x0100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x0100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash erase_address 0x100000 0x2000
+ erased address 0x00100000 length 8192 in 0.020000s
+ > mdw 0x100000 32
+ 0x00100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+ |
+ PASS |
+
+
+ | FLA004 |
+ SAM7S64 |
+ ZY1000 |
+ Loading to flash from GDB |
+ Reset init is working, flash is probed, connectivity to GDB server is working |
+ Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
+
+ (gdb) target remote ip:port
+ (gdb) monitor reset halt
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor verify_image path_to_elf_file
+
+ |
+ The output should look like:
+
+ verified 404 bytes in 5.060000s
+
+ The failure message is something like:
+ Verify operation failed address 0x00200000. Was 0x00 instead of 0x18
+ |
+
+
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 4 KB/sec, 404 bytes/write.
+ (gdb) moni verify_image /tftp/10.0.0.9/c:/temp/testing/examples/SAM7S256Test/test_rom.elf
+ verified 404 bytes in 0.570000s
+
+ |
+ PASS |
+
+
+
+
+
\ No newline at end of file
diff --git a/testing/results/v0.4.0-rc1/STR710.html b/testing/results/v0.4.0-rc1/STR710.html
new file mode 100755
index 000000000..1a18ad0e6
--- /dev/null
+++ b/testing/results/v0.4.0-rc1/STR710.html
@@ -0,0 +1,907 @@
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | RES001 |
+ STR912 |
+ ZY1000 |
+ Reset halt on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+> mdw 0 32
+0x00000000: 75755000 8a930104 65696f65 939a3e98 214751f1 fa0edb9b 6664686d 931a989e
+0x00000020: 676c65e4 9a0a0982 25653445 da02ba90 c4ed3165 9b9a8a9a 65676365 01981292
+0x00000040: 212e0982 82ba3f8b 34674765 96ba1a9a 6175e7e5 9b9ab91a 0789644d 120a9a18
+0x00000060: 65446167 80d20982 6d6d6565 187090ca 65277d65 9a9a0b81 6960416c 9ffe88b8
+> reset
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+>
+
+ |
+ PASS |
+
+
+ | RES002 |
+ STR912 |
+ ZY1000 |
+ Reset init on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset init |
+ Reset should return without error and the output should contain
executing reset script 'name_of_the_script' |
+
+
+> reset init
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+target state: halted
+target halted in ARM state due to debug-request, current mode: Undefined instruction
+cpsr: 0xf00000db pc: 0x00000004
+jtag_speed 10 => JTAG clk=6.400000
+6400 kHz
+
+ |
+ PASS |
+
+
+ | RES003 |
+ STR912 |
+ ZY1000 |
+ Reset after a power cycle of the target |
+ Reset the target then power cycle the target |
+ Connect via the telnet interface and type
reset halt after the power was detected |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ nsed power dropout.
+ nsed power dropout.
+ nsed nSRST deasserted.
+ invalid mode value encountered 0
+cpsr contains invalid mode value - communication failure
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x100000d3 pc: 0x0000001c
+jtag_speed 10 => JTAG clk=6.400000
+6400 kHz
+ nsed power restore.
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x500000d3 pc: 0x00000000
+jtag_speed 10 => JTAG clk=6.400000
+6400 kHz
+> reset init
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x500000d3 pc: 0x00000000
+jtag_speed 10 => JTAG clk=6.400000
+6400 kHz
+>
+
+ |
+ PASS |
+
+
+ | RES004 |
+ STR912 |
+ ZY1000 |
+ Reset halt on a blank target where reset halt is supported |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+> reset halt
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x200000d3 pc: 0xfe50cba4
+>
+
+ |
+ PASS |
+
+
+ | RES005 |
+ STR912 |
+ ZY1000 |
+ Reset halt on a blank target using return clock |
+ Erase all the content of the flash, set the configuration script to use RCLK |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > jtag_khz 0
+RCLK - adaptive
+RCLK timeout
+RCLK timeout
+RCLK timeout
+ > reset halt
+ RCLK timeout
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x200000d3 pc: 0xfe50cb50
+
+ |
+ FAIL |
+
+
+
+
+
+ | ID |
+ Target |
+ ZY1000 |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | SPD001 |
+ STR912 |
+ ZY1000 |
+ 16MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 16000
+jtag_speed 4 => JTAG clk=16.000000
+16000 kHz
+> mdw 0 32
+0x00000000: 75755000 8a930104 65696f65 939a3e98 214751f1 fa0edb9b 6664686d 931a989e
+0x00000020: 676c65e4 9a0a0982 25653445 da02ba90 c4ed3165 9b9a8a9a 65676365 01981292
+0x00000040: 212e0982 82ba3f8b 34674765 96ba1a9a 6175e7e5 9b9ab91a 0789644d 120a9a18
+0x00000060: 65446167 80d20982 6d6d6565 187090ca 65277d65 9a9a0b81 6960416c 9ffe88b8
+>
+
+ |
+ PASS |
+
+
+ | SPD002 |
+ STR912 |
+ ZY1000 |
+ 8MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 8000
+jtag_speed 8 => JTAG clk=8.000000
+8000 kHz
+> mdw 0 32
+0x00000000: 75755000 8a930104 65696f65 939a3e98 214751f1 fa0edb9b 6664686d 931a989e
+0x00000020: 676c65e4 9a0a0982 25653445 da02ba90 c4ed3165 9b9a8a9a 65676365 01981292
+0x00000040: 212e0982 82ba3f8b 34674765 96ba1a9a 6175e7e5 9b9ab91a 0789644d 120a9a18
+0x00000060: 65446167 80d20982 6d6d6565 187090ca 65277d65 9a9a0b81 6960416c 9ffe88b8
+>
+
+ |
+ PASS |
+
+
+ | SPD003 |
+ STR912 |
+ ZY1000 |
+ 4MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 4000
+jtag_speed 16 => JTAG clk=4.000000
+4000 kHz
+> mdw 0 32
+0x00000000: 75755000 8a930104 65696f65 939a3e98 214751f1 fa0edb9b 6664686d 931a989e
+0x00000020: 676c65e4 9a0a0982 25653445 da02ba90 c4ed3165 9b9a8a9a 65676365 01981292
+0x00000040: 212e0982 82ba3f8b 34674765 96ba1a9a 6175e7e5 9b9ab91a 0789644d 120a9a18
+0x00000060: 65446167 80d20982 6d6d6565 187090ca 65277d65 9a9a0b81 6960416c 9ffe88b8
+>
+
+ |
+ PASS |
+
+
+ | SPD004 |
+ STR912 |
+ ZY1000 |
+ 2MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> > jtag_khz 2000
+jtag_speed 32 => JTAG clk=2.000000
+2000 kHz
+> mdw 0 32
+0x00000000: 75755000 8a930104 65696f65 939a3e98 214751f1 fa0edb9b 6664686d 931a989e
+0x00000020: 676c65e4 9a0a0982 25653445 da02ba90 c4ed3165 9b9a8a9a 65676365 01981292
+0x00000040: 212e0982 82ba3f8b 34674765 96ba1a9a 6175e7e5 9b9ab91a 0789644d 120a9a18
+0x00000060: 65446167 80d20982 6d6d6565 187090ca 65277d65 9a9a0b81 6960416c 9ffe88b8
+>
+
+ |
+ PASS |
+
+
+ | SPD005 |
+ STR912 |
+ ZY1000 |
+ RCLK on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 0
+RCLK - adaptive
+RCLK timeout
+RCLK timeout
+RCLK timeout
+
+ |
+ FAIL |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | DBG001 |
+ STR912 |
+ ZY1000 |
+ Load is working |
+ Reset init is working, RAM is accesible, GDB server is started |
+ On the console of the OS:
+ arm-elf-gdb test_ram.elf
+ (gdb) target remote ip:port
+ (gdb) load
+ |
+ Load should return without error, typical output looks like:
+
+ Loading section .text, size 0x14c lma 0x0
+ Start address 0x40, load size 332
+ Transfer rate: 180 bytes/sec, 332 bytes/write.
+
+ |
+
+(gdb) load
+Loading section .text, size 0x1cc lma 0x20000000
+Loading section .vectors, size 0x40 lma 0x200001cc
+Loading section .rodata, size 0x4 lma 0x2000020c
+Start address 0x20000000, load size 528
+Transfer rate: 64 KB/sec, 176 bytes/write.
+(gdb)
+ |
+ PASS |
+
+
+
+ | DBG002 |
+ STR912 |
+ ZY1000 |
+ Software breakpoint |
+ Load the test_ram.elf application, use instructions from GDB001 |
+ In the GDB console:
+
+ (gdb) monitor gdb_breakpoint_override soft
+ force soft breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0xec: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+
+ |
+ The software breakpoint should be reached, a typical output looks like:
+
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+
+ |
+
+
+(gdb) monitor gdb_breakpoint_override soft
+force soft breakpoints
+Current language: auto
+The current source language is "auto; currently asm".
+(gdb) break main
+Breakpoint 1 at 0x20000170: file src/main.c, line 69.
+(gdb) c
+Continuing.
+
+Breakpoint 1, main () at src/main.c:69
+69 DWORD a = 1;
+Current language: auto
+The current source language is "auto; currently c".
+(gdb)
+
+ |
+ PASS |
+
+
+ | DBG003 |
+ STR912 |
+ ZY1000 |
+ Single step in a RAM application |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
(gdb) step |
+ The next instruction should be reached, typical output:
+
+ (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f0
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f4
+ 72 DWORD b = 2;
+
+ |
+
+
+ (gdb) step
+ 70 DWORD b = 2;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG004 |
+ STR912 |
+ ZY1000 |
+ Software break points are working after a reset |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
+ (gdb) monitor reset init
+ (gdb) load
+ (gdb) continue
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+
+ |
+
+((gdb) monitor reset init
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x60000013 pc: 0x200001bc
+jtag_speed 10 => JTAG clk=6.400000
+6400 kHz
+(gdb) load
+Loading section .text, size 0x1cc lma 0x20000000
+Loading section .vectors, size 0x40 lma 0x200001cc
+Loading section .rodata, size 0x4 lma 0x2000020c
+Start address 0x20000000, load size 528
+Transfer rate: 64 KB/sec, 176 bytes/write.
+(gdb) c
+Continuing.
+
+Breakpoint 1, main () at src/main.c:69
+69 DWORD a = 1;
+(gdb)
+ |
+ PASS |
+
+
+ | DBG005 |
+ STR912 |
+ ZY1000 |
+ Hardware breakpoint |
+ Flash the test_rom.elf application. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset init
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+(gdb) monitor gdb_breakpoint_override hard
+force hard breakpoints
+(gdb) break main
+Breakpoint 1 at 0x40000170: file src/main.c, line 69.
+(gdb) c
+Continuing.
+Note: automatically using hardware breakpoints for read-only addresses.
+
+Breakpoint 1, main () at src/main.c:69
+69 DWORD a = 1;
+Current language: auto
+The current source language is "auto; currently c".
+(gdb)
+
+ |
+ PASS |
+
+
+ | DBG006 |
+ STR912 |
+ ZY1000 |
+ Hardware breakpoint is set after a reset |
+ Follow the instructions to flash and insert a hardware breakpoint from DBG005 |
+ In GDB, type
+
+ (gdb) monitor reset
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue
+
+ where the value inserted in PC is the start address of the application
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+(gdb) monitor reset init
+jtag_speed 6400 => JTAG clk=0.010000
+10 kHz
+JTAG tap: str710.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)
+srst pulls trst - can not reset into halted mode. Issuing halt after reset.
+target state: halted
+target halted in ARM state due to debug-request, current mode: Undefined instruction
+cpsr: 0x400000db pc: 0x010aea80
+jtag_speed 10 => JTAG clk=6.400000
+6400 kHz
+(gdb) monitor reg pc 0x40000000
+pc (/32): 0x40000000
+(gdb) c
+Continuing.
+
+Breakpoint 1, main () at src/main.c:69
+69 DWORD a = 1;
+Current language: auto
+The current source language is "auto; currently c".
+(gdb)
+
+ |
+ PASS |
+
+
+ | DBG007 |
+ STR912 |
+ ZY1000 |
+ Single step in ROM |
+ Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step
+
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+
+ |
+
+Breakpoint 2, main () at src/main.c:69
+69 DWORD a = 1;
+Current language: auto
+The current source language is "auto; currently c".
+(gdb) step
+70 DWORD b = 2;
+(gdb)
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | FLA001 |
+ STR912 |
+ ZY1000 |
+ Flash probe |
+ Reset init is working |
+ On the telnet interface:
+ > flash probe 0
+ |
+ The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
+ flash 'ecosflash' found at 0x01000000
+ |
+
+
+ > flash probe 0
+ flash 'str7x' found at 0x40000000
+ >
+
+ |
+ PASS |
+
+
+ | FLA002 |
+ STR912 |
+ ZY1000 |
+ flash fillw |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash fillw 0x1000000 0xdeadbeef 16
+
+ |
+ The commands should execute without error. The output looks like:
+
+ wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
+
+ To verify the contents of the flash:
+
+ > mdw 0x1000000 32
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+ > flash fillw 0x40000000 0xdeadbeef 16
+ wrote 64 bytes to 0x40000000 in 0.000000s (inf kb/s)
+ > mdw 0x40000000 32
+ 0x40000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x40000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x40000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x40000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ >
+ |
+ PASS |
+
+
+ | FLA003 |
+ STR912 |
+ ZY1000 |
+ Flash erase |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash erase_address 0x1000000 0x2000
+
+ |
+ The commands should execute without error.
+
+ erased address 0x01000000 length 8192 in 4.970000s
+
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.
+
+ > mdw 0x1000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+> flash erase_address 0x40000000 0x2000
+erased address 0x40000000 (length 8192) in 0.270000s (29.630 kb/s)
+> mdw 0x40000000 32
+0x40000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x40000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x40000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x40000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+>
+ |
+ PASS |
+
+
+ | FLA004 |
+ STR912 |
+ ZY1000 |
+ Loading to flash from GDB |
+ Reset init is working, flash is probed, connectivity to GDB server is working |
+ Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
+
+ (gdb) target remote ip:port
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor verify_image path_to_elf_file
+
+ |
+ The output should look like:
+
+ verified 404 bytes in 5.060000s
+
+ The failure message is something like:
+ Verify operation failed address 0x00200000. Was 0x00 instead of 0x18
+ |
+
+
+(gdb) load
+Loading section .text, size 0x1cc lma 0x40000000
+Loading section .vectors, size 0x40 lma 0x400001cc
+Loading section .rodata, size 0x4 lma 0x4000020c
+Start address 0x40000000, load size 528
+Transfer rate: 53 bytes/sec, 176 bytes/write.
+(gdb) monitor verify_image /tftp/10.0.0.194/test_rom.elf
+verified 528 bytes in 4.760000s (0.108 kb/s)
+Current language: auto
+The current source language is "auto; currently asm".
+(gdb)
+
+ |
+ PASS |
+
+
+
+
+
\ No newline at end of file
diff --git a/testing/results/v0.4.0-rc1/STR912.html b/testing/results/v0.4.0-rc1/STR912.html
new file mode 100755
index 000000000..c8df03488
--- /dev/null
+++ b/testing/results/v0.4.0-rc1/STR912.html
@@ -0,0 +1,1008 @@
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | RES001 |
+ STR912 |
+ ZY1000 |
+ Reset halt on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+> reset halt
+RCLK - adaptive
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
+Trying to use configured scan chain anyway...
+Bypassing JTAG setup events due to errors
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
+>
+
+ |
+ PASS |
+
+
+ | RES002 |
+ STR912 |
+ ZY1000 |
+ Reset init on a blank target |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset init |
+ Reset should return without error and the output should contain
executing reset script 'name_of_the_script' |
+
+
+> reset init
+RCLK - adaptive
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
+Trying to use configured scan chain anyway...
+Bypassing JTAG setup events due to errors
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+cleared protection for sectors 0 through 7 on flash bank 0
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
+>
+
+ |
+ PASS |
+
+
+ | RES003 |
+ STR912 |
+ ZY1000 |
+ Reset after a power cycle of the target |
+ Reset the target then power cycle the target |
+ Connect via the telnet interface and type
reset halt after the power was detected |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ nsed nSRST asserted.
+ nsed power dropout.
+ nsed power restore.
+RCLK - adaptive
+SRST took 85ms to deassert
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
+Trying to use configured scan chain anyway...
+Bypassing JTAG setup events due to errors
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+cleared protection for sectors 0 through 7 on flash bank 0
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
+> reset halt
+RCLK - adaptive
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
+Trying to use configured scan chain anyway...
+Bypassing JTAG setup events due to errors
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
+>
+
+ |
+ PASS |
+
+
+ | RES004 |
+ STR912 |
+ ZY1000 |
+ Reset halt on a blank target where reset halt is supported |
+ Erase all the content of the flash |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted
pc = 0 |
+
+
+> reset halt
+ RCLK - adaptive
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (Manufacturer: 0x020, Part: 0x4570, Version: 0x0)
+JTAG Tap/device matched
+JTAG tap: str912.cpu tap/device found: 0x25966041 (Manufacturer: 0x020, Part: 0x5966, Version: 0x2)
+JTAG Tap/device matched
+JTAG tap: str912.bs tap/device found: 0x2457f041 (Manufacturer: 0x020, Part: 0x457f, Version: 0x2)
+JTAG Tap/device matched
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+>
+ |
+ PASS |
+
+
+ | RES005 |
+ STR912 |
+ ZY1000 |
+ Reset halt on a blank target using return clock |
+ Erase all the content of the flash, set the configuration script to use RCLK |
+ Connect via the telnet interface and type
reset halt |
+ Reset should return without error and the output should contain
target state: halted |
+
+
+ > reset halt
+RCLK - adaptive
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
+Trying to use configured scan chain anyway...
+Bypassing JTAG setup events due to errors
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
+>
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ ZY1000 |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | SPD001 |
+ STR912 |
+ ZY1000 |
+ 16MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 16000
+jtag_speed 4 => JTAG clk=16.000000
+16000 kHz
+ThumbEE -- incomplete support
+target state: halted
+target halted in ThumbEE state due to debug-request, current mode: System
+cpsr: 0xfdfdffff pc: 0xfdfdfff9
+> mdw 0 32
+0x00000000: 00000000 00000000 ffffffff ffffffff 00000001 ffffffff 00000001 ffffffff
+0x00000020: 00000001 00000001 00000001 00000001 00000001 fffffffe fffffffe 00000001
+0x00000040: fffffffe 00000000 00000000 00000000 00000000 00000000 00000000 00000000
+0x00000060: 00000000 00000000 00000000 00000000 ffffffff ffffffff 00000001 00000000
+invalid mode value encountered 0
+cpsr contains invalid mode value - communication failure
+ThumbEE -- incomplete support
+target state: halted
+target halted in ThumbEE state due to debug-request, current mode: System
+cpsr: 0xffffffff pc: 0xfffffff8
+>
+
+ |
+ FAIL |
+
+
+ | SPD002 |
+ STR912 |
+ ZY1000 |
+ 8MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 8000
+jtag_speed 8 => JTAG clk=8.000000
+8000 kHz
+> halt
+invalid mode value encountered 0
+cpsr contains invalid mode value - communication failure
+Command handler execution failed
+in procedure 'halt' called at file "command.c", line 647
+called at file "command.c", line 361
+Halt timed out, wake up GDB.
+>
+
+ |
+ FAIL |
+
+
+ | SPD003 |
+ STR912 |
+ ZY1000 |
+ 4MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 4000
+jtag_speed 16 => JTAG clk=4.000000
+4000 kHz
+> halt
+> mdw 0 32
+0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+>
+
+ |
+ PASS |
+
+
+ | SPD004 |
+ STR912 |
+ ZY1000 |
+ 2MHz on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 2000
+jtag_speed 32 => JTAG clk=2.000000
+2000 kHz
+> halt
+> mdw 0 32
+0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+>
+
+ |
+ PASS |
+
+
+ | SPD005 |
+ STR912 |
+ ZY1000 |
+ RCLK on normal operation |
+ Reset init the target according to RES002 |
+ Change speed and exercise a memory access over the JTAG, for example
mdw 0x0 32 |
+ The command should run without any errors. If any JTAG checking errors happen, the test failed |
+
+
+> jtag_khz 0
+RCLK - adaptive
+> halt
+> mdw 0 32
+0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+>
+
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | DBG001 |
+ STR912 |
+ ZY1000 |
+ Load is working |
+ Reset init is working, RAM is accesible, GDB server is started |
+ On the console of the OS:
+ arm-elf-gdb test_ram.elf
+ (gdb) target remote ip:port
+ (gdb) load
+ |
+ Load should return without error, typical output looks like:
+
+ Loading section .text, size 0x14c lma 0x0
+ Start address 0x40, load size 332
+ Transfer rate: 180 bytes/sec, 332 bytes/write.
+
+ |
+
+(gdb) load
+Loading section .text, size 0x1a0 lma 0x4000000
+Loading section .rodata, size 0x4 lma 0x40001a0
+Start address 0x4000000, load size 420
+Transfer rate: 29 KB/sec, 210 bytes/write.
+(gdb)
+ |
+ PASS |
+
+
+
+ | DBG002 |
+ STR912 |
+ ZY1000 |
+ Software breakpoint |
+ Load the test_ram.elf application, use instructions from GDB001 |
+ In the GDB console:
+
+ (gdb) monitor gdb_breakpoint_override soft
+ force soft breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0xec: file src/main.c, line 71.
+ (gdb) continue
+ Continuing.
+
+ |
+ The software breakpoint should be reached, a typical output looks like:
+
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+
+ |
+
+
+(gdb) monitor gdb_breakpoint_override soft
+force soft breakpoints
+Current language: auto
+The current source language is "auto; currently asm".
+(gdb) break main
+Breakpoint 1 at 0x4000144: file src/main.c, line 69.
+(gdb) c
+Continuing.
+
+Breakpoint 1, main () at src/main.c:69
+warning: Source file is more recent than executable.
+69 DWORD a = 1;
+Current language: auto
+The current source language is "auto; currently c".
+(gdb)
+
+ |
+ PASS |
+
+
+ | DBG003 |
+ STR912 |
+ ZY1000 |
+ Single step in a RAM application |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
(gdb) step |
+ The next instruction should be reached, typical output:
+
+ (gdb) step
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f0
+ target state: halted
+ target halted in ARM state due to single step, current mode: Abort
+ cpsr: 0x20000097 pc: 0x000000f4
+ 72 DWORD b = 2;
+
+ |
+
+
+ (gdb) step
+ 70 DWORD b = 2;
+ (gdb)
+
+ |
+ PASS |
+
+
+ | DBG004 |
+ STR912 |
+ ZY1000 |
+ Software break points are working after a reset |
+ Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002 |
+ In GDB, type
+ (gdb) monitor reset init
+ (gdb) load
+ (gdb) continue
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to breakpoint, current mode: Supervisor
+ cpsr: 0x000000d3 pc: 0x000000ec
+
+ Breakpoint 1, main () at src/main.c:71
+ 71 DWORD a = 1;
+
+ |
+
+(gdb) monitor reset init
+RCLK - adaptive
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
+Trying to use configured scan chain anyway...
+Bypassing JTAG setup events due to errors
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+cleared protection for sectors 0 through 7 on flash bank 0
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
+(gdb) load
+Loading section .text, size 0x1a0 lma 0x4000000
+Loading section .rodata, size 0x4 lma 0x40001a0
+Start address 0x4000000, load size 420
+Transfer rate: 25 KB/sec, 210 bytes/write.
+(gdb) c
+Continuing.
+
+Breakpoint 1, main () at src/main.c:69
+69 DWORD a = 1;
+(gdb)
+ |
+ PASS |
+
+
+ | DBG005 |
+ STR912 |
+ ZY1000 |
+ Hardware breakpoint |
+ Flash the test_rom.elf application. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset init
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor gdb_breakpoint_override hard
+ force hard breakpoints
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+(gdb) monitor reset init
+RCLK - adaptive
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
+Trying to use configured scan chain anyway...
+Bypassing JTAG setup events due to errors
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+cleared protection for sectors 0 through 7 on flash bank 0
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
+(gdb) load
+Loading section .text, size 0x1a0 lma 0x0
+Loading section .rodata, size 0x4 lma 0x1a0
+Start address 0x0, load size 420
+Transfer rate: 426 bytes/sec, 210 bytes/write.
+(gdb) monitor gdb_breakpoint_override hard
+force hard breakpoints
+(gdb) break main
+Breakpoint 1 at 0x144: file src/main.c, line 69.
+(gdb) continue
+Continuing.
+Note: automatically using hardware breakpoints for read-only addresses.
+
+Breakpoint 1, main () at src/main.c:69
+warning: Source file is more recent than executable.
+69 DWORD a = 1;
+Current language: auto
+The current source language is "auto; currently c".
+(gdb)
+
+ |
+ PASS |
+
+
+ | DBG006 |
+ STR912 |
+ ZY1000 |
+ Hardware breakpoint is set after a reset |
+ Follow the instructions to flash and insert a hardware breakpoint from DBG005 |
+ In GDB, type
+
+ (gdb) monitor reset
+ (gdb) monitor reg pc 0x100000
+ pc (/32): 0x00100000
+ (gdb) continue
+
+ where the value inserted in PC is the start address of the application
+ |
+ The breakpoint should be reached, typical output:
+
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+
+ |
+
+
+(gdb) monitor reset init
+RCLK - adaptive
+SRST took 2ms to deassert
+JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)
+JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)
+JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)
+JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)
+Trying to use configured scan chain anyway...
+Bypassing JTAG setup events due to errors
+SRST took 2ms to deassert
+target state: halted
+target halted in ARM state due to debug-request, current mode: Supervisor
+cpsr: 0x000000d3 pc: 0x00000000
+cleared protection for sectors 0 through 7 on flash bank 0
+NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.
+(gdb) c
+Continuing.
+
+Breakpoint 1, main () at src/main.c:69
+69 DWORD a = 1;
+(gdb)
+
+ |
+ PASS |
+
+
+ | DBG007 |
+ STR912 |
+ ZY1000 |
+ Single step in ROM |
+ Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed |
+ Be sure that gdb_memory_map and gdb_flash_program are enabled. In GDB, type
+
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor arm7_9 force_hw_bkpts enable
+ force hardware breakpoints enabled
+ (gdb) break main
+ Breakpoint 1 at 0x100134: file src/main.c, line 69.
+ (gdb) continue
+ Continuing.
+
+ Breakpoint 1, main () at src/main.c:69
+ 69 DWORD a = 1;
+ (gdb) step
+
+ |
+ The breakpoint should be reached, typical output:
+
+ target state: halted
+ target halted in ARM state due to single step, current mode: Supervisor
+ cpsr: 0x60000013 pc: 0x0010013c
+ 70 DWORD b = 2;
+
+ |
+
+ (gdb) c
+Continuing.
+
+Breakpoint 2, main () at src/main.c:69
+69 DWORD a = 1;
+Current language: auto
+The current source language is "auto; currently c".
+(gdb) step
+70 DWORD b = 2;
+(gdb)
+ |
+ PASS |
+
+
+
+
+
+ | ID |
+ Target |
+ Interface |
+ Description |
+ Initial state |
+ Input |
+ Expected output |
+ Actual output |
+ Pass/Fail |
+
+
+ | FLA001 |
+ STR912 |
+ ZY1000 |
+ Flash probe |
+ Reset init is working |
+ On the telnet interface:
+ > flash probe 0
+ |
+ The command should execute without error. The output should state the name of the flash and the starting address. An example of output:
+ flash 'ecosflash' found at 0x01000000
+ |
+
+
+ > flash probe 0
+ flash 'str9x' found at 0x00000000
+ >
+
+ |
+ PASS |
+
+
+ | FLA002 |
+ STR912 |
+ ZY1000 |
+ flash fillw |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash fillw 0x1000000 0xdeadbeef 16
+
+ |
+ The commands should execute without error. The output looks like:
+
+ wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
+
+ To verify the contents of the flash:
+
+ > mdw 0x1000000 32
+ 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+> flash fillw 0x0 0xdeadbeef 16
+wrote 64 bytes to 0x00000000 in 0.020000s (3.125 kb/s)
+> mdw 0 32
+0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+>
+ |
+ PASS |
+
+
+ | FLA003 |
+ STR912 |
+ ZY1000 |
+ Flash erase |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash erase_address 0x1000000 0x20000
+
+ |
+ The commands should execute without error.
+
+ erased address 0x01000000 length 131072 in 4.970000s
+
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.
+
+ > mdw 0x1000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+> flash erase_address 0 0x20000
+erased address 0x00000000 (length 131072) in 1.970000s (64.975 kb/s)
+> mdw 0 32
+0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+>
+ |
+ PASS |
+
+
+ | FLA004 |
+ STR912 |
+ ZY1000 |
+ Entire flash erase |
+ Reset init is working, flash is probed |
+ On the telnet interface
+ > flash erase_address 0x0 0x80000
+
+ |
+ The commands should execute without error.
+
+ erased address 0x01000000 length 8192 in 4.970000s
+
+ To check that the flash has been erased, read at different addresses. The result should always be 0xff.
+
+ > mdw 0x1000000 32
+ 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+
+ |
+
+> flash erase_address 0 0x80000
+ erased address 0x00000000 length 524288 in 1.020000s
+
+> mdw 0 32
+ 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+ |
+ PASS |
+
+
+ | FLA005 |
+ STR912 |
+ ZY1000 |
+ Loading to flash from GDB |
+ Reset init is working, flash is probed, connectivity to GDB server is working |
+ Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf.
+
+ (gdb) target remote ip:port
+ (gdb) monitor reset
+ (gdb) load
+ Loading section .text, size 0x194 lma 0x100000
+ Start address 0x100040, load size 404
+ Transfer rate: 179 bytes/sec, 404 bytes/write.
+ (gdb) monitor verify_image path_to_elf_file
+
+ |
+ The output should look like:
+
+ verified 404 bytes in 5.060000s
+
+ The failure message is something like:
+ Verify operation failed address 0x00200000. Was 0x00 instead of 0x18
+ |
+
+
+(gdb) load
+Loading section .text, size 0x1a0 lma 0x0
+Loading section .rodata, size 0x4 lma 0x1a0
+Start address 0x0, load size 420
+Transfer rate: 425 bytes/sec, 210 bytes/write.
+(gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf
+verified 420 bytes in 0.350000s (1.172 kb/s)
+(gdb)
+
+ |
+ PASS |
+
+
+
+
+
\ No newline at end of file