target: add target async algorithm support
Currently the stm32f1x flash driver uses an asynchronous algorithm as part of the block flash programming. This greatly speeds up flash programming as the target is always running. Moving the async code to the target enable other targets to use this added functionality. Change-Id: I8e53f094c2ef7848a7f86ddb9a35b6edbfc8454a Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/402 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Spencer Oliver
Andreas Fritiofson
parent
dec6b91380
commit
bee7184ce4
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@ -672,23 +672,6 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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}
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};
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/* Set up working area. First word is write pointer, second word is read pointer,
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* rest is fifo data area. */
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uint32_t wp_addr = source->address;
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uint32_t rp_addr = source->address + 4;
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uint32_t fifo_start_addr = source->address + 8;
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uint32_t fifo_end_addr = source->address + source->size;
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uint32_t wp = fifo_start_addr;
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uint32_t rp = fifo_start_addr;
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retval = target_write_u32(target, wp_addr, wp);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, rp_addr, rp);
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if (retval != ERROR_OK)
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return retval;
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init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
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init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
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init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
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@ -704,89 +687,12 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
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armv7m_info.core_mode = ARMV7M_MODE_ANY;
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/* Start up algorithm on target and let it idle while writing the first chunk */
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retval = target_start_algorithm(target, 0, NULL, 5, reg_params,
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stm32x_info->write_algorithm->address,
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0,
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retval = target_run_flash_async_algorithm(target, buffer, count, 2,
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0, NULL,
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5, reg_params,
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source->address, source->size,
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stm32x_info->write_algorithm->address, 0,
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&armv7m_info);
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if (retval != ERROR_OK) {
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LOG_ERROR("error starting stm32x flash write algorithm");
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goto cleanup;
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}
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while (count > 0) {
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retval = target_read_u32(target, rp_addr, &rp);
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if (retval != ERROR_OK) {
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LOG_ERROR("failed to get read pointer");
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break;
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}
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LOG_DEBUG("count 0x%"PRIx32" wp 0x%"PRIx32" rp 0x%"PRIx32, count, wp, rp);
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if (rp == 0) {
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LOG_ERROR("flash write algorithm aborted by target");
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retval = ERROR_FLASH_OPERATION_FAILED;
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break;
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}
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if ((rp & 1) || rp < fifo_start_addr || rp >= fifo_end_addr) {
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LOG_ERROR("corrupted fifo read pointer 0x%"PRIx32, rp);
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break;
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}
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/* Count the number of bytes available in the fifo without
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* crossing the wrap around. Make sure to not fill it completely,
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* because that would make wp == rp and that's the empty condition. */
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uint32_t thisrun_bytes;
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if (rp > wp)
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thisrun_bytes = rp - wp - 2;
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else if (rp > fifo_start_addr)
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thisrun_bytes = fifo_end_addr - wp;
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else
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thisrun_bytes = fifo_end_addr - wp - 2;
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if (thisrun_bytes == 0) {
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/* Throttle polling a bit if transfer is (much) faster than flash
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* programming. The exact delay shouldn't matter as long as it's
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* less than buffer size / flash speed. This is very unlikely to
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* run when using high latency connections such as USB. */
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alive_sleep(10);
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continue;
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}
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/* Limit to the amount of data we actually want to write */
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if (thisrun_bytes > count * 2)
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thisrun_bytes = count * 2;
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/* Write data to fifo */
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retval = target_write_buffer(target, wp, thisrun_bytes, buffer);
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if (retval != ERROR_OK)
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break;
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/* Update counters and wrap write pointer */
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buffer += thisrun_bytes;
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count -= thisrun_bytes / 2;
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wp += thisrun_bytes;
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if (wp >= fifo_end_addr)
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wp = fifo_start_addr;
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/* Store updated write pointer to target */
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retval = target_write_u32(target, wp_addr, wp);
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if (retval != ERROR_OK)
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break;
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}
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if (retval != ERROR_OK) {
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/* abort flash write algorithm on target */
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target_write_u32(target, wp_addr, 0);
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}
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int retval2 = target_wait_algorithm(target, 0, NULL, 5, reg_params,
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0, 10000, &armv7m_info);
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if (retval2 != ERROR_OK) {
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LOG_ERROR("error waiting for stm32x flash write algorithm");
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retval = retval2;
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}
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if (retval == ERROR_FLASH_OPERATION_FAILED) {
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LOG_ERROR("flash write failed at address 0x%"PRIx32,
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@ -805,7 +711,6 @@ static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
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}
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}
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cleanup:
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target_free_working_area(target, source);
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target_free_working_area(target, stm32x_info->write_algorithm);
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@ -796,6 +796,137 @@ done:
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return retval;
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}
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/**
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* Executes a target-specific native code algorithm in the target.
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* It differs from target_run_algorithm in that the algorithm is asynchronous.
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* Because of this it requires an compliant algorithm:
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* see contrib/loaders/flash/stm32f1x.S for example.
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*
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* @param target used to run the algorithm
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*/
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int target_run_flash_async_algorithm(struct target *target,
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uint8_t *buffer, uint32_t count, int block_size,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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uint32_t buffer_start, uint32_t buffer_size,
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uint32_t entry_point, uint32_t exit_point, void *arch_info)
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{
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int retval;
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/* Set up working area. First word is write pointer, second word is read pointer,
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* rest is fifo data area. */
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uint32_t wp_addr = buffer_start;
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uint32_t rp_addr = buffer_start + 4;
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uint32_t fifo_start_addr = buffer_start + 8;
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uint32_t fifo_end_addr = buffer_start + buffer_size;
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uint32_t wp = fifo_start_addr;
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uint32_t rp = fifo_start_addr;
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/* validate block_size is 2^n */
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assert(!block_size || !(block_size & (block_size - 1)));
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retval = target_write_u32(target, wp_addr, wp);
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if (retval != ERROR_OK)
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return retval;
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retval = target_write_u32(target, rp_addr, rp);
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if (retval != ERROR_OK)
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return retval;
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/* Start up algorithm on target and let it idle while writing the first chunk */
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retval = target_start_algorithm(target, num_mem_params, mem_params,
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num_reg_params, reg_params,
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entry_point,
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exit_point,
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arch_info);
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if (retval != ERROR_OK) {
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LOG_ERROR("error starting target flash write algorithm");
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return retval;
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}
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while (count > 0) {
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retval = target_read_u32(target, rp_addr, &rp);
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if (retval != ERROR_OK) {
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LOG_ERROR("failed to get read pointer");
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break;
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}
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LOG_DEBUG("count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32, count, wp, rp);
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if (rp == 0) {
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LOG_ERROR("flash write algorithm aborted by target");
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retval = ERROR_FLASH_OPERATION_FAILED;
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break;
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}
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if ((rp & (block_size - 1)) || rp < fifo_start_addr || rp >= fifo_end_addr) {
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LOG_ERROR("corrupted fifo read pointer 0x%" PRIx32, rp);
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break;
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}
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/* Count the number of bytes available in the fifo without
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* crossing the wrap around. Make sure to not fill it completely,
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* because that would make wp == rp and that's the empty condition. */
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uint32_t thisrun_bytes;
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if (rp > wp)
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thisrun_bytes = rp - wp - block_size;
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else if (rp > fifo_start_addr)
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thisrun_bytes = fifo_end_addr - wp;
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else
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thisrun_bytes = fifo_end_addr - wp - block_size;
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if (thisrun_bytes == 0) {
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/* Throttle polling a bit if transfer is (much) faster than flash
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* programming. The exact delay shouldn't matter as long as it's
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* less than buffer size / flash speed. This is very unlikely to
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* run when using high latency connections such as USB. */
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alive_sleep(10);
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continue;
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}
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/* Limit to the amount of data we actually want to write */
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if (thisrun_bytes > count * block_size)
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thisrun_bytes = count * block_size;
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/* Write data to fifo */
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retval = target_write_buffer(target, wp, thisrun_bytes, buffer);
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if (retval != ERROR_OK)
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break;
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/* Update counters and wrap write pointer */
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buffer += thisrun_bytes;
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count -= thisrun_bytes / block_size;
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wp += thisrun_bytes;
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if (wp >= fifo_end_addr)
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wp = fifo_start_addr;
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/* Store updated write pointer to target */
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retval = target_write_u32(target, wp_addr, wp);
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if (retval != ERROR_OK)
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break;
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}
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if (retval != ERROR_OK) {
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/* abort flash write algorithm on target */
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target_write_u32(target, wp_addr, 0);
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}
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int retval2 = target_wait_algorithm(target, num_mem_params, mem_params,
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num_reg_params, reg_params,
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exit_point,
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10000,
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arch_info);
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if (retval2 != ERROR_OK) {
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LOG_ERROR("error waiting for target flash write algorithm");
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retval = retval2;
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}
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return retval;
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}
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int target_read_memory(struct target *target,
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uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
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@ -442,6 +442,18 @@ int target_wait_algorithm(struct target *target,
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uint32_t exit_point, int timeout_ms,
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void *arch_info);
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/**
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* This routine is a wrapper for asynchronous algorithms.
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*
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*/
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int target_run_flash_async_algorithm(struct target *target,
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uint8_t *buffer, uint32_t count, int block_size,
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int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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uint32_t buffer_start, uint32_t buffer_size,
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uint32_t entry_point, uint32_t exit_point,
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void *arch_info);
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/**
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* Read @a count items of @a size bytes from the memory of @a target at
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* the @a address given.
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