diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c
index a3d68a91f..4c1667d8d 100644
--- a/src/target/riscv/batch.c
+++ b/src/target/riscv/batch.c
@@ -125,15 +125,20 @@ int riscv_batch_run(struct riscv_batch *batch)
 	return ERROR_OK;
 }
 
-void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data)
+void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data,
+	bool read_back)
 {
 	assert(batch->used_scans < batch->allocated_scans);
 	struct scan_field *field = batch->fields + batch->used_scans;
 	field->num_bits = riscv_dmi_write_u64_bits(batch->target);
 	field->out_value = (void *)(batch->data_out + batch->used_scans * DMI_SCAN_BUF_SIZE);
-	field->in_value  = (void *)(batch->data_in  + batch->used_scans * DMI_SCAN_BUF_SIZE);
 	riscv_fill_dmi_write_u64(batch->target, (char *)field->out_value, address, data);
-	riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
+	if (read_back) {
+		field->in_value = (void *)(batch->data_in + batch->used_scans * DMI_SCAN_BUF_SIZE);
+		riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
+	} else {
+		field->in_value = NULL;
+	}
 	batch->last_scan = RISCV_SCAN_TYPE_WRITE;
 	batch->used_scans++;
 }
diff --git a/src/target/riscv/batch.h b/src/target/riscv/batch.h
index 9c42ba81e..35384b5e8 100644
--- a/src/target/riscv/batch.h
+++ b/src/target/riscv/batch.h
@@ -59,7 +59,8 @@ bool riscv_batch_full(struct riscv_batch *batch);
 int riscv_batch_run(struct riscv_batch *batch);
 
 /* Adds a DMI write to this batch. */
-void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data);
+void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data,
+	bool read_back);
 
 /* DMI reads must be handled in two parts: the first one schedules a read and
  * provides a key, the second one actually obtains the result of the read -
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index cdb6bc252..a205424d3 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -2188,7 +2188,7 @@ static int sample_memory_bus_v1(struct target *target,
 						sbcs_write |= DM_SBCS_SBREADONDATA;
 					sbcs_write |= sb_sbaccess(config->bucket[i].size_bytes);
 					if (!sbcs_valid || sbcs_write != sbcs) {
-						riscv_batch_add_dmi_write(batch, DM_SBCS, sbcs_write);
+						riscv_batch_add_dmi_write(batch, DM_SBCS, sbcs_write, true);
 						sbcs = sbcs_write;
 						sbcs_valid = true;
 					}
@@ -2197,13 +2197,13 @@ static int sample_memory_bus_v1(struct target *target,
 							(!sbaddress1_valid ||
 							sbaddress1 != config->bucket[i].address >> 32)) {
 						sbaddress1 = config->bucket[i].address >> 32;
-						riscv_batch_add_dmi_write(batch, DM_SBADDRESS1, sbaddress1);
+						riscv_batch_add_dmi_write(batch, DM_SBADDRESS1, sbaddress1, true);
 						sbaddress1_valid = true;
 					}
 					if (!sbaddress0_valid ||
 							sbaddress0 != (config->bucket[i].address & 0xffffffff)) {
 						sbaddress0 = config->bucket[i].address;
-						riscv_batch_add_dmi_write(batch, DM_SBADDRESS0, sbaddress0);
+						riscv_batch_add_dmi_write(batch, DM_SBADDRESS0, sbaddress0, true);
 						sbaddress0_valid = true;
 					}
 					if (config->bucket[i].size_bytes > 4)
@@ -3742,20 +3742,20 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
 						((uint32_t) p[12]) |
 						(((uint32_t) p[13]) << 8) |
 						(((uint32_t) p[14]) << 16) |
-						(((uint32_t) p[15]) << 24));
+						(((uint32_t) p[15]) << 24), false);
 
 			if (size > 8)
 				riscv_batch_add_dmi_write(batch, DM_SBDATA2,
 						((uint32_t) p[8]) |
 						(((uint32_t) p[9]) << 8) |
 						(((uint32_t) p[10]) << 16) |
-						(((uint32_t) p[11]) << 24));
+						(((uint32_t) p[11]) << 24), false);
 			if (size > 4)
 				riscv_batch_add_dmi_write(batch, DM_SBDATA1,
 						((uint32_t) p[4]) |
 						(((uint32_t) p[5]) << 8) |
 						(((uint32_t) p[6]) << 16) |
-						(((uint32_t) p[7]) << 24));
+						(((uint32_t) p[7]) << 24), false);
 			uint32_t value = p[0];
 			if (size > 2) {
 				value |= ((uint32_t) p[2]) << 16;
@@ -3763,7 +3763,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address,
 			}
 			if (size > 1)
 				value |= ((uint32_t) p[1]) << 8;
-			riscv_batch_add_dmi_write(batch, DM_SBDATA0, value);
+			riscv_batch_add_dmi_write(batch, DM_SBDATA0, value, false);
 
 			log_memory_access(address + i * size, value, size, false);
 			next_address += size;
@@ -3967,8 +3967,8 @@ static int write_memory_progbuf(struct target *target, target_addr_t address,
 				setup_needed = false;
 			} else {
 				if (size > 4)
-					riscv_batch_add_dmi_write(batch, DM_DATA1, value >> 32);
-				riscv_batch_add_dmi_write(batch, DM_DATA0, value);
+					riscv_batch_add_dmi_write(batch, DM_DATA1, value >> 32, false);
+				riscv_batch_add_dmi_write(batch, DM_DATA0, value, false);
 				if (riscv_batch_full(batch))
 					break;
 			}