more error handling
git-svn-id: svn://svn.berlios.de/openocd/trunk@1543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
parent
4866c8ed25
commit
bd7d019b56
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@ -932,7 +932,8 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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u32 next_instruction;
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arm11_read_memory_word(arm11, R(PC), &next_instruction);
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if ((arm11_read_memory_word(arm11, R(PC), &next_instruction))!=ERROR_OK)
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return retval;
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/* skip over BKPT */
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if ((next_instruction & 0xFFF00070) == 0xe1200070)
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@ -976,7 +977,8 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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brp[1].address = ARM11_SC7_BCR0;
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brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
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arm11_sc7_run(arm11, brp, asizeof(brp));
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if ((retval=arm11_sc7_run(arm11, brp, asizeof(brp)))!=ERROR_OK)
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return retval;
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/* resume */
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@ -987,7 +989,8 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
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arm11_leave_debug_state(arm11);
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if ((retval=arm11_leave_debug_state(arm11))!=ERROR_OK)
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return retval;
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arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
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@ -1018,7 +1021,8 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
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arm11_sc7_clear_vbw(arm11);
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/* save state */
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arm11_on_enter_debug_state(arm11);
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if((retval = arm11_on_enter_debug_state(arm11))!=ERROR_OK)
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return retval;
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/* restore default state */
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R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
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@ -240,18 +240,18 @@ void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state);
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void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
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void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
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int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
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void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
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int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
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enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
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void arm11_run_instr_data_prepare (arm11_common_t * arm11);
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void arm11_run_instr_data_finish (arm11_common_t * arm11);
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void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
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int arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
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void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
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void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
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void arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
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void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
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void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
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int arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
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int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
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int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
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int arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
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void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
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void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
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@ -271,12 +271,12 @@ typedef struct arm11_sc7_action_s
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function returns. */
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} arm11_sc7_action_t;
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void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
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int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
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/* Mid-level helper functions */
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void arm11_sc7_clear_vbw(arm11_common_t * arm11);
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void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
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void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
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int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
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#endif /* ARM11_H */
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@ -254,7 +254,7 @@ int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
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*
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* \remarks This is a stand-alone function that executes the JTAG command queue.
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*/
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void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
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int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
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{
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arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
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@ -266,11 +266,15 @@ void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
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arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
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jtag_execute_queue();
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int retval;
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
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arm11->last_dscr = dscr;
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return ERROR_OK;
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}
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@ -365,7 +369,7 @@ void arm11_run_instr_data_finish(arm11_common_t * arm11)
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* \param count Number of opcodes to execute
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*
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*/
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void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
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int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
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{
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arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
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@ -379,12 +383,16 @@ void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
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arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
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jtag_execute_queue();
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int retval;
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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if (flag)
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break;
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}
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}
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return ERROR_OK;
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}
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/** Execute one instruction via ITR
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@ -414,7 +422,7 @@ void arm11_run_instr_no_data1(arm11_common_t * arm11, u32 opcode)
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* \param count Number of data words and instruction repetitions
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*
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*/
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void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
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int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
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{
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arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
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@ -439,7 +447,9 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
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Data = *data;
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arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
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jtag_execute_queue();
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int retval;
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
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}
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@ -455,11 +465,15 @@ void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data
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Data = 0;
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arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
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jtag_execute_queue();
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int retval;
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
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}
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while (!Ready);
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return ERROR_OK;
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}
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/** JTAG path for arm11_run_instr_data_to_core_noack
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@ -495,7 +509,7 @@ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
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* \param count Number of data words and instruction repetitions
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*
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*/
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void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
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int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
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{
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arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
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@ -536,7 +550,9 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
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arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
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jtag_execute_queue();
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int retval;
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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size_t error_count = 0;
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@ -551,6 +567,8 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
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if (error_count)
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LOG_ERROR("Transfer errors " ZU, error_count);
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return ERROR_OK;
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}
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@ -565,9 +583,9 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
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* \param data Data word to be passed to the core via DTR
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*
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*/
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void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
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int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
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{
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arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
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return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
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}
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@ -584,7 +602,7 @@ void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
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* \param count Number of data words and instruction repetitions
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*
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*/
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void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
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int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
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{
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arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
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@ -607,7 +625,9 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da
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do
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{
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arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
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jtag_execute_queue();
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int retval;
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
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}
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@ -615,6 +635,8 @@ void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * da
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*data++ = Data;
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}
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return ERROR_OK;
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}
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/** Execute one instruction via ITR
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@ -666,7 +688,7 @@ void arm11_run_instr_data_to_core_via_r0(arm11_common_t * arm11, u32 opcode, u32
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* \param count Number of instructions in the list.
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*
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*/
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void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
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int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
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{
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arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
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@ -706,7 +728,9 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t
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JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
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arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
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jtag_execute_queue();
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int retval;
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if ((retval=jtag_execute_queue())!=ERROR_OK)
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return retval;
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JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
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}
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@ -738,6 +762,8 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t
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{
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JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
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}}
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return ERROR_OK;
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}
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/** Clear VCR and all breakpoints and watchpoints via scan chain 7
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@ -798,17 +824,22 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value)
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* \param result Pointer where to store result
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*
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*/
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void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
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int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
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{
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int retval;
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arm11_run_instr_data_prepare(arm11);
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/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
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arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
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if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK)
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return retval;
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/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
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arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
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if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK)
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return retval;
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arm11_run_instr_data_finish(arm11);
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return ERROR_OK;
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}
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